Tài liệu COMPUTER SYSTEMS ORGANIZATION-2 ppt

2 COMPUTER SYSTEMS ORGANIZATION Central processing unit (CPU) Control unit Arithmetic logical unit (ALU) I/O devices Registers … … Main memory Disk Printer Bus Figure 2-1 The organization of a simple computer with one CPU and two I/O devices A+B A Registers B A B ALU input register ALU input bus ALU A+B ALU output register Figure 2-2 The data path of a typical von Neumann machine public class Interp { static int PC; static int AC; static int instr; static int instr3type; static int data3loc; static int data; static boolean run3bit = true; // program counter holds address of next instr // the accumulator, a register for doing arithmetic // a holding register for the current instruction // the instruction type (opcode) // the address of the data, or −1 if none // holds the current operand // a bit that can be turned off to halt the machine public static void interpret(int memory[ ], int starting3address) { // This procedure interprets programs for a simple machine with instructions having // one memory operand The machine has a register AC (accumulator), used for // arithmetic The ADD instruction adds am integer in memory to the AC, for example // The interpreter keeps running until the run bit is turned off by the HALT instruction // The state of a process running on this machine consists of the memory, the // program counter, the run bit, and the AC The input parameters consist of // of the memory image and the starting address PC = starting 3address; while (run3bit) { instr = memory[PC]; // fetch next instruction into instr PC = PC + 1; // increment program counter instr3type = get3instr3type(instr); // determine instruction type data3loc = find3data(instr, instr3type); // locate data (−1 if none) if (data3loc >= 0) // if data3loc is −1, there is no operand data = memory[data 3loc]; // fetch the data execute(instr 3type, data); //execute instruction } } private static int get3instr3type(int addr) { } private static int find3data(int instr, int type) { } private static void execute(int type, int data){ } } Figure 2-3 An interpreter for a simple computer (written in Java) S1 S2 S3 S4 S5 Instruction fetch unit Instruction decode unit Operand fetch unit Instruction execution unit Write back unit (a) S1: S2: 6 S3: S4: S5: Time (b) … Figure 2-4 (a) A five-stage pipeline (b) The state of each stage as a function of time Nine clock cycles are illustrated S1 Instruction fetch unit S2 S3 S4 S5 Instruction decode unit Operand fetch unit Instruction execution unit Write back unit Instruction decode unit Operand fetch unit Instruction execution unit Write back unit Figure 2-5 (a) Dual five-stage pipelines with a common instruction fetch unit S4 ALU ALU S1 S2 S3 Instruction fetch unit Instruction decode unit Operand fetch unit S5 LOAD Write back unit STORE Floating point Figure 2-6 A superscalar processor with five functional units Control unit Broadcasts instructions × Processor/memory grid Processor Memory Figure 2-7 An array processor of the ILLIAC IV type Local memories Shared memory CPU CPU CPU CPU Shared memory CPU CPU CPU CPU Bus (a) Bus (b) Figure 2-8 (a) A single-bus multiprocessor (b) A multicomputer with local memories Address Address Cell Address 0 1 2 3 4 5 6 16 bits 7 (c) 12 bits (b) 10 11 bits (a) Figure 2-9 Three ways of organizing a 96-bit memory ... I/O devices Registers … … Main memory Disk Printer Bus Figure 2-1 The organization of a simple computer with one CPU and two I/O devices A+B A Registers B A B ALU input register ALU input bus... } private static void execute(int type, int data){ } } Figure 2-3 An interpreter for a simple computer (written in Java) S1 S2 S3 S4 S5 Instruction fetch unit Instruction decode unit Operand... Shared memory CPU CPU CPU CPU Bus (a) Bus (b) Figure 2-8 (a) A single-bus multiprocessor (b) A multicomputer with local memories Address Address Cell Address 0 1 2 3 4 5 6 16 bits 7 (c) 12 bits (b)