2237 dell latitude 1

A B C D E MODEL NAME : Bold_Peak_II (AAE00) PCB NO : LA-C321P (DAA000A6000) BOM P/N : 1 Dell/Compal Confidential 2 ZZZ1 PCB_LA-C321P_MB Schematic Document Bold Peak2 (Skylake Y) 3 2015-07-03 Rev: 0.7 (X06) 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/08 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P01-Cover Page Size A B C D Document Number Rev 0.7(X06) LA-C321P Date: Wednesday, July 08, 2015 Sheet E of 61 A B eDP Panel 12.5" FHD, UHD C eDP 1.3 (4 LANE) P.23 Touch Screnn/Pen Cntrl Wacom W9006 P.29 D Intel Sky Lake Y (4W) E Channel A LPDDR3, 16Gb/32Gb (x64) per package Memory Bus (LPDDR3) Dual Channel 1600MHz P.18 Channel B LPDDR3, 16Gb/32Gb (x64) per package USB 2.0 P.19 PCIE *1 SMlink M2 2230-Key A Dual Band Wifi/BT USB2.0 P.25 PCIE *1 M2 2230 -Key B WWAN 4GLTE- Intel Telit P.26 M2 2230 uSIM Conn PCIE 2.0 USB3.0 USB3.0 P.26 PCIE*2 M2 2230 -Key M SSD 22x80 Cardreader RTS5242 P.39 USB2.0 DS4 Camera CSIx4 WF Camera 8MP P.29 CSIx2 UF Camera 5MP P.29 HDA Audio Codec ALC3266 P.27 Digital MIC I2C SPI ROM 16M P.31 TPM NPCT650 DP1.2 4xlanes DP1.2 4xlanes DP-MUX P.28 P.32 B USB3.0 SS only Page ~ 22 CC Vbus "THUNDERBOLT" Alpine ridge 4C P.34 DC/DC Interface CKT P.30, 31 Power Circuit DC/DC P.36 ~ 48 PCIe X4 LPC Bus TBT2 USB Type C TBT+ PD I2C SMSC MEC1641 P.46, 47 CC USB2.0 P.40, 41 Alt MODE I2C controller with PDP.43, 44 GPIO's HPD P.35 Vbus B Alt MODE I2C controller with PDP.43, 44 GPIO's Pogo 12pin SB P.34 DP AUX +/- SMBus Proximity SX9306 P.27 "THUNDERBOLT" Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Charger 2014/09/08 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P02-Block Diagram Size B C D Document Number Rev 0.7(X06) LA-C321P Date: A P.38 x chip Keyssa modules A P.45, 47 Int Speaker P.07 DP1.2 4xlanes TBT1 ( iPhone & Nokia compatible) P.24 Smart Amp ALC1006 P.38 DP1.2 4xlanes A Headphone Jack I2S P.29 DB SPI USB Type C TBT+ PD PMIC (Power) P.29 e-Compass + Accelerometer Gyro Magnetometer LSM9DS1TR P.30 Wednesday, July 08, 2015 Sheet E of 61 A B C D E 1 MB DB ALS I2C Tablet side DMIC CM32181 Digital MIC 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/08 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P03-DaughterB block diagram Size Date: A B C D Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet E of 61 A Board ID Table Vcc Board ID 3.3V +/- 5% R 240K +/- 5% 130K +/- 5% 62K +/- 5% 33K +/- 5% 8.2K +/- 5% 4.3K +/- 5% 2K +/- 5% NC C 4700p 4700p 4700p 4700p 4700p 4700p 4700p REV 0.1, 0.2 0.3 0.4 0.5 1.0 USB 3.0 PORT# Pre-EVT1, EVT DVT1 DVT2 PVT DESTINATION Debug WWAN DS4 camera Keyssa DDI PORT# PCH DDI Port Mapping B DP MUX C TBT D PCI EXPRESS SMBUS Control Table USB 2.0 PORT# SOURCE Base BATT Charger TBT XDP SB DESTINATION DESTINATION DESTINATION Lane TBT (Alpine Ridge, Gen3) BASE Lane TBT (Alpine Ridge, Gen3) PCH_SML0CLK PCH_SML0DATA PCH WWAN Lane TBT (Alpine Ridge, Gen3) PCH_SML1CLK PCH_SML1DATA PCH Touch Lane TBT (Alpine Ridge, Gen3) MEM_SMBCLK MEM_SMBDATA PCH BT Lane WWAN (NGFF, Gen3) Debug Lane EC_SMB00_CLK EC_SMB00_DAT MEC1641 EC_SMB01_CLK EC_SMB01_DAT MEC1641 EC_SMB03_CLK EC_SMB03_DAT MEC1641 EC_SMB04_CLK EC_SMB04_DAT MEC1641 EC_SMB05_CLK EC_SMB05_DAT MEC1641 V V Link V Lane 7/ SATA0 SSD (NGFF, Gen3) Lane SSD (NGFF, Gen3) Lane WLAN (NGFF, Gen2) Lane 10 Cardreader (Gen2) V V V 1 CLK DIFFERENTIAL DESTINATION CLKOUT_PCIE1 TBT CLKOUT_PCIE2 Cardreader CLKOUT_PCIE3 NGFF SSD CLKOUT_PCIE4 NGFF (WLAN) CLKOUT_PCIE5 NGFF (WWAN) FLEX CLOCKS DESTINATION CLKOUT_LPC_0 EC LPC CLKOUT_LPC_1 Debug Symbol Note : @ : means de-pop : means Digital Ground : means Analog Ground Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/08 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P04-Notes List Size Document Number Rev 0.7(X06) LA-C321P Date: A Wednesday, July 08, 2015 Sheet of 61 +3VS 1 1 RC6 RC16 RC32 RC33 1 RH1 RC3 D 2 2 @ 2.2K_0201_5% 2.2K_0201_5% 2.2K_0201_5% 2.2K_0201_5% PCH_DDI1_CLK PCH_DDI1_DAT PCH_DDI2_CLK PCH_DDI2_DAT 100K_0201_5% 100K_0201_5% PCH_DDI1_HPD eDP_HPD SOC_DP1_CTRL_DATA(Internal Pull Down): Display Port B Detected = Port B is not detected = Port B is detected SOC_DP2_CTRL_DATA(Internal Pull Down): Display Port C Detected = Port C is not detected = Port C is detected = Port B is not detected (32) (32) (32) (32) (32) (32) (32) (32) DP MUX PS8338B internal pull doewn GPP_E19 (Internal Pull Down): DDPB_CTRLDATA (40) (40) (40) (40) (40) (40) (40) (40) Alpine Ridge A46 C46 C48 A48 B45 D45 B47 D47 PCH_DDI1_N0 PCH_DDI1_P0 PCH_DDI1_N1 PCH_DDI1_P1 PCH_DDI1_N2 PCH_DDI1_P2 PCH_DDI1_N3 PCH_DDI1_P3 A42 C42 A44 C44 B41 D41 B43 D43 TBT_SNK1_ML0_N TBT_SNK1_ML0_P TBT_SNK1_ML1_N TBT_SNK1_ML1_P TBT_SNK1_ML2_N TBT_SNK1_ML2_P TBT_SNK1_ML3_N TBT_SNK1_ML3_P = Port B is detected +1.0VS_VCCIO GPP_E21 (Internal Pull Down): DDPC_CTRLDATA = Port C is not detected TC3 TC4 PCH_DDI1_CLK PCH_DDI1_DAT L6 H6 PCH_DDI2_CLK PCH_DDI2_DAT H4 F4 M5 L4 TP@ TP@ 24.9_0402_1% = Port C is detected A50 +EDP_COM RC4 DDI1_TXN[0] DDI1_TXP[0] DDI1_TXN[1] DDI1_TXP[1] DDI1_TXN[2] DDI1_TXP[2] DDI1_TXN[3] DDI1_TXP[3] EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3] eDP DDI DDI2_TXN[0] DDI2_TXP[0] DDI2_TXN[1] DDI2_TXP[1] DDI2_TXN[2] DDI2_TXP[2] DDI2_TXN[3] DDI2_TXP[3] EDP_AUXN EDP_AUXP EDP_DISP_UTIL DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP GPP_E18/DDPB_CTRLCLK GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3 GPP_E17/EDP_HPD GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA GPP_E22 GPP_E23 EDP_BKLEN EDP_BKLCTL EDP_VDDEN DISPLAY SIDEBANDS EDP_RCOMP H45 F45 J44 G44 J46 G46 H43 F43 eDP_TXN_P0 eDP_TXP_P0 eDP_TXN_P1 eDP_TXP_P1 eDP_TXN_P2 eDP_TXP_P2 eDP_TXN_P3 eDP_TXP_P3 J42 G42 A40 eDP_AUXN eDP_AUXP TP@ TC17 @ RC2 EDP_DISP H41 F41 J40 G40 C11 L10 M7 F6 A7 (23) (23) (23) (23) (23) (23) (23) (23) D 0_0201_5% PCH_DDI1_AUXN PCH_DDI1_AUXP TBT_SNK1_AUX_N TBT_SNK1_AUX_P PCH_DDI1_HPD (23) (23) (32) (32) (40) (40) DP MUX Alpine Ringe PCH_DDI1_HPD (32) TBT_SNK1_HPD (40) SPI1_INT# (23) WLAN_RST# (26) eDP_HPD (23) SPI1_INT# WLAN_RST# eDP_HPD D4 B6 D3 ENBKL PCH_INV_PWM PCH_ENVDD H active From eDP (23) (23) (23) OF 20 RC1 Width 20 mils, Spacing 25 mils, Length < 100 mil SKL-Y-REV1P2_BGA1515 +3V_PRIM +1.0VS_VCCSTG GPP_E23 (Internal Pull Down): DDPD_CTRLDATA SPI1_INT# RC13 1K_0402_5% H_PROCHOT# H_PROCHOT# RC50 Rev0.87 = Port D is detected (36,50,53,54) 10K_0201_5% SKYLAKE_ULX UC1D = Port D is not detected RC8 (36) 499_0402_1% RC11 TC5 TP@ H_PECI @ +1.0V_VCCST C Rev0.87 DISPLAY Functional Strap Definitions R90 PDG_Processor strap CFG[4] should be pulled low to enable embedded DisplayPort* SKYLAKE_ULX UC1A 1K_0402_1% H_THERMTRIP# (36) SIO_EXT_SMI# (36) B4_SLP_S0# RC14 RC15 H49 F49 J48 H47 B62 H_CATERR H_PROCHOT#_R H_THERMTRIP# SKTOCC# 0_0402_5% XDP_BPM#0 XDP_BPM#1 XDP_BPM#2_R TC6 TP@ XDP_BPM#3_R TC7 TP@ H51 J50 F51 G50 E11 M9 BD8 BC11 SIO_EXT_SMI# 49.9_0201_1% CPU_POPIRCOMP 49.9_0201_1% PCH_OPIRCOMP BN17 BP16 CATERR# PECI PROCHOT# THERMTRIP# SKTOCC# PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST# JTAG BPM#[0] BPM#[1] BPM#[2] BPM#[3] PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TRST# JTAGX GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 D53 C54 G48 C59 F47 CPU_XDP_TCK CPU_XDP_TDI CPU_XDP_TDO CPU_XDP_TMS CPU_XDP_TRST# B53 C50 B51 A52 C52 B49 PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST# PCH_JTAGX C PROC_POPIRCOMP PCH_OPIRCOMP CPU MISC OF 20 SKL-Y-REV1P2_BGA1515 +3V_PRIM PU/PD for CPU JTAG signals RC9 RH127 XDP@ 1K_0402_5% SYS_PWROK_XDP XDP CONN 100K_0201_5% 10K_0201_5% SIO_EXT_SMI# +1.0VS_VCCSTG B XDP@ RC25 51_0402_5% CPU_XDP_TDI RC19 2 2 1K_0402_5% CFG0_R XDP@ 51_0402_5% @ 1K_0402_5% XDP_ITP_PMODE CFG0 RC42 XDP@ RC24 51_0402_5% XDP_TDO XDP_TCK XDP_TDI XDP_TMS +1.0V_PRIM CPU_XDP_TRST# RC12 XDP@ 0_0201_5% XDP_TRST# PCH_JTAG_TDO RC49 XDP@ 0_0201_5% XDP_TDO PCH_JTAG_TDI PCH_JTAG_TMS RC51 XDP@ RC52 XDP@ 0_0201_5% 0_0201_5% XDP_TDI XDP_TMS PCH_JTAG_TRST# RC62 XDP@ PCH_JTAGX RC63 XDP@ PCH_JTAG_TCK RC22 XDP@ 0_0201_5% 0_0201_5% 0_0201_5% RC48 0_0402_5% @ @ XDP@ PM_SYS_RESET# RC36 XDP_PRSENT 0.1U_0201_10V6K (9,21,36) (9,53) CFD_PWRBTN#_XDP SIO_PWRBTN# SYS_PWROK (7,30) PCH_SPI_SI XDP_BPM#0 RC65 RC66 RC67 RC68 RC235 XDP@ XDP@ @ XDP@ XDP@ 2 2 XDP_TRST# XDP_TCK XDP_TCK1 (11) (11) XDP_DBRESET# 1K_0402_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0402_5% XDP_PREQ# XDP_PRDY# (17) (17) CFG0 CFG1 (17) (17) CFG2 CFG3 CFG3 RC31 XDP_PREQ# 1K_0402_1% CFG3 XDP_OBS0 XDP_OBS1 XDP_OBS1 CFD_PWRBTN#_XDP SYS_PWROK_XDP XDP_OBS0 SYS_PWROK_XDP (17) (17) CFG4 CFG5 (17) (17) CFG6 CFG7 PWRGD_XDP CFD_PWRBTN#_XDP PU/PD for PCH JTAG signals (7) PCH_SPI_IO2 (9,21,26,27,28,30,33,36,40) PLT_RST# (17) Connect to XDP Conn (Option w/ CPU JTAG) (9,36) +1.0VS_VCCSTG XDP_ITP_PMODE PCH_RSMRST# RC26 XDP@ 1K_0402_5% XDP_PRSENT RC28 1K_0402_5% XDP_RST# XDP_ITP_PMODE RC39 @ CFG0_R SYS_PWROK_XDP SMBDATA SMBCLK XDP_TCK1 XDP_TCK XDP@ 0_0402_5% RC29 XDP@ 1K_0402_5% RC70 XDP@ RC69 XDP@ 0_0201_5% 0_0201_5% +1.0V_XDP B JXDP2 CPU_XDP_TRST# (9,21) 0_0402_5% +1.0V_XDP 0_0402_5% +1.0V_XDP 0.1U_0201_10V6K XDP_DBRESET# @ CC162 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% RC154 XDP_BPM#1 RC237 2 2 CPU_XDP_TCK @ CC161 XDP@ XDP@ XDP@ XDP@ CPU_XDP_TMS 51_0402_5% CPU_XDP_TDO RC40 XDP@ RC23 1 1 51_0402_5% XDP_PREQ# @ XDP@ RC18 RC5 RC27 RC43 RC44 51_0402_5% RC20 CPU_XDP_TDO CPU_XDP_TCK CPU_XDP_TDI CPU_XDP_TMS RH148 WLAN_RST# PWRGD_XDP 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 CFG17 CFG16 CFG8 CFG9 (17) (17) (17) (17) CFG10 CFG11 (17) (17) CFG19 CFG18 (17) (17) CFG12 CFG13 (17) (17) CFG14 CFG15 (17) (17) CLK_XDP_L CLK_XDP#_L XDP_RST# XDP_DBRESET# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRSENT SAMTE_BSH-030-01-L-D-A-TR CONN@ RC37 51_0402_5% PCH_JTAG_TMS RC34 51_0402_5% PCH_JTAG_TDI From CPU A Link to PCH SMB RC38 XDP@ 51_0402_5% RC41 @ 51_0402_5% PCH_JTAGX RC35 @ 51_0402_5% PCH_JTAG_TCK (9) (9) CK_XDP CK_XDP# (7) SMBDATA (7) SMBCLK CLK_XDP_L CLK_XDP#_L footprint "SAMTE_BSH-030-01-L-D-A-TR_60P-S" non-location fear SMBDATA SMBCLK PCH_JTAG_TDO Compal Secret Data Security Classification Issued Date 2014/09/08 Deciphered Date 2015/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A Compal Electronics, Inc P05-SKL Y(1/13) DDI,MSIC,XDP Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet of 61 Non-interleaved Memory D D (18) C M_A_DQ_[0 63] M_A_DQ_0 M_A_DQ_1 M_A_DQ_2 M_A_DQ_3 M_A_DQ_4 M_A_DQ_5 M_A_DQ_6 M_A_DQ_7 M_A_DQ_8 M_A_DQ_9 M_A_DQ_10 M_A_DQ_11 M_A_DQ_12 M_A_DQ_13 M_A_DQ_14 M_A_DQ_15 UC1B AG61 AH60 DDR0_DQ[0] AK62 DDR0_DQ[1] AK60 DDR0_DQ[2] AH62 DDR0_DQ[3] AG63 DDR0_DQ[4] AL61 DDR0_DQ[5] AL63 DDR0_DQ[6] AM60 DDR0_DQ[7] AM62 DDR0_DQ[8] AT60 DDR0_DQ[9] AR61 DDR0_DQ[10] AN61 DDR0_DQ[11] AN63 DDR0_DQ[12] AR63 DDR0_DQ[13] AT62 DDR0_DQ[14] DDR0_DQ[15] M_A_DQ_16 M_A_DQ_17 M_A_DQ_18 M_A_DQ_19 M_A_DQ_20 M_A_DQ_21 M_A_DQ_22 M_A_DQ_23 M_A_DQ_24 M_A_DQ_25 M_A_DQ_26 M_A_DQ_27 M_A_DQ_28 M_A_DQ_29 M_A_DQ_30 M_A_DQ_31 M_A_DQ_32 M_A_DQ_33 M_A_DQ_34 M_A_DQ_35 M_A_DQ_36 M_A_DQ_37 M_A_DQ_38 M_A_DQ_39 M_A_DQ_40 M_A_DQ_41 M_A_DQ_42 M_A_DQ_43 M_A_DQ_44 M_A_DQ_45 M_A_DQ_46 M_A_DQ_47 M_A_DQ_48 M_A_DQ_49 M_A_DQ_50 M_A_DQ_51 M_A_DQ_52 M_A_DQ_53 M_A_DQ_54 M_A_DQ_55 M_A_DQ_56 M_A_DQ_57 M_A_DQ_58 M_A_DQ_59 M_A_DQ_60 M_A_DQ_61 M_A_DQ_62 M_A_DQ_63 AT56 AR55 AN57 AN55 AR57 AT58 AM58 AM56 AL55 AL57 AH58 AH56 AK58 AK56 AG55 AG57 BE55 BC55 BG53 BE53 BC53 BG55 BD52 BF52 BC51 BE51 BC49 BE49 BG51 BG49 BF48 BD48 BJ55 BL55 BJ53 BL53 BN55 BN53 BM52 BK52 BL51 BJ51 BL49 BJ49 BN49 BN51 BK48 BM48 Interleave/Non-lnterleaved DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] B (19) SKYLAKE_ULX DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR3L / LPDDR3 / DDR4 DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[3] DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1] Interleave/Non-lnterleaved DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR0_ALERT# DDR0_PAR DDR CH-A OF 20 DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ DDR_VTT_CNTL BC62 BC60 BA60 BA62 M_A_CK_DDR0_DN M_A_CK_DDR0_DP M_A_CK_DDR1_DN M_A_CK_DDR1_DP BB57 BC58 BE57 AW61 M_A_CKE0 M_A_CKE1 M_A_CKE2 M_A_CKE3 AW63 BJ57 BN61 M_A_CS0_N (18) M_A_CS1_N (18) M_A_ODT0 (18) AW59 AW55 BF62 AV56 AW57 AV58 BA56 BD59 BD61 BG61 BK59 BL62 BJ61 AV60 BN62 BB61 BL61 BM59 BN58 AV62 M_A_CA_0_0 M_A_CA_0_1 M_A_CA_0_2 M_A_CA_0_3 M_A_CA_0_4 M_A_CA_0_5 M_A_CA_0_6 M_A_CA_0_7 M_A_CA_0_8 M_A_CA_0_9 M_A_CA_1_0 M_A_CA_1_1 M_A_CA_1_2 M_A_CA_1_3 M_A_CA_1_4 M_A_CA_1_5 M_A_CA_1_6 M_A_CA_1_7 M_A_CA_1_8 M_A_CA_1_9 BB63 BL57 AJ61 AJ63 AP62 AP60 AP56 AP58 AJ57 AJ55 BD54 BF54 BF50 BD50 BM54 BK54 BK50 BM50 (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) M_A_DQS_DN_0 M_A_DQS_DP_0 M_A_DQS_DN_1 M_A_DQS_DP_1 (18) (18) (18) (18) M_A_DQS_DN_2 M_A_DQS_DP_2 M_A_DQS_DN_3 M_A_DQS_DP_3 M_A_DQS_DN_4 M_A_DQS_DP_4 M_A_DQS_DN_5 M_A_DQS_DP_5 M_A_DQS_DN_6 M_A_DQS_DP_6 M_A_DQS_DN_7 M_A_DQS_DP_7 (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) (18) BG57 BM56 AR53 AN53 AW53 +V_DDR_VREF_CA (20) +V_DDR_0_DQ_VREF (20) Trace width/Spacing >= 20mils +V_DDR_1_DQ_VREF (20) BN47 SKYLAKE_ULX UC1C M_B_DQ_[0 63] Rev0.87 Rev0.87 M_B_DQ_0 M_B_DQ_1 M_B_DQ_2 M_B_DQ_3 M_B_DQ_4 M_B_DQ_5 M_B_DQ_6 M_B_DQ_7 M_B_DQ_8 M_B_DQ_9 M_B_DQ_10 M_B_DQ_11 M_B_DQ_12 M_B_DQ_13 M_B_DQ_14 M_B_DQ_15 M_B_DQ_16 M_B_DQ_17 M_B_DQ_18 M_B_DQ_19 M_B_DQ_20 M_B_DQ_21 M_B_DQ_22 M_B_DQ_23 M_B_DQ_24 M_B_DQ_25 M_B_DQ_26 M_B_DQ_27 M_B_DQ_28 M_B_DQ_29 M_B_DQ_30 M_B_DQ_31 M_B_DQ_32 M_B_DQ_33 M_B_DQ_34 M_B_DQ_35 M_B_DQ_36 M_B_DQ_37 M_B_DQ_38 M_B_DQ_39 M_B_DQ_40 M_B_DQ_41 M_B_DQ_42 M_B_DQ_43 M_B_DQ_44 M_B_DQ_45 M_B_DQ_46 M_B_DQ_47 BC41 interleave / Non-lnterleaved BC39 DDR0_DQ[32]/DDR1_DQ[0] BG41 DDR0_DQ[33]/DDR1_DQ[1] BE39 DDR0_DQ[34]/DDR1_DQ[2] BF42 DDR0_DQ[35]/DDR1_DQ[3] BD42 DDR0_DQ[36]/DDR1_DQ[4] BG39 DDR0_DQ[37]/DDR1_DQ[5] BE41 DDR0_DQ[38]/DDR1_DQ[6] BC43 DDR0_DQ[39]/DDR1_DQ[7] BD46 DDR0_DQ[40]/DDR1_DQ[8] BG43 DDR0_DQ[41]/DDR1_DQ[9] BG45 DDR0_DQ[42]/DDR1_DQ[10] BC45 DDR0_DQ[43]/DDR1_DQ[11] BE43 DDR0_DQ[44]/DDR1_DQ[12] BE45 DDR0_DQ[45]/DDR1_DQ[13] BF46 DDR0_DQ[46]/DDR1_DQ[14] BM28 DDR0_DQ[47]/DDR1_DQ[15] BN27 DDR1_DQ[32]/DDR1_DQ[16] BK28 DDR1_DQ[33]/DDR1_DQ[17] BL25 DDR1_DQ[34]/DDR1_DQ[18] BN25 DDR1_DQ[35]/DDR1_DQ[19] BL27 DDR1_DQ[36]/DDR1_DQ[20] BJ25 DDR1_DQ[37]/DDR1_DQ[21] BJ27 DDR1_DQ[38]/DDR1_DQ[22] BM24 DDR1_DQ[39]/DDR1_DQ[23] BK24 DDR1_DQ[40]/DDR1_DQ[24] BN21 DDR1_DQ[41]/DDR1_DQ[25] BJ23 DDR1_DQ[42]/DDR1_DQ[26] BL23 DDR1_DQ[43]/DDR1_DQ[27] BN23 DDR1_DQ[44]/DDR1_DQ[28] BJ21 DDR1_DQ[45]/DDR1_DQ[29] BL21 DDR1_DQ[46]/DDR1_DQ[30] BN45 DDR1_DQ[47]/DDR1_DQ[31] BM46 DDR0_DQ[48]/DDR1_DQ[32] BL43 DDR0_DQ[49]/DDR1_DQ[33] BK46 DDR0_DQ[50]/DDR1_DQ[34] BN43 DDR0_DQ[51]/DDR1_DQ[35] BL45 DDR0_DQ[52]/DDR1_DQ[36] BJ45 DDR0_DQ[53]/DDR1_DQ[37] BJ43 DDR0_DQ[54]/DDR1_DQ[38] BM42 DDR0_DQ[55]/DDR1_DQ[39] BN41 DDR0_DQ[56]/DDR1_DQ[40] BJ41 DDR0_DQ[57]/DDR1_DQ[41] BN39 DDR0_DQ[58]/DDR1_DQ[42] BK42 DDR0_DQ[59]/DDR1_DQ[43] BL41 DDR0_DQ[60]/DDR1_DQ[44] BL39 DDR0_DQ[61]/DDR1_DQ[45] BJ39 DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47] M_B_DQ_48 M_B_DQ_49 M_B_DQ_50 M_B_DQ_51 M_B_DQ_52 M_B_DQ_53 M_B_DQ_54 M_B_DQ_55 M_B_DQ_56 M_B_DQ_57 M_B_DQ_58 M_B_DQ_59 M_B_DQ_60 M_B_DQ_61 M_B_DQ_62 M_B_DQ_63 BF28 BD28 BG25 BC27 BG27 BE27 BE25 BC25 BF24 BD24 BG21 BC23 BE23 BG23 BC21 BE21 DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] DDR1_CKN[0] DDR1_CKP[0] DDR1_CKN[1] DDR1_CKP[1] DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR3L / LPDDR3 / DDR4 DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_BA[0] /DDR1_CAB[4]/DDR1_BA[0] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[3] DDR1_MA[4] interleave / Non-lnterleaved DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5] DDR CH-B OF 20 DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7] DDR1_ALERT# DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2] BK36 BM36 BD32 BF32 M_B_CK_DDR0_DN M_B_CK_DDR0_DP M_B_CK_DDR1_DN M_B_CK_DDR1_DP BN33 BK32 BG33 BH30 M_B_CKE0 M_B_CKE1 M_B_CKE2 M_B_CKE3 BM30 BJ33 BC35 (19) (19) (19) (19) (19) (19) (19) (19) M_B_CS0_N (19) M_B_CS1_N (19) M_B_ODT0 (19) BK30 BN31 BM32 BL37 BG31 BN37 BJ37 BJ35 BM34 BN35 BG37 BE37 BC37 BF34 BC33 BF30 BD36 BG35 BC31 BF36 M_B_CA_0_0 M_B_CA_0_1 M_B_CA_0_2 M_B_CA_0_3 M_B_CA_0_4 M_B_CA_0_5 M_B_CA_0_6 M_B_CA_0_7 M_B_CA_0_8 M_B_CA_0_9 M_B_CA_1_0 M_B_CA_1_1 M_B_CA_1_2 M_B_CA_1_3 M_B_CA_1_4 M_B_CA_1_5 M_B_CA_1_6 M_B_CA_1_7 M_B_CA_1_8 M_B_CA_1_9 (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) C BJ31 BK34 BD40 BF40 BD44 BF44 BK26 BM26 BM22 BK22 BK44 BM44 BM40 BK40 BD26 BF26 BF22 BD22 BD34 BD30 BP20 BF64 BJ64 BC64 M_B_DQS_DN_0 M_B_DQS_DP_0 M_B_DQS_DN_1 M_B_DQS_DP_1 M_B_DQS_DN_2 M_B_DQS_DP_2 M_B_DQS_DN_3 M_B_DQS_DP_3 M_B_DQS_DN_4 M_B_DQS_DP_4 M_B_DQS_DN_5 M_B_DQS_DP_5 (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) (19) M_B_DQS_DN_6 M_B_DQS_DP_6 M_B_DQS_DN_7 M_B_DQS_DP_7 (19) (19) (19) (19) TP_DDR_DRAM_RST_N TP@ TC16 200_0201_1% DDR_RCOMP_0 RC45 80.6_0201_1% DDR_RCOMP_1 RC46 162_0201_1% DDR_RCOMP_2 RC47 B SKL-Y-REV1P2_BGA1515 SKL-Y-REV1P2_BGA1515 A A Compal Secret Data Security Classification Issued Date 2014/09/08 Deciphered Date 2015/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P06-SKL Y(2/13) DDRIII Size C Date: Compal Electronics, Inc Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet of 61 SKYLAKE_ULX UC1E +3VS Rev0.87 PCH_SPI_CLK PCH_SPI_SO (30) PCH_SPI_CLK (30) PCH_SPI_SO (5,30) PCH_SPI_SI RC72 0_0402_5% PCH_SPI_CLK_R RC71 0_0402_5% (5) PCH_SPI_SI_R PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_CS0# PCH_SPI_IO2 CH43 0.1U_0201_10V6K @EMI@ D (23) (23) (23) (23) (23) (23) (30) SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2# GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT# SPI - FLASH SMBUS, SMLINK GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT# GPP_C6/SML1CLK GPP_C7/SML1DATA GPP_B23/SML1ALERT#/PCHHOT# SPI - TOUCH 1 1 1 RC73 RC75 RC76 RC77 RC80 RC89 SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_IO2 SPI1_IO3 SPI1_CS# PCH_SPI_CS2# AU10 AU12 AT3 AV11 AV13 AU4 AU6 AU8 2 2 2 15_0402_1% 15_0402_1% 15_0402_1% 15_0402_1% 15_0402_1% 15_0402_1% PCH_SPI1_CLK PCH_SPI1_MISO PCH_SPI1_MOSI PCH_SPI1_IO2 PCH_SPI1_IO3 PCH_SPI1_CS# P9 N8 P3 W12 V7 N6 F12 D12 B12 (26) CL_CLK (26) CL_DATA (26) CL_RST# BL10 BN8 SIO_RCIN# IRQ_SERIRQ (36) SIO_RCIN# (36) IRQ_SERIRQ GPP_D1 GPP_D2/SPI1_MISO GPP_D3 GPP_D21 GPP_D22 GPP_D0 GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME#/ESPI_CS# GPP_A14/SUS_STAT#/ESPI_RESET# LPC C LINK CL_CLK CL_DATA CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK GPP_A10/CLKOUT_LPC1 GPP_A8/CLKRUN# GPP_A0/RCIN# GPP_A6/SERIRQ AC12 W6 W8 SMBCLK SMBDATA SMBALERT# W4 AC10 AA6 SML0CLK SML0DATA SML0ALERT# AA4 W10 BB6 SML1_SMBCLK SML1_SMBDAT SML1ALERT# SMBCLK (5) SMBDATA (5) SML1_SMBCLK SML1_SMBDAT BK11 BJ8 BG10 BP5 BP7 BJ6 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# BJ10 BF5 BH11 CLKOUT_LPC0 CLKOUT_LPC1 CLKRUN# RH11 RH12 OF 20 1 from CPU RH13 RH14 RH15 RH181 1 1 2 2 8.2K_0201_5% 10K_0201_5% 8.2K_0201_5% 150K_0402_5% +3V_PRIM Connect EC (21,36) (21,36) (21,36) (21,36) (21,36) 22_0201_5% 22_0201_5% CH41 0.1U_0201_10V6K @EMI@ SKL-Y-REV1P2_BGA1515 (36) (36) CLKRUN# SIO_RCIN# IRQ_SERIRQ SML1ALERT# 1 2 CLK_PCI_MEC (36) CLK_LPC_DEBUG (21) CLKRUN# (36) SML1_SMBCLK RH96 SML1_SMBDAT RH97 SML1ALERT# RH102 1 @ 1K_0201_5% 1K_0201_5% 150K_0402_5% SML0CLK SML0DATA 1 1K_0201_5% 1K_0201_5% RH99 RH100 CH42 0.1U_0201_10V6K @EMI@ to SPI ROM JSPI1 Closed to ROM SPI_CLK_ROM1 RH89 33_0201_1% SPI_PCH_CLK SPI_SO_ROM1 SPI_IO2_ROM1 SPI_SI_ROM1 SPI_IO3_ROM1 RH105 RH106 RH107 RH108 1 1 2 2 SPI_PCH_SO SPI_PCH_IO2 SPI_PCH_SI SPI_PCH_IO3 33_0201_1% 33_0201_1% 33_0201_1% 33_0201_1% PCH_SPI_SI RC54 0_0402_5% SPI_PCH_SI PCH_SPI_SO RC53 0_0402_5% SPI_PCH_SO PCH_SPI_CLK RC55 0_0402_5% SPI_PCH_CLK PCH_SPI_CS0# RC56 0_0402_5% SPI_PCH_CS0# PCH_SPI_IO2 RC57 0_0402_5% SPI_PCH_IO2 PCH_SPI_IO3 RC58 0_0402_5% SPI_PCH_IO3 +3.3V_SPI +3V_PRIM RC59 0_0402_5% SPI ROM FOR ME ( 16MByte ) ROM is Quad SPI C +3.3V_SPI CS# DO WP# GND VCC HOLD#_RESET# CLK DI +3V_PRIM 10 11 12 13 14 15 16 17 18 19 20 SMBCLK SMBDATA 1K_0201_5% 1K_0201_5% 100_0402_5% 1K_0201_5% 1K_0201_5% C W25Q128FVPIQ_WSON8 RH183 1 GND_1 GND_2 CH32 0.1U_0201_10V6K PDG_SUS_STAT#, This signal is asserted by the PCH to indicate that the system will be entering a low power state soon This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes +3.3V_SPI RH90 RH91 RH94 RH95 ACES_50696-0200M-P01 CONN@ DVT2 SPI_IO3_ROM1 SPI_CLK_ROM1 SPI_SI_ROM1 10 11 12 13 14 15 16 17 18 19 20 21 22 U18 SPI_PCH_CS0# SPI_SO_ROM1 SPI_IO2_ROM1 D SPI_PCH_IO2 SPI_PCH_IO3 Functional Strap Definitions +3.3V_SPI U19 @ B SPI_PCH_CS0# SPI_SO_ROM1 SPI_IO2_ROM1 /CS VCC DO(IO1) /HOLD(IO3) /WP(IO2) CLK GND DI(IO0) GPP_C2 (Internal Pull Down): SMBALERT# GPP_C5 (Internal Pull Down): SML0ALERT# = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality) = LPC Is selected for EC = eSPI Is selected for EC SPI_IO3_ROM1 SPI_CLK_ROM1 SPI_SI_ROM1 W25Q128FVSIG_SO8 = Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality) Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS B +3V_PRIM +3V_PRIM Reserve SO8 footprint for BIOS debug conn 2.2K_0201_5% RH101 SMBALERT# 10K_0201_5% @ RH98 SML0ALERT# A A Compal Secret Data Security Classification Issued Date 2014/09/08 Deciphered Date 2015/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P07-SKL Y(3/13) SPI,SMB Size C Date: Compal Electronics, Inc Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet of 61 SKYLAKE_ULX UC1G Rev0.87 internal pull down internal pull down PDG_internal pull down, series-resistors place as closed as codec (40) (24) BJ19 BK18 BK16 BL15 BL17 BL19 V5 BL12 BK14 HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDI0 HDA_RST# PCH_RTD3_USB_PWR_EN HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM AUDIO I2S1_TXD SDIO/SDXC GPP_A17/SD_PWR_EN#/ISH_GP7 GPP_A16/SD_1P8_SEL D TC30 TC31 TC32 TC33 (40) (40) (40) AT13 AT11 AP11 AT5 GPP_F1 GPP_F0 GPP_F2 GPP_F3 V3 V11 TBT_CIO_PLUG_EVENT# PCH_TBT_FORCE_PWR U12 U8 (40) TBT_BATLOW# PCH_RTD3_CIO_PWR_EN (10,24) AV3 SPKR GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3 GPP_G5/SD_CD# GPP_G6/SD_CLK GPP_G7/SD_WP GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD SD_RCOMP GPP_F23 AH9 AH11 AG12 AF9 AF11 AG8 AG10 AE12 GNSS_CTS_RESET_N EMMC_RST_N SSD_RST# TC26 TC23 SSD_RST# (28) SSD_PWR_EN (37) WWAN_OFF# BT_UART_MUX_SEL WWAN_OFF# (27) TC27 BL4 BN4 +3VS SD_PWR_EN (37) NGFF_WWAN_PWREN BF1 SDIO_RCOMP AJ8 GPP_F23 RC60 (37) RH25 RH29 WWAN_OFF# SSD_RST# 200_0402_1% D 10K_0201_5% 10K_0201_5% TC163 GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0 GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1 GPP_B14/SPKR OF 20 SKL-Y-REV1P2_BGA1515 Strap pin HDA_SDO +5VALW ME debug mode , this signal has a weak internal PD L=>security measures defined in the Flash Descriptor will be in effect (default) H=>Flash Descriptor Security will be overridden HDA for AUDIO 2 33_0201_1% 33_0201_1% 33_0201_1% 33_0201_1% UC1I From EC, for enable ME code programing HDA_BIT_CLK HDA_RST# HDA_SYNC HDA_SDOUT (36) 2 2 RH26 Q10B DMN2400UV-7_SOT-563-6 ME_FWP# +3V_PRIM 1 DMN2400UV-7_SOT-563-6 Q10A 1 1 @EMI@ CH40 0.1U_0201_10V6K @EMI@ CH39 0.1U_0201_10V6K @EMI@ CH50 0.1U_0201_10V6K C RH109 RH110 RH111 RH112 HDA_BIT_CLK_L HDA_RST#_L HDA_SYNC_L HDA_SDOUT_L @EMI@ CH49 0.1U_0201_10V6K (24) (24) (24) (24) R1 1M_0201_1% HDA_SDOUT C 1K_0201_5% * Low = Disabled High = Enabled SKYLAKE_ULX +3V_PRIM Rev0.87 (29) (29) (29) (29) (29) (29) (29) (29) SKYCAM_CSI0_D# SKYCAM_CSI0_D SKYCAM_CSI1_D# SKYCAM_CSI1_D SKYCAM_CSI2_D# SKYCAM_CSI2_D SKYCAM_CSI3_D# SKYCAM_CSI3_D H29 F29 F33 H33 J30 G30 J32 G32 D29 B29 C32 A32 C30 A30 D33 B33 (29) (29) (29) (29) SKYCAM_USER_CSI0_D# SKYCAM_USER_CSI0_D SKYCAM_USER_CSI1_D# SKYCAM_USER_CSI1_D B D35 B35 C36 A36 D37 B37 C38 A38 CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3 CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3 CSI2_COMP GPP_D4/FLASHTRIG CSI-2 CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7 H31 F31 D31 B31 C34 A34 D39 B39 A11 N4 SKYCAM_CSI_CLK_D# SKYCAM_CSI_CLK_D (29) (29) SKYCAM_USER_CSI_CLK_D# SKYCAM_USER_CSI_CLK_D RH27 PCH_STROBE_OUT 10K_0201_5% (29) (29) +1.8V_PRIM CSI2_COMP RC64 PCH_STROBE_OUT 100_0201_1% PCH_STROBE_OUT (29) @ RH118 10K_0201_5% GNSS_OFF# RH24 10K_0201_5% PCH_WWAN_WAKE# RH182 100K_0201_5% GNSS_IRQ eMMC GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7 CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11 GPP_F21/EMMC_RCLK GPP_F22/EMMC_CLK GPP_F12/EMMC_CMD EMMC_RCOMP AN12 AP9 AN10 AJ10 AM9 AL12 AJ12 AN8 MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3 GNSS_OFF# GNSS_OFF# (27) PCH_WWAN_WAKE# AL10 AL8 AM11 GNSS_IRQ BC1 EMMC_RCOMP RC61 GNSS_IRQ (27) WWAN_PWR_OFF# (27) (27) B 200_0402_1% OF 20 SKL-Y-REV1P2_BGA1515 Memory Type Configuration Strap pin +1.8V_PRIM @ RH144 10K_0402_5% MEM_CONFIG2 @ RH129 10K_0402_5% @ RH150 10K_0402_5% MEM_CONFIG0 @ RH139 10K_0402_5% @ RH149 10K_0402_5% MEM_CONFIG1 @ RH145 10K_0402_5% @ RH184 10K_0402_5% MEM_CONFIG3 @ RH185 10K_0402_5% DVT1 Pin Name MEM_CONFIG3 MEM Speed 1600 MEM Speed 1866 Pin Name Micron 4G SA00006ZS1L Micron 8G SA000083Z0L Hynix 4G SA00008GC0L Hynix 8G SA00008420L Samsung 4G SA000073T0L Samsung 8G P/N: TBD MEM_CONFIG0 1 MEM_CONFIG1 0 1 0 MEM_CONFIG2 0 0 1 A A Compal Secret Data Security Classification Issued Date 2014/09/08 Deciphered Date 2015/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P08-SKL Y(4/13) HDA,EMMC,SDIO Size C Date: Compal Electronics, Inc Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet of 61 2 SUSCLK 10P_0402_50V8J @ MC1 Reserve for RF please close to UH1 SKYLAKE_ULX UC1J Rev0.87 CLOCK SIGNALS D CLK_PCIE2# CLK_PCIE2 C228 EMI@ 22P_0402_50V8J CLK_PCIE3# C251 EMI@ 22P_0402_50V8J SSD CLK_PCIE3 Cadreader WLAN C268 EMI@ 22P_0402_50V8J C269 EMI@ 22P_0402_50V8J WWAN TBT_REFCLK_100_N TBT_REFCLK_100_P +3VS (40) TBT_CLKREQ_N (33) CLK_PCIE2# (33) CLK_PCIE2 +3VS (33) CLK_REQ2# (28) CLK_PCIE3# (28) CLK_PCIE3 +3VS (28) CLK_REQ3# (26) CLK_PCIE4# (26) CLK_PCIE4 +3VS (26) CLK_REQ4# (27) CLK_PCIE5# (27) CLK_PCIE5 +3VS (27) CLK_REQ5# RH28 10K_0201_5% H35 F35 AV9 CLK_REQ1# J36 G36 BD10 RH30 10K_0201_5% CLK_PCIE2# CLK_PCIE2 CLK_REQ2# RH33 10K_0201_5% CLK_PCIE3# CLK_PCIE3 CLK_REQ3# J38 G38 AV5 CLK_REQ4# H37 F37 AV7 CLK_REQ5# H39 F39 BC5 RH35 10K_0201_5% RH37 10K_0201_5% TC62 BB10 GPP_B5 TP@ CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1# J34 G34 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2# RTCX1 RTCX2 SRTCRST# RTCRST# D 0_0402_5% SUSCLK XTAL24_IN XTAL24_OUT P1 XCLK_BIASREF CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4# RH76 M1 L2 XTAL24_IN XTAL24_OUT CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3# CK_XDP# (5) CK_XDP (5) BA15 GPD8/SUSCLK RH32 XCLK_BIASREF BN19 BP18 PCH_RTCX1 PCH_RTCX2 BH18 BN12 PCH_SRTCRST# RTC_RST# 2.7K_0201_1% RTC_RST# +VCCCLK (26,27,28) @EMI@ CH46 0.1U_0201_10V6K (40) (40) TBT power on reset (21,36) CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5# XTAL24_IN GPP_B5/SRCCLKREQ0# 10 OF 20 XTAL24_OUT SKL-Y-REV1P2_BGA1515 1M_0402_5% RH39 YH1 24MHZ_12PF_7V24000020 0_0201_5% +3VS 100K_0201_5% RESET_OUT# (5,21,26,27,28,30,33,36,40) IN1 O G IN2 PCH_PLTRST# @ RH46 100K_0201_5% (29) UH1 SN74AHC1G08DCKR_SC70-5 CH6 1U_0402_6.3V6K PCH_PLTRST# 10K_0201_5% 10K_0201_5% 10K_0201_5% AC_PRESENT GPD11 BATLOW# RH82 1K_0201_5% EC_WAKE#_L DVT1 CH7 10P_0402_50V8J DVT1 DVT2 PCH_RTCX1 RH48 10M_0402_5% ESR must Rev0.87 SYSTEM POWER MANAGEMENT PCH_PLTRST# SYS_RESET# PCH_RSMRST#_R BB8 H2 BJ12 H_CPUPWRGD_R H_VCCST_PWRGD A62 B61 SYS_PWROK RESET_OUT# PCH_DPWROK_R J1 BP14 BN15 0.01U_0402_16V7K (5,53) (53) (36) (36) (36,40) SYS_PWROK RESET_OUT# PCH_DPWROK ME_SUS_PWR_ACK (36) SUSACK# TP@ PCH_DPWROK SUS_PWR_DN PCIE_WAKE_O# (36) LAN_WAKE# (37) B PCH_RSMRST# RH52 RH53 1 RH54 @ RH56 RH59 RH60 @ RH62 RH63 0_0402_5% 0_0402_5% 0_0402_5% 1 1 10K_0201_5% 0_0402_5% 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% RH77 DVT1 EN_CAM BL6 BF9 SUS_PWR_DN SUSACK#_R BP9 BE15 BC15 BB16 WAKE# EC_WAKE#_L GPD11 GPP_B13/PLTRST# SYS_RESET# RSMRST# GPP_B12/SLP_S0# GPD4/SLP_S3# GPD5/SLP_S4# GPD10/SLP_S5# PROCPWRGD VCCST_PWRGD SLP_SUS# SLP_LAN# GPD9/SLP_WLAN# GPD6/SLP_A# SYS_PWROK PCH_PWROK DSW_PWROK GPP_A13/SUSWARN#/SUSPWRDNACK GPP_A15/SUSACK# WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD GPD3/PWRBTN# GPD1/ACPRESENT GPD0/BATLOW# GPP_A11/PME# INTRUDER# GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT# +1.0V_VCCST BC9 AY14 BF16 BH14 BN10 BP11 BH16 BE17 BF14 BD14 BD16 SIO_SLP_S0#_R RH51 SIO_SLP_SUS#_L 0_0402_5% RH55 SIO_SLP_S0# SIO_SLP_S3# SIO_SLP_S4# SIO_SLP_S5# 0_0402_5% SIO_SLP_SUS# SIO_SLP_WLAN# (36,53) SIO_SLP_WLAN# (36) SIO_SLP_A# (21,36) PBTN_OUT#_R AC_PRESENT_R BATLOW# BF7 BG19 (21,30,36,38,53) (21,36,37,38,40,53) (21,36,38,53) (21) RH57 RH58 TP@TC63 SM_INTRUDER# BC7 BD6 1 1M_0402_5% 0_0201_5% 0_0201_5% SIO_PWRBTN# AC_PRESENT AC_PRESENT RH64 EXT_PWR_GATE# PDG_ internal pull-up resistor, nterna 16 ms de-bounce on the input (5,21,36) (36) +RTCVCC (38) B 11 OF 20 1K_0201_5% RH66 PCH_RSMRST# H_VCCST_PWRGD_R 0_0402_5% PCH_DPWROK @ (53) RH67 RC79 H_VCCST_PWRGD 60.4_0402_1% PDG_DPWROK connect to VccDSW3_3 power rail monitoring circuit to support Deep Sx state.This signal can be tied to RSMRST# for platforms that not support the Deep Sx state.The DSW rails must be stable for at least 10 ms before DPWROK is asserted to PCH @ @ @ @ @ @ @ @ @ @ @ @ @ @ T24 T25 T27 T23 T26 T29 T31 T28 T30 T32 T33 T34 T36 T37 SKL-Y-REV1P2_BGA1515 PLT_RST# PM_SYS_RESET# PCH_RSMRST# H_VCCST_PWRGD SYS_PWROK RESET_OUT# PCH_DPWROK ME_SUS_PWR_ACK SUSACK# PCIE_WAKE_O# RTC_RST# PCH_SRTCRST# SIO_PWRBTN# AC_PRESENT SIO_SLP_S5# T6 SIO_SLP_S3# SIO_SLP_A# SIO_SLP_WLAN# T8 @ T9 @ T10 @ @ +3VALW_DSW PDG_SUSACK#, this signal is driven from the platform EC to PCH to acknowledge that EC has received the SUSWARN# signals and it is preparing to go into DeepSx mode.for at least 10 ms before DPWROK is asserted to PCH RH68 PDG_SLP_SUS#, a low on this signal indicates that PCH is in Deep Sx state and that EC/platform logic does not need to keep the Primary Rails ON 2.2K_0201_5% PBTN_OUT#_R PDG_SLP_A#, This signal is used to control power to devices on the platform in conjunction with the IntelR ME sub-system This signal will be asserted in M-off state If M3 is not supported then SLP_A# will have the same timings as SLP_S3# A A Compal Secret Data Security Classification Issued Date 2014/09/08 Deciphered Date 2015/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P09-SKL Y(5/13) CLK,GPIO Size C Date: Compal Electronics, Inc Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet of 61 SKYLAKE_ULX UC1F Rev0.87 LPSS (37) Strap Pin BC3 AW10 AW6 BB4 Strap Pin BB2 AW12 AW4 AW8 WLAN_PWR_EN GPP_B18 TC70 (26) WLAN_ON (36) SIO_EXT_SCI# (37) TS_EN TC95 D (27) WWAN_RST# (24) PCH_MUTE# (26) BT_ON/OFF# (33) HOST_SD_WP# SIO_EXT_SCI# GPP_B22 WWAN_RST# HOST_SD_WP# AC8 AA8 AA10 AA12 TC81 TC83 SIO_EXT_WAKE# TC87 UART2_RXD UART2_TXD SIO_EXT_WAKE# UART2_CTS AD5 AD7 AD3 AD9 Codec and AMP (25) (25) I2C0_SDA_AUD I2C0_SCL_AUD I2C0_SDA_AUD I2C0_SCL_AUD AD11 AB3 Touch Screen (23) (23) TS_I2C_SDA TS_I2C_SCL TS_I2C_SDA TS_I2C_SCL AB9 AB11 DVT1 Skycam PMIC (36) (29) (29) SKYCAM_I2C_DATA SKYCAM_I2C_CLK AP3 AP7 AP5 AT7 UF CAM (29) UF_I2C_DATA (29) UF_I2C_CLK AN4 AN6 ISH GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI GPP_D9 GPP_D10 GPP_D11 GPP_D12 GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS# 1.8V GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS# GPP_D13/ISH_UART0_RXD/SML0BDATA GPP_D14/ISH_UART0_TXD/SML0BCLK GPP_D15/ISH_UART0_RTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5 Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY#/ISH_GP6 GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL 1.8V P11 T7 T5 T11 WIFI_RF_KILL PCH_GPP_D11 TS_INT# P7 P5 ISH_I2C0_SDA ISH_I2C0_SCL T9 T3 ISH_I2C1_SDA ISH_I2C1_SCL AM7 AT9 GNSS_SDA GNSS_SCL U10 U4 U6 V9 VPRO AC6 AC4 AB7 AB5 BF11 BD2 BJ1 BL3 BJ3 BD4 BJ4 TC69 TS_INT# ISH_I2C0_SDA ISH_I2C0_SCL GNSS_SDA GNSS_SCL (23) +3VS (31) (31) (27) (27) Sensors G, Gyro and eCompass WWAN GNSS WIFI_RF_KILL PCH_GPP_D11 TS_INT# HOST_SD_WP# @ RH119 @ RH120 RC10 RH134 ISH_I2C0_SDA ISH_I2C0_SCL ISH_I2C1_SDA ISH_I2C1_SCL RH131 RH130 RH92 RH93 1 1 DDR_CHA_EN DDR_CHB_EN DDR_CHA_EN DDR_CHB_EN RH140 RH141 RH142 RH143 1 1 2 DVT2 GPP_D16 Strap Pin TC88 DDR_CHA_EN DEBUG_UART_TX (36) DDR_CHB_EN ACCEL_INT1# ACCEL_INT2# (31) (31) AUDIO_PWR_EN 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% @ @ 2 2 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% (37) 11/28 remove ALS interrupt siganal TPM_DET +1.8VS GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL RH70 RH71 1 @ RC81 @ RC82 1 1K_0201_5% 1K_0201_5% GNSS_SDA GNSS_SCL OF 20 2.2K_0201_5% 2.2K_0201_5% SKL-Y-REV1P2_BGA1515 +3V_PRIM +3VS Functional Strap Definitions DVT1 DVT2 @ RC200 49.9K_0201_1% UART2_RXD RC201 49.9K_0201_1% UART2_TXD RC202 10K_0201_5% SIO_EXT_WAKE# I2C0_SDA_AUD I2C0_SCL_AUD 1 1K_0201_5% 1K_0201_5% 49.9K_0201_1% UART2_CTS SIO_EXT_SCI# RC7 10K_0201_5% WWAN_RST# RH128 100K_0201_5% @ RC203 C D 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% TS_I2C_SDA TS_I2C_SCL DVT2.1 @ RH74 GPP_B14 (Internal Pull Down): SPKR @ RH75 C +3V_PRIM TOP Swap Override @ = Disable TOP Swap mode. -> AAE00 Use RC83 100K_0201_5% SPKR (8,24) = Enable TOP Swap Mode GPP_B18 (Internal Pull Down): GSSPIO_MOSI No Reboot = Disable No Reboot mode > AAE00 Use +3V_PRIM RC84 @ 150K_0402_5% GPP_B18 = Enable No Reboot Mode (PCH will disable the TCO Timer system reboot feature) This function is useful when running ITP/XDP GPP_B22 (Internal Pull Down): GSSPI1_MOSI Boot BIOS Strap Bit = SPI Mode > AAE00 Use +3V_PRIM B RC85 RC86 @ 150K_0402_5% GPP_B22 4.7K_0201_5% GPP_D16 B = LPC Mode GPPD16 (Internal Pull Down): +3VS eSPI or LPC @ = LPC is selected for EC > For KB9022/9032 Use = eSPI is selected for EC > For KB9032 Only +3V_PRIM +3V_PRIM vPRO@ RH177 VPRO TPM@ 100K_0402_5% TPM_DET 100K_0402_5% TPM_DET 100K_0402_5% RH146 nvPRO@ RH178 100K_0402_5% RH147 NTPM@ VPRO BOM Optional TPM BOM Optional VPRO VPRO TPM_DET TPM = W/VPRO = W/O VPRO = W/TPM = W/O TPM A A Compal Secret Data Security Classification Issued Date 2014/09/08 Deciphered Date 2015/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P10-SKL Y(6/13) GPIO,LPIO,I2C Size C Date: Compal Electronics, Inc Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet 10 of 61 1 PR139 1M_0402_5% 2 1 2 3 PR109 0_0201_1% G S S PR159 0_0402_5% D C S5C2 CHRGR_VIN PQ108 AON7405_DFN8-5 PC124 0.022U_0402_25V7K PC123 0.022U_0402_25V7K PR141 1M_0402_5% 2 1 4 (36,44,47,48,50) EN_PD_HV_1 G PQ120A DMN66D0LDW-7_SOT363-6 1 1 PR116 100K_0402_1% PR108 100K_0402_1% VCC3V3_TBTA_LDO S D PD103 RB520SM-30T2R_EMD2-2 1 + - O PU100B TLV1702AIDGKR_VSSOP8 PR137 100K_0402_1% VBUS1_ACOK PC126 100P_0402_50V8J (36) A VCC3V3_PD_LDO VCC3V3_TBTB_LDO From TI PD LDO_3V3 PD104 RB520SM-30T2R_EMD2-2 PC120 0.01U_0402_25V7K Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PR138 100K_0402_1% VCC3V3_PD_LDO PC125 220P_0402_50V7K TBTA_DC_SS PC116 100P_0402_50V8J (36) PR126 221K_0402_1% VBUS2_ACOK VCC3V3_PD_LDO 1 O PU100A TLV1702AIDGKR_VSSOP8 PR130 1.8M_0402_1% 2 G PR142 19.1K_0402_1% PR140 200K_0402_1% 2 >18V VCC3V3_PD_LDO PR162 100K_0402_1% PC103 1000P_0402_50V7K S VCC3V3_PD_LDO PQ120B DMN66D0LDW-7_SOT363-6 EN_PD_HV_2 G @ PR160 0_0402_5% DVT2 P - B VBUS2_ACOK PQ109B DMN66D0LDW-7_SOT363-6 P S PR147 0_0402_5% G G D PR112 0_0201_1% PC102 1000P_0402_50V7K @ PR156 0_0201_1% + 2 PR134 100K_0402_1% +3V_PDLDO 2S1P Voltage: Max Typ Min 8.8V 7.6V 6V 2S1P Dischrger Current : 5.9A PR133 100K_0402_1% +3VALW_EC Battery information: D PR115 221K_0402_1% 1 VCC3V3_PD_LDO VCC3V3_PD_LDO TBTB_DC_SS PR136 200K_0402_1% 2 PR117 19.1K_0402_1% >18V @ PR120 100K_0402_1% SMART Battery: 01.BATT+ 02.BATT+ 03.BATT+ 04.CLK_SMB 05.DAT_SMB 06.BATT_PRS# 07.SYS_PRES# 08.GND 09.GND 10.GND DVT2 PC117 220P_0402_50V7K (36) (50) PBAT_PRES# PR161 0_0402_5% PR128 1.8M_0402_1% +3VLDO_BATT PBAT_SMBDAT @ PR123 100_0402_1% (49) G PQ109A DMN66D0LDW-7_SOT363-6 PR113 0_0201_1% (36) SYS_PRE# PR135 0_0402_5% EN_PD_HV_2 non-PD pop pop pop de-pop de-pop de-pop de-pop 2 PBAT_SMBCLK PD de-pop de-pop de-pop pop pop pop pop (36,45,48,50) 2 2 1 PR110 PR113 PR114 PD103 PD104 PD102 PL101 PR122 100_0402_1% CLK_SMB DAT_SMB BATT_PRS# VBUS1_ACOK G PQ110B DMN66D0LDW-7_SOT363-6 PQ110A DMN66D0LDW-7_SOT363-6 2 PR132 100K_0402_1% PC127 0.1U_0402_25V6 EMC PD101 TVNST52302AB0_SOT523-3 EMC PD100 TVNST52302AB0_SOT523-3 EMI PC108 1000P_0402_50V7K @ PR121 100_0402_1% A D PR105 100K_0402_1% JBAT100 1 2 3 4 5 6 7 8 9 10 10 11 GND 12 GND ACES_50278-01001-001 CONN@ AC_DIS For Constant 20V adapter Primary Battery Connector S @ PR110 0_0201_1% TBTB_DC_SS PQ107 AON7405_DFN8-5 PR119 1M_0402_5% PQ112A DCX124EU-7-F_SOT363-6 PR131 0_0402_5% (48) PR144 0_0402_5% PR143 0_0402_5% D EMC PC113 10U_0603_25V6M PC112 0.1U_0402_25V6 EMC PC119 100P_0402_50V8J EMC PC106 1000P_0402_50V7K EMC PC105 0.01U_0402_25V7K EMC PC118 100P_0402_50V8J PQ112B DCX124EU-7-F_SOT363-6 +BATT 2 EMI PC107 0.1U_0402_25V6 @ PR158 100K_0402_1% S4C2 PR167 0_0805_5% B S PD102 RB520SM-30T2R_EMD2-2 PU101 SN74AHC1G08DCKR_SC70-5 PR124 25.5K_0402_1% VBUS2_ACOK PR157 100K_0402_1% @ IN2 EN_PD_HV_1 EMC PL101 HCB2012KF-121T50_0805 DVT2 PR166 0_0805_5% PR127 100K_0402_1% S Fine tune delay time to keep transient high (36,47) +PBATT D PR107 100K_0402_1% G O (36,44,47,48,50) PQ105 SI2303CDS-T1-GE3_SOT23-3 IN1 S PR103 0_0402_5% 2 G PC130 0.1U_0402_25V6 2 1 G PQ104A DMN66D0LDW-7_SOT363-6 D TBTB_DCIN PR165 0_0805_5% 4 1 EN_PD_HV_2 PDLDO PC134 1U_0402_16V6K PWR2_ON EMI @ PC109 2200P_0402_50V7K 2 1 1 P EN @ PR154 100K_0402_1% EN_PD_HV_1 D D 2 PR155 100K_0402_1% GND NC PR146 0_0402_5% G 2 G +3VALW_DSW PC129 0.01U_0402_25V7K PQ104B DMN66D0LDW-7_SOT363-6 PR145 1K_0402_1% PQ115A DMN66D0LDW-7_SOT363-6 TBTB_VBUS PC122 0.022U_0402_25V7K PR106 100K_0402_1% PC132 1U_0402_16V6K PC133 1U_0603_25V6 D D S PQ115B DMN66D0LDW-7_SOT363-6 MUTI_ACIN_TAB Quickly Fast Start (ALW_ON) PU102 RT9069-33GB_SOT23-5 VCC OUT G (36) RB520SM-30T2R_EMD2-2 PR153 100K_0402_1% PR102 100K_0402_1% @ PR148 0_0402_5% +PD_VBUS_B 2 S PC128 0.1U_0402_25V6 PD105 S +PD_VBUS_A +3V_PDLDO G PR152 0_0402_5% C PDLDO PR129 100K_0402_1% RB520SM-30T2R_EMD2-2 PQ114 AO3413_SOT23-3 PR150 0_0402_5% AC_DIS PC121 0.022U_0402_25V7K S D G PC131 0.01U_0402_25V7K +3VALW_DSW PR111 100K_0402_1% PD106 PR151 2K_0402_5% PR118 0_0402_5% (48) (36,47) PR149 100K_0402_1% PR104 1M_0402_5% PWR1_ON 1 PQ111B DCX124EU-7-F_SOT363-6 PQ111A DCX124EU-7-F_SOT363-6 +3V_PDLDO_OUT EMC PC111 10U_0603_25V6M PC110 0.1U_0402_25V6 EMC PC115 100P_0402_50V8J EMC PC100 1000P_0402_50V7K EMC PC101 0.01U_0402_25V7K EMC PC114 100P_0402_50V8J PR125 25.5K_0402_1% CHRGR_VIN PQ101 AON7405_DFN8-5 1 EMC PL100 HCB2012KF-121T50_0805 PQ113 AO3413_SOT23-3 S5C1 TBTA_DC_SS PQ100 AON7405_DFN8-5 PQ103 SI2303CDS-T1-GE3_SOT23-3 TBTA_DCIN TBTA_VBUS +3V_PDLDO S4C1 TBTA_DCIN For E5 45W Adapter test without PD controller D D D S CONN@ JDC1 ACES_50281-00501-001 1 2 3 4 5 GND1 GND2 G P47-PWR_DCIN/BATT CONN/OTP Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet 47 of 61 S1 P-MOSFET PC224 0.022U_0402_25V7K 2 PC232 0.1U_0402_25V6 PR206 1M_0402_5% 1 2 +3VALW_DSW PC212 0.01U_0402_25V7K 2 PR216 1M_0402_5% 1 DVT2 +3VALW_DSW @ @ PR253 100K_0201_1% VBOS @ RT9069-33GB_SOT23-5 @ PR252 100K_0201_1% EN B PR258 100K_0402_1% NC OUT GND @ PC204 1U_0603_25V6 VCC @ PR236 0_0201_1% EN_PD_HV_2 S G PD202 RB520SM-30T2R_EMD2-2 2 PR234 0_0201_1% 2 @ 2 BASE_DET# VBASE Y Y 1.668 1.668 DOCK Y N 0.687 DOCK N Y Y Y X SN74LVC1G02DCKR_SC70-5 DOCK /UNDOCK PC231 1000P_0402_50V7K VTABLET DOCK UNDOCK P.BASE Power X 1.00 1.25 2.2 TABLET Power VTABLET DOCK N 0.02 UNDOCK Y 1.25 A PR230 2M_0402_5% TABLET Power (35,36,48) Undock: BASE_DET# = H Dock-P.Base no power: BASE_DET# = L Dcok-P.Base has power:BASE_DET# = L Dcok-M.Base: BASE_DET# = L PC230 1000P_0402_50V7K 4 PR226 0_0402_5% P O + PU209 PU206A LM393DMR2G_MICRO8 DOCK /UNDOCK @ PR245 560K_0402_5% PU206B LM393DMR2G_MICRO8 G - +3VLDO PC218 0.01U_0402_25V7K PR225 100K_0402_1% PR227 100K_0402_1% PC229 0.22U_0201_6.3V6K PWR2_ON @ PU202 D PC203 1U_0402_16V6K PD201 RB520SM-30T2R_EMD2-2 @ PD205 RB520SM-30T2R_EMD2-2 2 @ PR235 0_0201_1% EN_PD_HV_1 +3V_DD @ PR257 0_0402_5% VBOS PWR1_ON PR233 0_0201_1% +3VALW_DSW - G O 1 PWRPATH_S3# PU207A LM393DMR2G_MICRO8 (36,44,47,50) +3VALW_DSW VDDTAB3 (36,48) PR244 100K_0402_1% O - PC221 0.1U_0201_10V6K P + PC228 0.22U_0201_6.3V6K PWRPATH_S6 PQ205A DMN66D0LDW-7_SOT363-6 PR237 560K_0402_5% 1 2 VDDTAB4 G S +3VALW_DSW PR243 0_0402_5% PR222 49.9K_0402_1% D S PQ205B DMN66D0LDW-7_SOT363-6 + (47) PR229 2M_0402_5% VDDTAB3=0.974V D G PQ210 S TR 2N7002KW 1N SOT323-3 G Low Vth Mos PC214 0.01U_0402_25V7K PR221 15.4K_0402_1% PR251 20K_0402_1% G_S3 2 PQ212 SI2336DS-T1-GE3_SOT23-3 (36) (36,45,47,50) @ PR256 78.7K_0402_1% VDDTAB4=1.471V PR208 100K_0402_1% +3VLDO @ +3V_DD PR220 78.7K_0402_1% PC226 0.022U_0402_25V7K 1 2 (47) A +5VALW B +3VLDO C P S (36) 2 PWRPATH _DD G D PC222 1U_0402_6.3V6K - PR207 100K_0402_1% PC208 0.1U_0402_25V6 G O PU207B LM393DMR2G_MICRO8 delay V- O 1 P - PR213 249K_0402_1% PU203 SN74LVC1G02DCKR_SC70-5 PR214 0_0402_5% PU208 OPA376AIDCKR_SC70-5 + PR219 100K_0402_1% + 9V DETECTION @ PR250 0_0402_5% PR238 0_0201_1% PC207 0.01U_0402_25V7K 1 PR217 422K_0402_1% PC217 0.01U_0402_25V7K PR212 430K_0402_5% 2 1 @ PR254 165K_0402_1% DD +3VLDO Undock: DD = 1.25V Dock-P.Base no power: DD = ~1.03V Dcok-P.Base has power: DD = 1.71V Dcok-M.Base: DD = 0.02V PR210 100K_0402_1% +PWR_SRC_AC +3VALW_DSW PR209 1.8M_0402_1% +3VS @ PQ208 AON7405_DFN8-5 V+ (34) VBOS +3VLDO PR242 0_0402_5% 2 @ PR259 0_0402_5% @ PR240 0_0402_5% @ DVT2 +3VALW_DSW PD204 RB520SM-30T2R_EMD2-2 1 +3VALW_DSW +3VALW_DSW PC205 0.01U_0402_25V7K @ PC206 0.1U_0402_25V6 (36,48) S6 P-MOSFET VBOS PQ207 AON7405_DFN8-5 PC225 0.022U_0402_25V7K +3VALW_DSW PR211 115K_0402_1% PR218 165K_0402_1% P B+ @ PR255 100K_0402_1% PC219 0.1U_0402_25V6 DVT2 PD203 PD3S230L-7_POWERDI323-2 C PR204 1M_0402_5% RT9069-33GB_SOT23-5 S P-MOSFET PU204 SN74AHC1G08DCKR_SC70-5 VBOS PWRPATH_S1# PQ214B D DMN66D0LDW-7_SOT363-6 G @ PR228 0_0402_5% S S3 IN2 2 PR200 1M_0402_5% EN NC +3VLDO PU205 SN74LVC1G02DCKR_SC70-5 PR215 1M_0402_5% OUT GND PC201 1U_0402_16V6K PC200 1U_0603_25V6 VCC PR246 100K_0402_1% O PC220 0.1U_0402_25V6 PWRPATH_S6 PU200 IN1 (36,48) +3V_LDO VBOS S2_Gate-1 G_S1 G_S3 G 5 G PQ206A DMN66D0LDW-7_SOT363-6 S 2 PC211 0.01U_0402_25V7K PR248 0_0402_5% 2 G PC209 0.1U_0402_25V6 PQ206B DMN66D0LDW-7_SOT363-6 @ PR241 560K_0402_5% D +3VALW_DSW D PQ214A DMN66D0LDW-7_SOT363-6 PQ204A DMN66D0LDW-7_SOT363-6 G S PR249 100K_0402_1% PR202 100K_0402_1% D S D DVT2 D S G PR231 0_0402_5% S PU201 SN74LVC1G02DCKR_SC70-5 G PR232 0_0402_5% 2 BASE_DET# D (35,36,48) DMN66D0LDW-7_SOT363-6 G D PR203 100K_0402_1% PQ204B PWRPATH_S1# DPWROK 2 +3VLDO PR247 560K_0402_5% PR223 2K_0402_5% (53) (36,48) PQ211 AO3413_SOT23-3 PR201 100K_0402_1% PC202 0.01U_0402_25V7K 2 G PC215 0.01U_0402_25V7K +3VALW PC213 1U_0402_16V6K PC223 0.022U_0402_25V7K S +3VALW_DSW +3VLDO PR224 100K_0402_1% 1 DVT2 D D +3VLDO PC227 0.1U_0402_25V6 PQ209 AO3413_SOT23-3 +3V_LDO CHRGR_VIN PQ203 AON7405_DFN8-5 DVT2 S2 P-MOSFET VBOS PQ202 AON7405_DFN8-5 PR205 1M_0402_5% VINTAB @ PR239 0_0201_1% PC233 0.1U_0402_25V6 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Date: P48-PWR_Power Switch Document Number LA-C321P Wednesday, July 08, 2015 Sheet Rev 0.7(X06) 48 of 61 D D DVT2 PD301 RB520SM-30T2R_EMD2-2 +3VLDO +3VLDO_BATT B+ PQ300 DMN65D8LW -7_SOT323-3 D G CLR# GND R/CEXT CEXT Q PR305 0_0201_1% 2 (36) SYS_PRE# (47) S PR301 1M_0402_5% DVT2 B 1 2 PR304 820K_0402_1% PU300 SN74LVC1G123DCUR_VSSOP8 A# VCC PR303 100K_0402_5% PR302 100K_0402_5% C 1 1 PR300 1M_0402_5% PD302 RB520SM-30T2R_EMD2-2 C PW R_SW _IN# PC300 1U_0402_16V6K @ PR306 0_0201_1% PR307 0_0201_1% B B Support Storage mode A A 2011/06/02 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2013/10/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: P49-PWR_BATT output 3.3V Document Number Rev 0.7(X06) LA-C321P W ednesday, July 08, 2015 Sheet 49 of 61 D D +PWR_SRC_AC PR401 0_0402_5% GNDA_CHG (5,36,53,54) PBAT_PRES# GNDA_CHG @ PR423 0_0402_5% PR426 0_0402_5% 14 29 PC408 10U_0805_25V6K PC407 10U_0805_25V6K PC406 10U_0805_25V6K PC405 10U_0805_25V6K PC404 10U_0805_25V6K CMPIN NC CMPOUT /BATPRES CELL SRN /BATDRV PWPD BAT 21 Package: 6.7x7.2x1.5 (LxWxH) Idc=5.5A Isat=9A DCR=18.5mohm (Typ.) 20 19 18 PR420 4.02K_0402_1% 17 DVT2 PC432 PC429 330P_0603_50V8 0.1U_0402_25V6 PC430 0.1U_0402_25V6 PC439 10U_0603_25V6M PC438 10U_0603_25V6M PC437 10U_0603_25V6M PC436 10U_0603_25V6M PC419 10U_0603_25V6M PC415 10U_0603_25V6M PC414 10U_0603_25V6M PC441 10U_0603_25V6M @ PC440 10U_0603_25V6M PC434 10U_0805_25V6K @ PC426 10U_0805_25V6K 1 PR418 10K_0402_1% 2BQ24777_REGN PC425 10U_0805_25V6K 2 S2 S2 22 GND EMC PR413 2_1206_5% PMON LODRV PC424 10U_0603_25V6M PL401 1UH_PCME061E-1R0MS_5.5A_20% 10 D1 BQ24777_CSON CHG_LGATE D2/S1 D1 23 D1 CHG_SW 27 BAT_B+ IADP SRP 15 C PR410 0.01_1206_1% BQ24777_CSOP PHASE PC423 0.047U_0603_25V7M 13 PC403 10U_0805_25V6K 1 PC402 EMC 2200P_0402_50V7K EMC PC401 0.1U_0402_25V6 CHG_UGATE D1 ACP ACN HIDRV ACOK /PROCHOT + DVT2 @ PC431 0.1U_0402_25V6 GNDA_CHG GNDA_CHG B PR422 10_0603_1% BQ24777RUYR_WQFN28_4x4 GNDA_CHG (47) 10 CHG_BTS_C 26 PR416 75_0402_1% 16 H_PROCHOT# PR421 1K_0402_1% @ BTST SDA IDCHG PQ400 AON7934_DFN3X3A-8-10 EMC 1BQ24777_REGN B 1 P_SYS PR419 20K_0402_1% I_BATT (36) (36,54) I_ADP 0_0402_5% 0_0402_5% 0_0402_5% PC428 100P_0402_50V8J (36) GNDA_CHG PR412 PR415 PR417 ACDET SCL + DVT2 PR406 2.2_0603_5% 25 CHG_BTS 24 G1 12 + 1U_0603_10V6K REGN S2 11 CMSRC G2 PR407 0_0402_5% PR408 0_0402_5% VCC PC427 100P_0402_50V8J 1 @ CMSRC PC418 BQ24777_REGN CHG_PMIC_SMBCLK +DCIN 28 ACDRV CHG_PMIC_SMBDAT (36,53) PU400 PR414 154K_0402_1% GNDA_CHG GNDA_CHG (36,53) 1BQ24777_REGN GNDA_CHG @ PR429 100K_0402_1% PR409 100K_0402_1% HW_ACAV_IN PC411 0.1U_0402_25V6 2 S GNDA_CHG (36,53) 1 D G @ PQ402B DMN66D0LDW-7_SOT363-6 S @ PQ402A DMN66D0LDW-7_SOT363-6 EN_PD_HV_2 PR411 0_0402_5% PC410 0.1U_0402_25V6 GNDA_CHG PC421 1U_0603_25V6K PC422 0.1U_0402_25V6 G @ PD403 RB520SM-30T2R_EMD2-2 (36,45,47,48) D EN_PD_HV_1 PR405 49.9K_0402_1% @ PD402 RB520SM-30T2R_EMD2-2 (36,44,47,48) PC409 1U_0603_25V6K PR403 10_1206_5% B+ @ PR430 100K_0402_1% VINTAB @ PD404 RB520SM-30T2R_EMD2-2 PR404 200K_0402_1% @ PR428 560K_0402_5% C DVT2 DVT2 PR402 0_0402_5% PC442 33U_B3_16VM_R45M +3VALW PD401 RB520SM-30T2R_EMD2-2 @ CHRGR_VIN @ PC443 33U_B3_16VM_R45M CMSRC @ PC444 33U_B3_16VM_R45M 2 @ BQ2477_CSIP PD400 RB520SM-30T2R_EMD2-2 PR427 4.02K_0402_1% CHRGR_VIN BQ24777_CSIN +PBATT EMC PL400 FBMA-L11-201209-121LMA50T_0805 PR400 0.01_1206_1% PC400 10U_0805_25V6K CHRGR_VIN +PBATT PR424 0_0402_5% +PBATT PC433 1U_0603_25V6K BATDRV# GNDA_CHG QBATT @ PR425 121K_0402_1% GNDA_CHG GNDA_CHG PQ401 AON7405_DFN8-5 +PBATT BAT_B+ BATDRV# A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 Title P50-PWR_Charger_BQ24777 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.7(X06) LA-C321P Date: Wednesday, July 08, 2015 Sheet 50 of 61 EMI @ PC555 2200P_0402_50V7K 1 ILIM4 B+ EMI PL504 HCB2012KF-121T50_0805 A6 LG5 VOUT8 A3 B3 C6 B8 PC524 0.1U_0402_25V6 +1.8VA_S PC539 0.047U_0402_25V7K PR515 120K_0402_1% 2 B9 +5VALW _S ILIM5 VOUT5 PC567 10P_0201_25V8 1 1 @ C @ PJP503 +1.8VA_S JUMP_43X39 DVT2 @ B PR516 0_0402_5% P_AGND PC542 0.1U_0402_25V6 BOOT6 J13 HG6 J14 G1 D1 PR517 0_0402_5% K14 LG6 L14 G2 LG6-1 SW M13 M14 S2 S2 D2/S1 S2 D1 10 D1 D1 PQ502 AON7934_DFN3X3A-8-10 PC549 0.047U_0402_25V7K PR520 71.5K_0402_1% 1 ILIM6 @ +3VALW _S L13 K13 AON7934 Package: SON-3mmx3mm Q1 Control FET Rds(on)=12.4mohm (Vgs=4.5V) Q2 Sync FET Rds(on)=9.1mohm (Vgs=4.5V) BOOT6 HG6 SW6 LG6 PR518 0_0402_5% PGND6_0 PGND6_1 P_AGND ILIM6 GND VOUT6 A DVT2 P_AGND +3VALW +/- 5% TDC 7.32A Peak Current 10.33A OCP 11.93A Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Issued Date Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P51-PWR_BD99992_A Size Document Number Rev 0.7(X06) LA-C321P Date: DVT2 +1.8V_PRIM PL507 2.2UH_1239AS-H-2R2N-P2_1.3A_30% SW LG5 PGND5 1 PGND8_0 PGND8_1 PR511 0_0402_5% EMC @ PC538 1000P_0603_50V7K SW5 A4 B4 BOOT8 S2 B6 SW8_0 SW8_1 C5 1 PR512 0_0402_5% G2 LG5-1 HG5 BOOT8 A7 SW BOOT5 EMC @ PC537 1000P_0603_50V7K A8 HG5 A9 EMC @ PR513 4.7_0805_5% 2 BOOT5 G1 D1 D1 D1 S2 D2/S1 S2 D1 PC523 0.1U_0402_25V6 Package: 2.5x2x1.2 (LxWxH) Idc=1.3A Isat=1.7A DCR=96mohm (Typ.) 2 A5 B5 VIN8_0 VIN8_1 JUMP_43X39 +1.8V_PRIM +/- 5% TDC 0.296A Peak Current 0.423A OCP 0.4884A VOUT4 +3VA_S +3VA_S F12 C13 C14 EMC @ PC516 1000P_0603_50V7K PGND7_0 PGND7_1 +3V_PRIM @ PJP501 2 EMI PC502 0.1U_0402_25V7K 1 SW EMC @ PR504 4.7_0805_5% PGND4_0 PGND4_1 SGND4 PR509 0_0402_5% 2VOUT4 VCCIO_SENSE PL503 1UH_1239AS-H-1R0M-P2_3A_20% LG4 @ PC507 0.1U_0402_25V6 EMI @ PC556 2200P_0402_50V7K VSSIO_SENSE L3 EMI PC520 0.1U_0402_25V7K PR508 0_0402_5% 2SGND4 PC501 10U_0603_25V6M SW7_0 SW7_1 PR501 0_0402_5% PC519 10U_0603_25V6M 2 G2 S2 M1 M2 K3 ILIM5 EMC @ PC548 1000P_0603_50V7K 2 G1 D1 D1 D1 S2 S2 (12) PQ501 AON7934_DFN3X3A-8-10 EMI @ PC554 2200P_0402_50V7K EMI PC541 0.1U_0402_25V7K EMC @ PR519 4.7_0805_5% 1 PC566 22U_0603_6.3V6M PC565 22U_0603_6.3V6M PC564 22U_0603_6.3V6M PC563 22U_0603_6.3V6M PC551 10U_0805_25V6K 1 PC550 10U_0805_25V6K PC518 0.047U_0402_25V7K PR506 430K_0402_5% 2 EMC @ PC517 EMC @ PR503 1000P_0603_50V7K 4.7_0805_5% 2 EMI PC522 0.1U_0402_25V7K EMI @ PC553 2200P_0402_50V7K EMC @ PR514 4.7_0805_5% 1 PC540 10U_0805_25V6K PC561 10U_0603_25V6M PC562 10U_0603_25V6M 1 2 2 2 2 2 A L1 D13 D14 BOOT7 D PC530 22U_0603_6.3V6M PC547 22U_0603_6.3V6M PC546 22U_0603_6.3V6M PC545 22U_0603_6.3V6M PC544 22U_0603_6.3V6M PC543 22U_0603_6.3V6M JUMP_43X118 LG4-1 SW4 F14 +3V_PRIM +/- 5% TDC 0.616A Peak Current 0.88A OCP 1.0614A Package: 2.5x2x1.2 (LxWxH) Idc=3.0A Isat=3.8A DCR=45mohm (Typ.) F13 PC529 22U_0603_6.3V6M +3VALW _S PR502 0_0402_5% LG4 PR510 0_0402_5% PL509 0.47UH_MMD-05ABHR47M-T1L_7A_20% @ PJP504 HG4 BOOT7 K1 SW PC505 1U_0402_16V6K PC528 22U_0603_6.3V6M PL508 HCB2012KF-121T50_0805 +3VALW PC536 22U_0603_6.3V6M B+ Package: 5.7x5.4x1.2 (LxWxH) Idc=7A Isat=11A DCR=13.6mohm (Typ.) PC535 22U_0603_6.3V6M PC534 22U_0603_6.3V6M PC533 22U_0603_6.3V6M PC532 22U_0603_6.3V6M PC531 22U_0603_6.3V6M B J1 HG4 J2 (12) Package: 4.7x4.3x1.5 (LxWxH) Idc=8A Isat=11A DCR=18mohm (Typ.) PVCC7 ILIM4 PL506 0.47UH_MMD-04AE-R47M-M1L_8A_20% 10 +5VALW +/- 5% TDC 4.926A Peak Current 7.037A OCP 8.13A D2/S1 BOOT4 VOUT7 P_AGND PC559 10U_0603_25V6M PC560 10U_0603_25V6M +5VALW_S JUMP_43X118 EMI @ PC552 2200P_0402_50V7K EMI PC504 0.1U_0402_25V7K PC503 10U_0805_25V6K 1 2 PC527 10U_0805_25V6K PC526 10U_0805_25V6K PC525 10U_0805_25V6K 2 D1 K2 E13 E14 PC515 22U_0603_6.3V6M @ PJP502 10 BOOT4 VIN7_0 VIN7_1 PC514 22U_0603_6.3V6M SGND4 @ PR507 100_0201_1% PL505 HCB2012KF-121T50_0805 PVCC4 REG5 PC513 22U_0603_6.3V6M B+ VOUT4 PU500A BD99992GW -E2_UCSP55M5C195 L2 PC506 0.1U_0402_25V6 B+ PC557 22U_0603_6.3V6M +5VALW PQ500 AON7934_DFN3X3A-8-10 EMC PL500 HCB2012KF-121T50_0805 PC558 22U_0603_6.3V6M C PC512 22U_0603_6.3V6M V4_VCCIO GND PC511 22U_0603_6.3V6M +1.0VS_VCCIO_S @ PR505 100_0201_1% PC510 22U_0603_6.3V6M PC509 22U_0603_6.3V6M PC508 22U_0603_6.3V6M +1.0VS_VCCIO_S 2 JUMP_43X79 PR500 0_0402_5% PL502 1UH_PCMB041B-1R0MS_4.2A_20% @ PJP500 PC500 1U_0402_16V6K Package: 4.75x4.2x1.2 (LxWxH) Idc=4.2A Isat=5.2A DCR=43mohm (Typ.) +1.0VS_VCCIO REG5 D +1.0VS_VCCIO +/- 5% TDC 2.03A Peak Current 2.29 A OCP 3.35A B+_PMIC EMC PL501 HCB2012KF-121T50_0805 PC521 10U_0805_25V6K B+ W ednesday, July 08, 2015 Sheet 51 of 61 EMI @ PC649 2200P_0402_50V7K P11 SGND12 N11 +V0.85A_S 2 2 JUMP_43X39 PR604 0_0201_5% SGND12 Package: 2.5x2x1.2 (LxWxH) Idc=1.3A Isat=1.7A DCR=96mohm (Typ.) PVCC10 +1.2V_VDDQ F1 SW10 G1 VIN13_0 VIN13_1 E1 E2 C HG10 PR606 0_0402_5% LG10 H1 H2 VTT_0 VTT_1 VOUT10 VTTS +V_VDDQ_VTT +1.2V_VDDQ @ F3 @ BOOT11 N7 HG11 P7 SW11 P6 @ PC633 0.22U_0402_10V4Z B P_AGND BOOT11 PC637 0.1U_0402_25V6 1 E3 PVCC11 PC634 1U_0402_16V6K PR610 0_0402_5% LG11 LG11-1 P5 G2 N5 PC644 0.047U_0402_25V7K +V_VDDQ_VTT D1 D2 ILIM10 VDDQ M7 M5 C1 C2 H3 N6 S2 S2 PGND10 REG5 G1 D1 D1 D1 D2/S1 S2 D1 PGND13_0 PGND13_1 DVT2 PR609 0_0402_5% 10 LG10 PC630 0.047U_0402_25V7K PR608 150K_0402_1% 2 EMC @ PC629 1000P_0603_50V7K +1.2V_VDDQ_S @ PQ601 AON7934_DFN3X3A-8-10 @ PC621 10U_0603_10V6M SW10 G2 LG10-1 S2 S2 D2/S1 S2 D1 G1 D1 D1 HG10 BOOT10 F2 BOOT10 PC620 0.1U_0402_25V6 +1.0VA_S M6 DVT2 HG11 AON7934: Package: SON-3mmx3mm Q1 Control FET Rds(on)=12.4mohm (Vgs=4.5V) Q2 Sync FET Rds(on)=9.1mohm (Vgs=4.5V) SW11 LG11 PGND11 SGND11 ILIM11 VOUT11 @ A P_AGND Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Issued Date Deciphered Date 2013/10/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: @ PJP601 +V0.85A_S 1 N10 P10 +0.85V_PRIM PL603 2.2UH_1239AS-H-2R2N-P2_1.3A_30% 2 PC605 0.1U_0402_25V6 G2 SGND11 EMC @ PC643 1000P_0603_50V7K +1.0V_PRIM +/- 5% TDC 3.24A Peak Current 3.29A OCP 5.35A EMI PC603 0.1U_0402_25V7K 1 PC602 10U_0603_25V6M 2 SW12 EMC @ PR603 4.7_0805_5% VOUT9 N9 P9 D 1 2 D1 10 PR613 360K_0402_1% A PGND12_0 PGND12_1 VOUT12 PC617 1U_0402_16V6K PQ600 AON7934_DFN3X3A-8-10 EMI @ PC646 2200P_0402_50V7K EMI @ PC648 2200P_0402_50V7K EMC @ PR611 4.7_0805_5% 1 2 2 22U_0603_6.3V6M PC642 PC641 22U_0603_6.3V6M PC640 22U_0603_6.3V6M PC639 22U_0603_6.3V6M PC638 22U_0603_6.3V6M PR612 0_0201_5% SGND111 +1.0VA_S JUMP_43X79 PGND9_0 PGND9_1 PR600 0_0402_5% BOOT12 REG5 G3 PL607 0.47UH_MMD-04AB-R47M-V2_6A_20% @ PJP603 EMI PC636 0.1U_0402_25V7K Package: 4.5x4x1.2 (LxWxH) Idc=6A Isat=6A DCR=19mohm (Typ.) PC635 10U_0805_25V6K 2 B SW12_0 SW12_1 SGND12 P_AGND SW9_0 SW9_1 M9 PC632 22U_0603_6.3V6M B+_PMIC BOOT12 PC631 22U_0603_6.3V6M EMC @ PR607 4.7_0805_5% @ 1 2 2 @ PC628 22U_0603_6.3V6M PC627 22U_0603_6.3V6M PC626 22U_0603_6.3V6M PC625 22U_0603_6.3V6M PC624 22U_0603_6.3V6M PC623 22U_0603_6.3V6M PC622 22U_0603_6.3V6M 2 PL605 0.47UH_MMD-04AB-R47M-V2_6A_20% +1.2V_VDDQ_S +1.0V_PRIM C10 BOOT9 M8 PR605 0_0402_5% 2 JUMP_43X79 EMI PC619 0.1U_0402_25V7K PC618 10U_0805_25V6K 1 @ PJP602 EMI @ PC645 2200P_0402_50V7K +1.8V_MEM_S 1 2 +1.2V_VDDQ A11 B11 PVCC12 V0.85_PRIM +/- 5% TDC 0.77A Peak Current 1.1A OCP 1.27A PC615 22U_0603_6.3V6M C SW9 A12 B12 EMI PL604 HCB2012KF-121T50_0805 Package: 4.5x4x1.2 (LxWxH) Idc=6A Isat=6A DCR=19mohm (Typ.) PC608 0.1U_0402_25V6 PVCC9 N8 P8 PC614 22U_0603_6.3V6M B+ BOOT9 C11 VIN12_0 VIN12_1 REG5 PC613 22U_0603_6.3V6M +1.2V_VDDQ +/- 5% TDC 3.78A Peak Current 5.4A OCP 6.237A VIN9_0 VIN9_1 B+ PC612 22U_0603_6.3V6M PL602 2.2UH_1239AS-H-2R2N-P2_1.3A_30% PC611 22U_0603_6.3V6M PC610 22U_0603_6.3V6M PC609 22U_0603_6.3V6M JUMP_43X39 PC607 1U_0402_16V6K +1.8V_MEM_S EMC @ PR602 4.7_0805_5% 2 EMC @ PC606 1000P_0603_50V7K @ PJP600 PR601 0_0402_5% PU500B BD99992GW-E2_UCSP55M5C195 C12 +1.8V_MEM VIN12 A10 B10 REG5 Package: 2.5x2x1.2 (LxWxH) Idc=1.3A Isat=1.7A DCR=96mohm (Typ.) D VIN9 EMI PC601 0.1U_0402_25V7K 1 +1.8V_MEM +/- 5% TDC 0.294A Peak Current 0.42A OCP 0.485A EMC PL601 HCB2012KF-121T50_0805 PC604 1U_0402_16V6K EMC PL600 HCB2012KF-121T50_0805 EMC @ PC616 1000P_0603_50V7K B+ PC600 10U_0603_25V6M P52-PWR_BD99992_B Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet 52 of 61 B+ TC77 B+ 0.1U_0201_10V6K SIO_SLP_S4# SIO_SLP_S4# SIO_SLP_S3# (9,21,30,36,38) SIO_SLP_S0# V1.8S V3.3S REG33 (36,50) (36,50) CHG_PMIC_SMBCLK PR712 0_0201_1% (36,50) CHG_PMIC_SMBDAT HW _ACAV_IN K8 ACOK N4 P4 REGIN CLK DATA SYS_PWROK ALLSYS_PWRGD VCCST_PWRGD RADPPOS DPWROK PR710 2K_0402_5% PR709 2K_0402_5% E11 E12 E10 F11 RADPNEG PCH_PWROK ECWAKECLK RBATTNEG +3VS PC714 0.1U_0402_25V6 PR717 80.6K_0402_1% VBATTBKUP K10 L8 BATTID PR741 24.9K_0402_1% 1 PC718 0.1U_0402_25V6 NTC_REF PC717 1U_0402_16V6K J10 B+ F10 G10 H10 H9 H12 N2 REG33 PR711 150_0402_1% H13 SYS_PW ROK (5,9) ALLSYS_PW RGD K6 K5 DPW ROK +3VALW D5 +3VALW_EC L7 P_AGND P_AGND PC711 1U_0402_6.3V6K (9) P_AGND +1.0VS_VCCSTG H_PROCHOT# GPIO_VDD2 EC_VCC C7 C8 D8 E8 E7 E6 E5 F5 G5 H5 P_AGND (5,36,50,54) N3 P3 C4 N12 P12 G13 J3 G12 J9 J11 CLK_VDD TEST00 TEST01 TEST21 TEST22 TEST30 TEST31 TEST32 TESTSEL0 TESTSEL1 TESTSEL2 TEST02 TEST10 TEST11 TEST12 TEST20 AGND_0 AGND_1 AGND_2 AGND_3 AGND_4 AGND_5 DGND_0 DGND_1 ADC_GND CLK_GND P_AGND M11 N1 P1 A14 A13 N14 P14 P13 B2 B13 N13 P2 B1 A1 A2 B14 +3VLDO_PMIC K12 VREF G4 H4 J4 K4 B No Use NTC_REF SYSTHERM0 SYSTHERM1 SYSTHERM2 SYSTHERM3 LDO_EN LDO_UVLO_OFF A NO_FAULT PR718 0_0201_1% P_AGND Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Issued Date Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P53-PWR_BD99992_C Size Document Number Rev 0.7(X06) LA-C321P Date: GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO_VDD1 C TC75 AVCC33_1 AVCC33_2 AVCC33_3 AVCC33_4 AVCC33_5 REG33 L11 (9) @ PR714 10K_0402_1% D11 E4 DVCC33 PC710 4.7U_0603_6.3V6M (48) RESET_OUT# L12 PC709 1U_0402_6.3V6K +3VALW (36,54) H_VCCST_PW RGD_R L4 2 M3 C3 G14 M12 D3 F8 PR745 47K_0402_1%_NCP15WB473F03RC P_AGND VDD_V3P3A_RTC LED1 LED2 LED3 LED4 L9 SYSTHERM0 @ PR747 0_0201_1% C9 J6 P_AGND +1.0V_VCCST +1.0VS_VCCSTG PU500D BD99992GW -E2_UCSP55M5C195 MBI No Use P_AGND P_AGND J12 H6 PC703 1U_0402_6.3V6K @ PR715 75_0402_1% have these functions B +1.8VS F9 RBATTPOS PROC_HOT# P_AGND One thermistor signal for dock detect E9 PC702 1U_0402_6.3V6K K11 (36) P_AGND Charger BQ24777 PMIC_INT# PC708 4.7U_0603_6.3V6M +3VALW_DSW A PR746 0_0201_1% PR737 0_0201_1% PR713 0_0201_1% No Use TC79 REG5 REG5 PR738 0_0201_1% G9 +3VALW_DSW P_AGND @ PR829 100K_0402_1% PC713 (9,21,36,38,53) (9,21,36,38,53) (9,21,36,37,38,40) V1.00S TC74 TC73 2 0.1U_0201_10V6K ALW ON TC72 PC707 1U_0402_6.3V6K PC712 1 (36,37) 0_0201_1% 499_0201_1% 1.4K_0201_1% D PC701 0.1U_0402_25V6 PC706 1U_0402_6.3V6K P_AGND C PR736 PR739 PR740 PCH_PW R_EN RTC_RST# V1.8A_EN SLP_SUS# DS3_VREN V5EN V7_EN V12_EN V11_EN V1.8U_2.5U_EN SLP_S4# SLP_S3# DDR_VTT_CTRL SLP_S0# G11 L6 J8 J7 K9 J5 D10 REG33 PC705 1U_0402_6.3V6K (36,53) PCH_PW R_EN SIO_SLP_SUS# EC_RST# PCH_ONOFF_B EC_ON_OFF# BC_ACOK RSMRST# PMIC_INT# PR703 0_0201_1% TC71 VPPID P_AGND (36,53) (9,36) VDCSENSE DDRID 0_0201_1% L10 D6 B7 D7 M10 H7 G7 H8 D9 F6 G6 F4 F7 LOWBATTSENSE H11 PC716 1U_0402_6.3V6K @ PR735 D12 ADRS_SEL H14 1 G8 ENSL VIN 20K_0201_5% M4 PWRBTN_IN 1 L5 PR704 0_0201_1% REG33 PR742 K7 +RTCVCC PR733 0_0201_1% PR700 10K_0402_1% D PU500C BD99992GW -E2_UCSP55M5C195 DDRID: L(0V) > 1.2V (LPDDR3, DDR4) @ PR734 0_0201_1% VPPID (V1.8U_2.5U Output voltage): L(0V) > 1.8V (LPDDR3) BAT_B+ PC700 10U_0805_25V6K REG33 PC704 1U_0402_6.3V6K W ednesday, July 08, 2015 Sheet 53 of 61 CSP1 CSN1 @ PR818 100K_0402_1% H5 @ PR825 100K_0402_1% G5 VGATE H_PROCHOT# (5,36,50,53) (54) C3 PWM2 C7 PR832 0_0402_5% D6 TYP MAX H/S Rds(on) :12.4 mohm , 15.8 mohm L/S Rds(on) :N/A mohm , 11.6 mohm K9 J9 B9 A9 K2 J2 B2 A2 K1 J1 B1 A1 B5 A5 B6 TEST_MODE2 TEST0 PC1245 10U_0603_25V6M TEST1 TEST2 SWBP_0 SWBP_1 PGND_0 PGND_1 TEST3 VCCSENSE B B7 A7 B8 A8 C2 VCCSENSE_1 TEST4 PR821 2K_0402_5% TEST5 TEST6 FB TEST7 PR822 1.6K_0402_1% A3 PC809 390P_0402_50V7K PR823 4.3K_0402_1% +3VALW_DSW TEST8 TEST9 CTRL TEST10 COMP B3 PR824 33K_0402_1% A4 TEST11 TEST12 PC810 150P_0402_50V8J A10 CPU_B+ PR834 200K_0402_1% PC811 22P_0402_50V8J VSSSENSE DVT1 D2 B10 BTBP PC812 150P_0402_50V8J P_AGND_1 TEST13 IMON E4 VSSSENSE_1 TEST14 TEST15 OCP DROOP VCCSENSE_1 PR826 0_0402_5% VSSSENSE_1 D3 PC813 100P_0402_50V8J J10 VIN_0 VIN_1 TEST_MODE1 C4 E6 K10 TEST_MODE0 D5 PR833 200K_0402_1% 2 J3 C J4 P_AGND_1 PR811 2.4K_0402_1% CPU:SKL_Y VCC_core (Base on PDDG rev 0.91) TDC PL1 4W TDC at PL2: 12A ICCmax 16A DC Load line4.7mV/A(TYP))/ 5.9mV/A(MAX) (SKU A (10-layerMotherboard) Icc_Dyn_VID1 16A OCP current 30.87A CSP2 PC807 0.1U_0402_25V6 +VCC_CORE CSN2 PH800 10K_0402_5%_B25/50 4250K +5VALW IINSENSE3 PR809 680_0402_1% 2 IINSENSE1 IINSENSE2 PR808 680_0402_1% 2 S2 S2 10 4.7_0805_5% D1 D1 D1 S2 D1 Package: SON-3mmx3mm Q1 Control FET Rds(on)=12.4mohm (Vgs=4.5V) Q2 Sync FET Rds(on)=9.1mohm (Vgs=4.5V) PR810 2.4K_0402_1% B4 D2/S1 1000P_0603_50V7K C9 +VCC_CORE PL802 0.22UH_PIME051E-R22MS3R805_16A_20% PR837 75_0402_1% J5 Package: 5.75x5.4x1.5 (LxWxH) Idc= 16.8A Isat= 19.5A DCR=3.8mohm (Typ.) Tolerance ±5% PC814 47U_0603_4V6M PC821 33U_B3_16VM_R45M PC820 10U_0805_25V6K EMC @ PC823 0.1U_0402_25V7K EMC @ PC822 2200P_0402_25V7K 1 SOC_SVID_ALERT#_R PR838 0_0402_5% ALERT_B PR820 84.5K_0402_1% PR819 84.5K_0402_1% 2 VSS DRVEN2 PC808 1000P_0402_25V8J K4 2 K6 B D7 C5 PR814 2.4K_0402_1% P_AGND_1 H6 2@ EMC @ PC806 VR_READYS @ PR813 1M_0402_5% PR815 0_0402_5% P_AGND_1 VR_HOT_B RSVD_1 P_AGND_1 1 PR812 0_0402_5% C RSVD_0 D + EMC @ PR807 C8 ALERT_B D8 P_AGND_1 VIN_S PWM1 SDIO DRVEN1 +5VALW P_SYS C6 J8 SCLK G1 K5 G2 K3 SDAT SCLK PU801 PR805 PC804 BD9515NUX-E2_VSON008X2020-8 0_0402_5% 0.47U_0402_25V6K CPUBST1 2 BST CPUDRVH1 VCC PWM DRVH CPUSW1 SW CPUDRVL1 EN CPUDRVL1_1 PGND DRVL PR806 (14) 0_0402_5% PAD PR835 49.9_0402_1% + PQ800 AON7934_DFN3X3A-8-10 VR_EN PR836 10_0402_1% (36,50) G1 1 E8 +5VALW A6 PC803 1U_0402_16V6K SOC_SVID_DAT_R +5VALW PC802 1U_0402_16V6K SOC_SVID_CLK_R (14) VCC3 ALLSYS_PWRGD (14) PVCC1 PR804 0_0402_5% DVT2 PR841 0_0805_5% F5 (36,53,54) VCC5 K8 1 PR803 45.3_0402_1% CPU_B+ PR839 0_0805_5% CPU_B+ P_AGND_1 PR802 100_0402_1% PR840 0_0805_5% PC824 33U_B3_16VM_R45M (54) +1.0V_VCCST D CPU_B+ PR817 47_0402_1% PC801 1U_0402_16V6K P_AGND_1 2 VGATE DVCC3 ALLSYS_PWRGD B+ PR816 47_0402_1% (36,53,54) H_PROCHOT# PR801 100K_0402_1% PC800 1U_0402_16V6K @ PR800 75_0402_1% +1.0VS_VCCSTG +5VALW +3VALW_DSW PU800A BD99991GW-E2_UCSP55M4C99 PR828 33K_0402_1% P_AGND_1 A P_AGND_1 PR830 51K_0402_1% VCCSENSE (14) VSSSENSE (14) PR827 0_0402_5% A PR831 0_0402_5% P_AGND_1 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P54-PWR_BD99991_A Size Document Number Rev 0.7(X06) LA-C321P Date: Wednesday, July 08, 2015 Sheet 54 of 61 CPU_B+ CSPG1 CSNG1 PR905 2.7K_0402_1% E3 F3 DRVENG2 CSPG2 2 EMC @ PC910 0.1U_0402_25V7K EMC @ PC911 2200P_0402_25V7K PH900 10K_0402_5%_B25/50 4250K PC912 22U_0603_6.3V6M PR906 2.4K_0402_1% VCCGT:SKL_Y VCC_GT (Base on PDDG rev 0.91) TDC PL1 4W TDC at PL2: 11A ICCmax 20A DC Load line 4.2mV/A(TYP)/5.7mV/A(MAX) (SKU A (10-layer Motherboard) Icc_Dyn_VID1 20A OCP current 35.28A PR919 0_0402_5% G2 E2 PR920 200K_0402_1% F2 C TYP MAX H/S Rds(on) :12.4 mohm , 15.8 mohm L/S Rds(on) :N/A mohm , 11.6 mohm +VCC_GT CSNG2 PR904 680_0402_1% PC904 0.1U_0402_25V6 +5VALW PR903 680_0402_1% 2 C H2 D +VCC_GT PR907 2.7K_0402_1% PWMG2 EMC @ PC903 1000P_0603_50V7K EMC @ PR902 4.7_0805_5% 10 S2 S2 D1 Package: 5.75x5.4x1.5 (LxWxH) Idc= 16.8A Isat= 19.5A DCR=3.8mohm (Typ.) Tolerance ±5% PL902 0.22UH_PIME051E-R22MS3R805_16A_20% D2/S1 PC817 10U_0805_25V6K PC818 33U_B3_16VM_R45M + D1 D1 D1 G1 H3 H1 S2 PWMG1 PU901 PR900 PC901 BD9515NUX-E2_VSON008X2020-8 0_0402_5% 0.47U_0402_25V6K GTBST1 2 VCC BST GTDRVH1 PWM DRVH GTSW1 SW GTDRVL1 EN GTDRVL1_1 PGND DRVL PR901 PAD 0_0402_5% G2 PU800B BD99991GW-E2_UCSP55M4C99 DRVENG1 DVT2 PQ900 AON7934_DFN3X3A-8-10 D PC818 wanting CIS symbol PC900 1U_0402_16V6K +5VALW PR921 200K_0402_1% D1 PR909 1.6K_0402_1% G3 VSSGTSENSE PC906 22P_0402_50V8J (14) PR914 0_0402_5% PC907 150P_0402_50V8J P_AGND_1 2 PC909 100P_0402_50V8J H4 PR915 33K_0402_1% A (14) VSSGT_SENSE F4 OCPG VCCGT_SENSE C1 VSSGT_SENSE_1 IMONG 1 E1 COMPG PC908 150P_0402_50V8J VSSGT_SENSE_1 PR910 4.3K_0402_1% DVT2 PR911 22K_0402_1% VCCGT_SENSE_1 PR913 0_0402_5% PC905 390P_0402_50V7K FBG B VCCGT_SENSE_1 PR908 2K_0402_5% 2 VCCGTSENSE B A PR917 2K_0402_5% PR918 51K_0402_1% P_AGND_1 P_AGND_1 Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Issued Date Deciphered Date 2013/10/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: P55-PWR_BD99991_B Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet 55 of 61 CSPS G8 1 @ PR1010 4.3K_0402_1% H7 @ PC1008 150P_0402_50V8J P_AGND_1 F7 PR1012 47K_0402_1% P_AGND_1 PC1010 1000P_0402_25V8J PR1022 30K_0402_1% PC1018 10U_0805_25V6K 2 1 PH1000 10KB_0402_5%_ERTJ0ER103J PC1015 22U_0603_6.3V6M PR1005 4.7K_0402_1% VCCSA:SKL_Y VCC_SA (Base on PDDG rev 0.91) TDC PL1 4W TDC at PL2: 4A ICCmax 4A DC Load line 14mV/A(TYP)/17.9mV/A(MAX) (SKU A (10-layer Motherboard) Icc_Dyn_VID1 4A OCP current 7.35A C TYP MAX H/S Rds(on) :12.4 mohm , 15.8 mohm L/S Rds(on) :N/A mohm , 11.6 mohm PC1009 100P_0402_50V8J G6 PH1003 100K_0402_1%_TSM0B104F4251RZ 2 PR1021 30K_0402_1% PH1002 100K_0402_1%_TSM0B104F4251RZ P_AGND_1 P_AGND_1 P_AGND_1 PR1020 30K_0402_1% 1 PR1027 0_0402_5% PR1026 20K_0402_1% 62K_0402_1% P_AGND_1 PR1025 P_AGND_1 PH1001 100K_0402_1%_TSM0B104F4251RZ 2 PR1019 0_0402_5% PR1018 100K_0402_1% PR1017 0_0402_5% PR1016 0_0402_5% PR1015 0_0402_5% P_AGND_1 PC1007 22P_0402_50V8J VSSSA_SENSE_1 B P_AGND_1 PC1006 220P_0402_50V7K H9 ADREF THERM 2 J7 G4 D4 THERMG THERMS F6 FREQ E7 IMAXG IMAXS E9 G9 F9 IMAX VBOOT D9 K7 F1 J6 ADDR AGND_0 AGND_1 OCPS S2 PC1005 330P_0402_50V7K PR1009 5.6K_0402_1% PR1013 75K_0402_1% NC S2 PR1014 5.6K_0402_1% E5 H8 PR1011 10K_0402_1% IMONS PR1003 680_0402_1% VCCSA_SENSE_1 VSSSASENSE PR1002 680_0402_1% D PR1008 560_0402_1% COMPS +VCC_SA PC1004 0.068U_0402_16V7K G7 C FBS F8 PR1006 5.1K_0402_1% PR1007 5.1K_0402_1% VCCSASENSE C10 CSNS S2 SALGS_1 PGNDS PR1004 0_0402_5% 10 EMC @ PC1003 1000P_0603_50V7K SALGS D1 EMC @ PR1001 4.7_0805_5% D10 +5VALW PC1002 1U_0402_16V6K LGS G2 E10 D2/S1 SASWS PVCC3 F10 Package: 5.7x5.4x1.2 (LxWxH) Idc=7A Isat=11A DCR=13.6mohm (Typ.) Tolerance ±5% PL1001 0.47UH_MMD-05ABHR47MET1L_7A_20% D SWS @ PC1017 10U_0805_25V6K EMC @ PC1013 0.1U_0402_25V7K DVT2 D1 D1 SAHGS G10 D1 HGS PQ1000 AON7934_DFN3X3A-8-10 G1 BTS PR1000 PC1000 0_0402_5% 0.47U_0402_25V6K H10 SABTS 2 EMC PC1014 2200P_0402_25V7K CPU_B+ PU800C BD99991GW-E2_UCSP55M4C99 B P_AGND_1 VCCSA_SENSE_1 PR1024 0_0402_5% VSSSA_SENSE_1 P_AGND_1 VCCSA_SENSE (15) VSSSA_SENSE (15) PR1028 0_0402_5% PR1029 0_0402_5% P_AGND_1 GND P_AGND_1 P_AGND_1 P_AGND_1 A A Fsw=1MHz for VCC_CORE and VCC_GT, Fsw=850kHz for VCC_SA Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Issued Date Deciphered Date 2013/10/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: P56-PWR_BD99991_C Document Number Rev 0.7(X06) LA-C321P Sheet Wednesday, July 08, 2015 56 of 61 A B C Issued Date Security Classification 2011/06/02 Deciphered Date D @ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 2013/10/28 Compal Secret Data Size Date: @ @ PC1238 0.1U_0201_6.3V6K @ PC1239 0.1U_0201_6.3V6K PC1232 0.1U_0201_6.3V6K @ PC1237 0.1U_0201_6.3V6K PC1109 0.1U_0201_6.3V6K PC1224 0.1U_0201_6.3V6K PC1221 0.1U_0201_6.3V6K PC1108 0.1U_0201_6.3V6K PC1216 0.1U_0201_6.3V6K PC1231 0.1U_0201_6.3V6K @ LA-C321P Wednesday, July 08, 2015 E Sheet PC1175 47U_0603_4V6M @ PC1102 0.1U_0201_6.3V6K 1 PC1165 0.1U_0201_6.3V6K @ PC1227 0.1U_0201_6.3V6K PC1124 0.1U_0201_6.3V6K PC1220 0.1U_0201_6.3V6K PC1217 0.1U_0201_6.3V6K 2 PC1104 0.1U_0201_6.3V6K 2 PC1243 0.1U_0201_6.3V6K PC1236 0.1U_0201_6.3V6K PC1230 0.1U_0201_6.3V6K PC1229 0.1U_0201_6.3V6K PC1228 0.1U_0201_6.3V6K PC1226 0.1U_0201_6.3V6K PC1225 0.1U_0201_6.3V6K 2 PC1105 0.1U_0201_6.3V6K PC1234 0.1U_0201_6.3V6K PC1233 0.1U_0201_6.3V6K PC1103 0.1U_0201_6.3V6K PC1222 0.1U_0201_6.3V6K PC1219 0.1U_0201_6.3V6K PC1101 0.1U_0201_6.3V6K +VCC_GT PC1174 47U_0603_4V6M PC1248 0.1U_0201_6.3V6K 1 @ @ PC1249 0.1U_0201_6.3V6K PC1247 0.1U_0201_6.3V6K @ @ PC1120 0.1U_0201_6.3V6K PC1244 0.1U_0201_6.3V6K @ PC1135 0.1U_0201_6.3V6K PC1123 0.1U_0201_6.3V6K PC1100 0.1U_0201_6.3V6K PC1242 0.1U_0201_6.3V6K 2 PC1122 0.1U_0201_6.3V6K D PC1173 47U_0603_4V6M @ PC1246 0.1U_0201_6.3V6K 1 PC1241 0.1U_0201_6.3V6K PC1223 0.1U_0201_6.3V6K PC1136 0.1U_0201_6.3V6K 2 PC1121 0.1U_0201_6.3V6K PC1240 0.1U_0201_6.3V6K @ @ @ PC1172 47U_0603_4V6M @ PC1107 0.1U_0201_6.3V6K 1 @ @ PC1171 47U_0603_4V6M @ PC1235 0.1U_0201_6.3V6K @ @ @ PC1209 47U_0603_4V6M @ PC1204 0.1U_0201_6.3V6K 2 PC1218 0.1U_0201_6.3V6K @ @ PC1170 47U_0603_4V6M 1 TOP side @ @ PC1208 47U_0603_4V6M @ @ PC1169 47U_0603_4V6M 2 @ @ @ PC1207 47U_0603_4V6M @ PC1106 0.1U_0201_6.3V6K PC1215 0.1U_0201_6.3V6K @ PC1152 1U_0201_6.3V6M @ PC1254 22U_0603_6.3V6M PC1214 0.1U_0201_6.3V6K @ PC1253 22U_0603_6.3V6M @ @ PC1168 47U_0603_4V6M 1 For Layout area PC1213 0.1U_0201_6.3V6K @ PC1156 10U_0402_6.3V6M @ @ PC1203 22U_0603_6.3V6M @ PC1202 22U_0603_6.3V6M Back side PC1151 1U_0201_6.3V6M @ PC1212 0.1U_0201_6.3V6K PC1211 0.1U_0201_6.3V6K @ @ PC1188 47U_0603_4V6M 1 @ @ PC1201 22U_0603_6.3V6M PC1210 0.1U_0201_6.3V6K @ PC1200 22U_0603_6.3V6M PC1193 0.1U_0201_6.3V6K @ PC1199 22U_0603_6.3V6M @ PC1192 0.1U_0201_6.3V6K VCC_SA 1U_0201 * pcs +22U_0603*8 pcs+(Reserve 0.1U_0201*10pcs+22u_0603*2pcs) PC1167 47U_0603_4V6M 2 @ PC1191 0.1U_0201_6.3V6K +VCC_SA PC1198 22U_0603_6.3V6M PC1190 0.1U_0201_6.3V6K Decoupling capacitor all follow Rohm BD99991_REFERENCE_1PHASE_REV1P01 PC1187 47U_0603_4V6M 1 @ @ PC1197 22U_0603_6.3V6M 1 C PC1155 47U_0603_4V6M 2 TOP side @ PC1196 4.7U_0603_25V6K @ PC1195 22U_0603_6.3V6M 2 DVT2 PC1189 1U_0201_6.3V6M PC1148 0.1U_0201_6.3V6K PC1147 0.1U_0201_6.3V6K PC1144 0.1U_0201_6.3V6K PC1141 0.1U_0201_6.3V6K B PC1166 47U_0603_4V6M @ PC1194 22U_0603_6.3V6M @ PC1143 0.1U_0201_6.3V6K PC1140 0.1U_0201_6.3V6K PC1146 0.1U_0201_6.3V6K PC1138 0.1U_0201_6.3V6K @ PC1206 47U_0603_4V6M @ PC1142 0.1U_0201_6.3V6K @ PC1252 10U_0402_6.3V6M PC1131 0.1U_0201_6.3V6K PC1137 0.1U_0201_6.3V6K @ PC1205 47U_0603_4V6M @ PC1139 0.1U_0201_6.3V6K PC1132 0.1U_0201_6.3V6K PC1130 0.1U_0201_6.3V6K PC1134 0.1U_0201_6.3V6K @ PC1251 10U_0402_6.3V6M PC1129 0.1U_0201_6.3V6K PC1113 0.1U_0201_6.3V6K @ PC1250 10U_0402_6.3V6M PC1128 0.1U_0201_6.3V6K PC1145 0.1U_0201_6.3V6K PC1127 0.1U_0201_6.3V6K 1 PC1114 0.1U_0201_6.3V6K 2 PC1111 0.1U_0201_6.3V6K @ PC1185 47U_0603_4V6M PC1117 0.1U_0201_6.3V6K PC1116 0.1U_0201_6.3V6K PC1126 0.1U_0201_6.3V6K PC1118 0.1U_0201_6.3V6K PC1119 0.1U_0201_6.3V6K PC1125 0.1U_0201_6.3V6K PC1133 0.1U_0201_6.3V6K 1 PC1112 0.1U_0201_6.3V6K 2 PC1110 0.1U_0201_6.3V6K @ PC1184 47U_0603_4V6M PC1164 10U_0402_6.3V6M 1 @ PC1183 47U_0603_4V6M PC1163 10U_0402_6.3V6M PC1162 10U_0402_6.3V6M PC1161 10U_0402_6.3V6M PC1160 10U_0402_6.3V6M PC1159 10U_0402_6.3V6M PC1158 10U_0402_6.3V6M 2 PC1115 0.1U_0201_6.3V6K @ PC1182 47U_0603_4V6M PC1181 47U_0603_4V6M PC1180 47U_0603_4V6M PC1179 47U_0603_4V6M 1 +VCC_CORE PC1178 47U_0603_4V6M PC1177 47U_0603_4V6M 2 PC1157 10U_0402_6.3V6M 2 A PC1186 47U_0603_4V6M 2 PC1176 47U_0603_4V6M VCC_CORE 0.1U_0201 * 20 pcs +10U_0402*8cs+47U_0603*12pcs+(Reserve 0.1u_0201*12pcs) VCC_GT 0.1U_0201 * 12 pcs +1U_0201*2 pcs+47U_0603*16pcs+(Reserve 0.1U_0201*40pcs+10u_0402*2pcs) E Back side @ Back side @ @ DVT2 @ TOP side 4 Title Document Number P57-PWR_CPU BACK SIDE MLCC Compal Electronics, Inc 57 of 61 Rev 0.7(X06) B+ +3VALW: TDC 7.32A DB99992(V6) Power block DC IN Power Switch Page 47 B+ Page 51 +5VALW: TDC 4.926A DB99992(V5) Page 48 D ALWON D Page 51 +3V_PRIM TDC 0.616A BD99992(V7) Page 51 CHARGER BQ24777(NVDC) +1.8V_PRIM TDC 0.296A BD99992(V8) PCH_PWR_EN PCH_PWR_EN Page 51 Page 50 +0.85_PRIM TDC 0.77A BD99992(V12) PCH_PWR_EN Page 52 C C Battery (2S1P) Page 47 Battery Low Detect +1.0V_PRIM TDC 3.24A BD99992(V11) Page 49 PCH_PWR_EN Page 52 +1.2V_VDDQ : TDC 2.24A BD99992(V10) SIO_SLP_S4# Page 52 +1.8V_MEM TDC 0.294A BD99992(V9) SIO_SLP_S4# Page 52 +1.0VS_VCCIO TDC 2.03A BD99992(V4) B B SIO_SLP_S3# Page 51 +VCC_CORE TDC PL1 4W TDC at PL2: 15A Page 54 BD99991(V1) +VCC_GT TDC PL1 4W TDC at PL2: 14A BD99991(V2) +VCC_SA A ALLSYS_PWRGD Page 55 TDC PL1 4W TDC at PL2: NA BD99991(V3) ALLSYS_PWRGD A Page 56 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date ALLSYS_PWRGD 2013/04/10 Deciphered Date 2014/05/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PWR_POWER BLOCK DIAGRAM Document Number Rev 0.7(X06) LA-C321P Wednesday, July 08, 2015 Sheet 58 of 61 +3VS_AUDIO I2C 2.2K AB3 2.2K I2C0_SCK 0-ohm AD11 I2C0_SDA I2C0_SCK_R Smart AMP I2C0_SDA_R D D 0-ohm Audio +3V_PRIM 2.2K 2.2K @0-ohm AB11 TS_I2C1_SCK AB9 USB20_P3_CONN USB20_N3_CONN TS_I2C1_SDA @0-ohm PCH +1.8V_PRIM C 2.2K AN6 UF_I2C_CLK AN4 UF_I2C_DATA C 2.2K UF CAM +1.8V_PRIM 2.2K AP7 SKYCAM_I2C_CLK AP3 SKYCAM_I2C_DATA 2.2K Skycam PMIC +3VS 2.2K 2.2K B B P7 ISH_I2C0_SCL P5 ISH_I2C0_SDA Sensor +3VS 2.2K T3 ISH_I2C1_SCL T9 ISH_I2C1_SDA 2.2K +1.8VS 2.2K 2.2K A A A19 GNSS_SCL 0-ohm AM7 GNSS_SDA GNSS_SCL_L WWAN GNSS_SDA_L 0-ohm Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2041/09/08 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P61-I2C Block Diagram Size Date: Document Number Rev 0.7(X06) Wednesday, July 08, 2015 Sheet 59 of 61 [Power ON Sequence] +RTCVCC tPCH01_Min : ms RTCRST# D D +DC_IN PWR -> EC ACAV_IN B+ Ta_Min : 10 ms +3VALW tPCH04_Min : ms EC -> PWR ALWON +3VALW_DSW +5VALW EC -> PCH PCH_DPWROK PCH -> EC SIO_SLP_SUS# EC input POWER_SW_IN# EC -> PWR 500us< Tb PCH PCH_RSMRST# PCH -> EC ME_SUS_PWR_ACK tPCH37_Min : mv/us tPCH17_Min : 10 us_Max : 200 us tPCH03_Min : 10 ms tPLT01_Min : 200 ms C C PCH output SUSCLK tPLT02_Max : 90 ms EC -> PCH AC_PRESENT PCH -> EC SUS_ACK# PCH -> EC SIO_SLP_M# PCH -> EC SIO_SLP_WLAN# PCH -> EC SIO_SLP_S5# PCH -> EC SIO_SLP_S4# +1.2V_VDDQ +1.8V_MEM +1.0V_VCCST PCH -> EC SIO_SLP_S3# tCPU00 Min : 1ms +1.0V_VCCSFR_OC tCPU04 Min : 100 ns +1.0VS_VCCSTG +1.0VS_VCCIO tCPU06 Min : 100 ns +5VS/+3VS/+1.8VS EC input ALLSYS_PWRGD EC input H_VCCST_PWRGD_R 500us< Td