A B C D E MODEL NAME : VAZ90 PCB NO : LA-A161P BOM P/N : revision: A00 1 Compal Confidential Schematic Document ZZZ MB_PCB 2 Jarama (Haswell Y-series) @ : Nopop Component CONN@ : Connector Component vPRO@ : SPI ROM (8M+4M) Component nvPRO@ : SPI ROM (8M) Component CS@ : Connected Standby Component Non-CS@ : Non-Connected Standby Component 3 2013-08-14 Rev: A00 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P01-Cover Page Size A B C D Document Number Rev X02 LA-A161P Date: Wednesday, August 14, 2013 E Sheet of 49 A B C D Channel A DDR3L-RS 4Gb (x16) *4 Memory Bus (DDR3L-RS) eDP Panel eDP 1.3* 4lan P.19 E P.12, 13 Dual Channel DDR3L-RS 1600 MHz Channel B DDR3L-RS 4Gb (x16) * USB2.0 Touch Screen P.14, 15 P.17 SATA3.0 HDMI Conn USB 3.0 Conn ( USB Charger Port ) USB 3.0 Conn ( USB Charger Port ) HDMI 1.4a LEVEL SHIFT P.18 P.18 Intel Haswell Y-Series BGA 1168 Balls 7.5W SDP SPI Mini Card (Full) # mSATA P.26 SPI ROM vPRO: (8M+4M) non vPRO (8M) P.07 USB3.0/USB2.0 P.23 Card Reader RTS5249 PCIE *1 USB3.0/USB2.0 P.23 in Socket P.23 P.23 2 Digital Camera USB2.0 USB2.0 P.17 PCIE *2 TO EC ALS+CLS TCS3472 UART I2C e-Compass + Accelerometer DE303DLHCTR Sensor HUB STM32F103RC PCIE PCM P.19 level shift SMLink HDA I2C Touch Pad NGFF Slot A-SD WLAN BT 802.11abgn/ac, BT4.0+LEP.25 USB2.0 USB2.0 Daughter Board level shift SDIO I2C P.24 NFC Module Conn P.26 Gyro Sensor TX3GD20TR NGFF Slot A-DP WiGig/ Tri-Band 802.11abgn/ac/ad, BT3+LE P.25 DP lan PS2 TO EC Audio AMP APA2605 P.22 st Digital MIC RTC 2nd Array MIC P.33 KSI/KSO P.19 I2C DC/DC Interface CKT Power Circuit DC/DC Resistance Keyboard Win8 KEY P.31 P.19 Capacitance Keyboard P.31 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/02/23 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P02-Block Diagram Size B C D Document Number Rev A00 LA-A161P Date: A P.22 Panel SMBus P.30 Keyboard BL P.22 P.19 Int Speaker Sensor HUB AUDIO Codec GPIO PCH GPIO Digital MIC Switch PWM P.31 I2C Touch Controller P.31 P.21 Page 5, 6, 7, 8, 9, 10, 11 ENE KB9012BF P.32 Global headset P.21 LPC Bus TPM AT97SC3204 P.24 FAN conn Audio Codec ALC3661 HDA Audio DSP ALC5505 P.20 Wednesday, August 14, 2013 E Sheet of 49 A B C D E Compal Confidential Project Code : VAZ90 File Name : 1 2 3 4 LA-A161P Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P03-DaughterB block diagram Size Date: A B C D Document Number Rev A00 Wednesday, August 14, 2013 E Sheet of 49 A Board ID Table for AD channel Vcc Ra Board ID 10 11 12 13 14 15 16 17 18 19 3.3V +/- 5% 100K +/- 1% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 75K +/- 1% 100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1% NC USB PORT# BOARD ID Table V AD_BID V AD_BID typ V AD_BID max EC AD3 Board ID 10 11 12 13 14 15 16 17 18 19 PCB Revision Non- VPRO 0.1 (SSI) VPRO 0.2 (PT) VPRO 0.3 (ST) VPRO 1.0 (XB) PCH USB Port Mapping VPRO 0.1 (SSI) Non- VPRO 0.2 (PT) Non- VPRO 0.3 (ST) Non- VPRO 1.0 (XB) DESTINATION External USB3 External USB3 NGFF CARD WLAN Touch Panel Camera Sensors HUB NGFF(WiGig) SMBUS Control Table SOURCE EC_SMB_CK1 EC_SMB_DA1 KB9012 EC_SMB_CK2 EC_SMB_DA2 KB9012 EC_SMB_CK4 EC_SMB_DA4 KB9012 PCH_SML0CLK PCH_SML0DATA PCH PCH_SML1CLK PCH_SML1DATA PCH PCH_SMBCLK PCH_SMBDATA PCH CL_CLK CL_DATA PCH NGFF V Charger NFC XDP ALS Panel T-COM Keyboard V V V PCH DDI Port Mapping V Link V DDI PORT# DESTINATION NGFF(WiGig) HDMI V V DIFFERENTIAL DESTINATION CLKOUT_PCIE0 WiGig CLKOUT_PCIE1 CLKOUT_PCIE2 CLK BATT CLKOUT_PCIE3 Card Reader NGFF CARD WLAN WiGig FLEX CLOCKS DESTINATION SATA CLKOUT_LPC_0 TPM , EC LPC SATA0 CLKOUT_LPC_1 LPC Debug DESTINATION PCI EXPRESS m-SATA DESTINATION Lane NGFF(WiGig) SATA1 Lane CardReader SATA2 Lane NGFF(WLAN) SATA3 Lane NGFF(WiGig) CLKOUT_PCIE4 Lane CLKOUT_PCIE5 Lane Symbol Note : : means Digital Ground : means Analog Ground Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P04-Notes List Size Document Number Rev A00 LA-A161P Date: A Wednesday, August 14, 2013 Sheet of 49 NGFF(WiGig) D 2 0_0402_5%~D EDP_BKLCTL 0_0402_5%~D EDP_DISP HDMI @ @ RH123 100K_0402_5%~D ENBKL @ RH158 100K_0402_5%~D PCH_ENVDD RH300 1M_0402_5%~D PCH_DP_HPD @ RH387 1M_0402_5%~D PCH_HDMI_HPD DDI DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL PCH_DP_CLK PCH_DP_DAT PCH_HDMI_CLK PCH_HDMI_DAT ENBKL PCH_ENVDD 23,25 MPCIE_RST# TP_INT# EDP_BKLCTL ENBKL PCH_ENVDD B8 A9 C6 MPCIE_RST# TPM_IRQ# PCI_PIRQC# PCI_PIRQD# U6 P4 N4 N2 AD4 @ T123 C D20 +EDP_COM A43 EDP_DISP RC36 @ RC158 D +VCCIOA_OUT 19 19 2 24.9_0402_1% 0_0402_5%~D HSW_ULT_DDR3L RH455 RH456 1 10K_0402_5%~D 10K_0402_5%~D PCI_PIRQC# PCI_PIRQD# RH463 10K_0402_5%~D TPM_IRQ# @ RH396 RH397 1 10K_0402_5%~D 10K_0402_5%~D AUDIO_IRQ# NGFF_WAKE# RH452 10K_0402_5%~D Sensor_RST# RH381 100K_0402_5%~D MPCIE_RST# TP_INT# 32 TP_INT# 19 TS_RST# 25 NGFF_WAKE# 24 Sensor_RST# NGFF_WAKE# Sensor_RST# AUDIO_IRQ# U7 L1 L3 R5 L4 EDP_BKLCTL EDP_BKLEN EDP_VDDEN DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND B9 C9 D9 D11 PCH_DP_CLK PCH_DP_DAT PCH_HDMI_CLK PCH_HDMI_DAT PCH_HDMI_CLK PCH_HDMI_DAT +5VS 18 18 PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP DISPLAY PCIE GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_HPD DDPC_HPD EDP_HPD C5 B6 B5 A6 C8 A8 D6 PCH_DP_HPD PCH_HDMI_HPD CPU_eDP_HPD# PCH_DP_AUXN 25 PCH_DP_AUXP 25 @ QC5 DII-DMN65D8LW-7~D @ RC148 CPU_eDP_HPD# PCH_DP_HPD 25 PCH_HDMI_HPD 18 D 100K_0402_5%~D eDP_AUXN eDP_AUXP S 19 19 19 19 G @ RH380 2.2K_0402_5%~D 2.2K_0402_5%~D 2.2K_0402_5%~D 2.2K_0402_5%~D eDP_TXN_P2 eDP_TXP_P2 eDP_TXN_P3 eDP_TXP_P3 19 19,29,30 2 2 A45 B45 19 19 19 19 OF 19 +3VS 1 1 C47 C46 A49 B49 eDP_TXN_P0 eDP_TXP_P0 eDP_TXN_P1 eDP_TXP_P1 Width 20 mils, Spacing 25 mils, Length < 100 mil UCPU1I RH281 RH282 RH388 RH389 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP C45 B46 A47 B47 C eDP_HPD 0_0402_5%~D @ RC138 100K_0402_5%~D RC160 100K_0402_5%~D OF 19 19 1 RC146 C51 C50 C53 B54 C49 B50 A53 B53 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 @ RC147 PCH_DDI2_N0 PCH_DDI2_P0 PCH_DDI2_N1 PCH_DDI2_P1 PCH_DDI2_N2 PCH_DDI2_P2 PCH_DDI2_N3 PCH_DDI2_P3 DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 PCH_INV_PWM 18 18 18 18 18 18 18 18 C54 C55 B58 C58 B55 A55 A57 B57 19 PCH_DP_N0 PCH_DP_P0 PCH_DP_N1 PCH_DP_P1 PCH_DP_N2 PCH_DP_P2 PCH_DP_N3 PCH_DP_P3 HSW_ULT_DDR3L UCPU1A 25 25 25 25 25 25 25 25 +1.05VS_VCCST HSW_ULT_DDR3L UCPU1B RC43 62_0402_5% @ T2 H_CATERR# H_PECI PROC_DETECT CATERR PECI PU/PD for JTAG signals MISC PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO 33 D61 K61 N62 33,35 H_PROCHOT# H_PROCHOT# RC41 H_PROCHOT#_R 56_0402_5% H_CPUPWRGD_R RC44 K63 C61 H_CPUPWRGD_R 10K_0402_5%~D JTAG PROCHOT PROCPWRGD THERMAL 200_0402_1%~D 121_0402_1% 100_0402_1%~D Avoid stub in the PWRGD path while placing resistors RC44 & RC53 2 RC55 RC58 RC60 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 H_DRAMRST# DDR_PG_CNTL DDR3 Compensation Signals AU60 AV60 AU61 AV15 AV61 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 XDP_PRDY# XDP_PREQ# CPU_XDP_TCK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO XDP_PRDY# 17 XDP_PREQ# 17 CPU_XDP_TCK 17 CPU_XDP_TMS 17 CPU_XDP_TRST# 17 CPU_XDP_TDI 17 CPU_XDP_TDO 17 +1.05VS_VCCST PWR BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 Width 15 mils, Spacing 25 mils, Length < 500 mil B J62 K62 E60 E61 E59 F63 F62 DDR3L J60 H60 H61 H62 K59 H63 K60 J61 @ T226 @ T227 @ T228 @ T229 @ T230 @ T231 XDP_BPM0# XDP_BPM1# CPU_XDP_TMS 51_0402_5% RC45 @ CPU_XDP_TDI 51_0402_5% RC46 @ CPU_XDP_TDO 51_0402_5% RC48 17 17 B Stuffed : Single & Dual TCK OF 19 CPU_XDP_TCK 51_0402_5% RC52 CPU_XDP_TRST# 51_0402_5% RC54 @ closed MCP 1000 mils +3VS +1.35V_DDR CC240 0.1U_0402_10V7K~D R1d Stuffed : Dual TCK unstuffed : Singel TCK XDP_PRDY# XDP_PREQ# TP@ TP@ T263 T264 CPU_XDP_TCK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO TP@ TP@ TP@ TP@ TP@ T265 T266 T267 T268 T269 R2 R9 UC1 RC159 220K_0402_5%~D 42 SM_PG_CTRL VCC NC A Y DDR_PG_CNTL GND 74AUP1G07GW_TSSOP5 @ RC161 2M_0402_5% +1.35V_DDR A A RC75 470_0402_5%~D H_DRAMRST# @ RC162 0_0402_5%~D DDR3_DRAMRST# 12,13,14,15 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P05-MCP(1/7) DDI,EDP,PM,XDP Size Document Number Rev A00 LA-A161P Date: Wednesday, August 14, 2013 Sheet of 49 D D UCPU1C 12,13 C B HSW_ULT_DDR3L HSW_ULT_DDR3L UCPU1D DDR_A_D[0 63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 DDR CHANNEL A SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 14,15 AU37 AV37 AW36 AY36 M_CLK_A_DDR#0 M_CLK_A_DDR0 AU43 AW43 AY42 AY43 AP33 AR32 DDR_B_D[0 63] 12,13,16 12,13,16 DDR_A_CKE0 DDR_A_CKE1 12,13,16 12,13,16 DDR_A_CS0# DDR_A_CS1# 12,13,16 12,13,16 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AP32 AY34 AW34 AU34 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# AU35 AV35 AY41 AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AP49 AR51 AP51 12,13,16 12,13,16 12,13,16 DDR_A_BS0 12,13,16 DDR_A_BS1 12,13,16 DDR_A_BS2 12,13,16 DDR_A_MA[0 15] DDR_A_DQS#[0 7] DDR_A_DQS[0 7] V_DDR_REF_CA V_DDR_REFA_R V_DDR_REFB_R 12,13,16 12,13 12,13 16 16 16 10 mil trace width AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2 DDR CHANNEL B SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 AM38 AN38 AK38 AL38 M_CLK_B_DDR#0 M_CLK_B_DDR0 AY49 AU50 AW49 AV50 DDR_B_CKE0 DDR_B_CKE1 14,15,16 14,15,16 AM32 AK32 DDR_B_CS0# DDR_B_CS1# 14,15,16 14,15,16 14,15,16 14,15,16 AL32 AM35 AK35 AM33 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 14,15,16 14,15,16 14,15,16 14,15,16 14,15,16 14,15,16 DDR_B_MA[0 15] 14,15,16 DDR_B_DQS#[0 7] C 14,15 DDR_B_DQS[0 7] 14,15 B OF 19 OF 19 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P06-MCP(2/7) DDRIII Size Document Number Rev A00 LA-A161P Date: Wednesday, August 14, 2013 Sheet of 49 HSW_ULT_DDR3L UCPU1E 15P_0402_50V8J~D PCH_RTCX1 1 CH2 RH2 10M_0402_5% RH11 +RTCVCC 1M_0402_5%~D 2 YH1 32.768KHZ_12.5PF_9H03200031 CH3 17 PCH_RTCX2 PCH_RTCRST# 15P_0402_50V8J~D far away hot spot 20 20 20 20 HDA_BITCLK_AUDIO HDA_RST_AUDIO# HDA_SYNC_AUDIO HDA_SDOUT_AUDIO HDA_BIT_CLK HDA_RST# HDA_SYNC HDA_SDOUT 20 HDA_BIT_CLK HDA_SYNC HDA_RST# HDA_SDIN0 HDA_SDOUT @EMI@ MC96 TP@ TP@ TP@ TP@ TP@ HDA_BIT_CLK 22P_0402_50V8J~D PCH_SRTCRST# SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 RTC PCH_JTAG_JTAGX PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TCK PCH_JTAG_TDI T273 T275 T276 T277 T278 AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8 HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK AUDIO HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK SATA SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 closed MCP 1000 mils Reserve for EMI please close to UCPU1E SP@ CLRP2 SHORT PADS ME CMOS CH5 1U_0402_6.3V6K~D CMOS SP@ CLRP1 SHORT PADS PCH_RTCRST# 1 RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 33_8P4R_5% CH4 1U_0402_6.3V6K~D 2 RH25 20K_0402_5%~D RH23 20K_0402_5%~D AW5 AY5 AU6 AV7 AV6 AU7 PCH_RTCX1 PCH_RTCX2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST# PCH_RTCRST# RP3 D +RTCVCC CLP1 & CLP2 place near DIMM +5VALW 17 17 17 17 17 PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS 17 PCH_JTAG_JTAGX PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_JTAGX AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2 PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD SATA_IREF RSVD RSVD SATA_RCOMP SATALED JTAG J5 H5 B15 A15 PCH_INTVRMEN 330K_0402_5%~D 330K_0402_5%~D SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 26 26 26 26 @RF@MC103 @RF@ MC103 mSATA HDA_SDOUT 10P_0402_50V8J~D Reserve for RF please close to UH1 J8 H8 A17 B17 +3VS J6 H6 B14 C15 PCH_GPIO35 PCH_GPIO36 mSATA_DET# closed MCP 2000 mils F5 E5 C17 D17 EC_SMI# PCH_GPIO35 PCH_GPIO36 mSATA_DET# V1 EC_SMI# U1 PCH_GPIO35 V6 PCH_GPIO36 AC1 mSATA_DET# TP@ TP@ TP@ TP@ EC_SMI# 1 @ RH390 RH391 RH392 D 10K_0402_5%~D 200K_0402_5%~D 100K_0402_5%~D T270 T271 T272 T274 HDA_SDO 33 mSATA_DET# A12 L11 K10 C12 SATA_RCOMP RH43 U3 PCH_SATALED# RH35 26 ME debug mode , this signal has a weak internal PD +V1.05S_ASATA3PLL L=>security measures defined in the Flash Descriptor will be in effect (default) 3K_0402_1%~D +3VS 10K_0402_5%~D H=>Flash Descriptor Security will be overridden +3V_PCH Width = 15 mil, Spacing = 12 mil Close PCH within 500 mil +RTCVCC @ RH42 R1341 1M_0402_5%~D 1K_0402_5%~D HDA_SDOUT = Disabled *Low High = Enabled OF 19 Q351 G HDA_SDO From EC, for enable ME code programing INTVRMEN +3V_PCH RH24 1K_0402_5%~D HDA_SDOUT HSW_ULT_DDR3L UCPU1F S 33 Integrated VRM enable * HL：：Integrated VRM disable D RH31 @RH34 @ RH34 XTAL24_IN DII-DMN65D8LW-7~D 0312-45 PCH JTAG R4 R3d R5 R8 R6 Stuffed : Single & Dual TCK RH40 51_0402_5% RH445 51_0402_5% PCH_JTAG_TDO RH39 51_0402_5% PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_JTAGX @ RH53 51_0402_5% PCH_JTAG_TCK 25 25 WiGig @ RH410 @RH410 1 RH91 CLK_PCIE_CD# CLK_PCIE_CD +3VS 23 CDCLK_REQ# 25 CLK_PCIE2# 25 CLK_PCIE2 +3VS WLAN 1K_0402_5%~D CLK_PCIE0# CLK_PCIE0 +3VS 23 23 CardReader @ RH375 10K_0402_5%~D RH95 RH100 PCH_GPIO18 C43 C42 U2 B41 A41 Y5 10K_0402_5%~D PCH_GPIO19 10K_0402_5%~D C41 B42 PCH_GPIO20 AD1 CLK_PCIE3# CLK_PCIE3 +3VS RH103 10K_0402_5%~D B38 C37 N1 PCH_GPIO21 +3VS RH107 10K_0402_5%~D PCH_GPIO22 22 A39 B39 U5 B37 A37 T2 DMIC_SW_PCH CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18 XTAL24_IN XTAL24_OUT RSVD RSVD DIFFCLK_BIASREF CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLOCK CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20 SIGNALS CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP CLKOUT_ITPXDP_P CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22 A25 B25 XTAL24_IN XTAL24_OUT K21 M21 C26 XCLK_BIASREF C35 C34 AK8 AL8 TESTLOW1 TESTLOW2 TESTLOW3 TESTLOW4 AN15 AP15 RH113 3K_0402_1%~D RH428 RH360 RH386 1 22_0402_5%~D 22_0402_5%~D 22_0402_5%~D +V1.05S_AXCK_LCPLL CLKOUT_LPC0 CLKOUT_LPC1 CH24 15P_0402_50V8J~D CLK_PCI_TPM 24 CLK_LPC_DEBUG 17 CLK_PCI_LPC 33 LPC CLOCK CAN FEED ONLY LOAD AT A TIME 1 1 RH76 RH77 RH78 RH79 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D @RH417 @ RH417 25 CLK_REQ0# PCH_GPIO18 G CLK_REQ2# PCH_GPIO20 +3VS_NGFF 25 G PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_IO3 RP4 AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1 RH258 SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3 SPI SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74 CL_CLK CL_DATA CL_RST C-LINK AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 SMBALERT# SMBCLK SMBDATA CR_PWREN SML0CLK SML0DATA SML1ALERT# SML1CLK SML1DATA SMBALERT# 24 CR_PWREN 23 SML0CLK 26 SML0DATA 26 SML1ALERT# 24 @RH418 @ RH418 Connect NFC AF2 AD2 AF4 CL_CLK 25 CL_DATA 25 CL_RST# 25 25 CLK_REQ3# +3VS_NGFF OF 19 +3V_PCH +3VS CH6 1U_0402_16V7K~D SPI_DIN32 SPI_PCH_DO2_32 SPI_DO32 SPI_PCH_DO3_32 33_0402_5%~D vPRO@ RP5 PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_SI PCH_SPI_IO3 SMBCLK @EMI@ MC94 @EMI@ MR256 1 RH99 10K_0402_5%~D PCH_SMBCLK RH469 RH470 RH471 RH472 1 1 2 2 SML0CLK RH70 499_0402_1%~D SML0DATA RH72 499_0402_1%~D SMBALERT# EC_SMI# CR_PWREN RH80 RH81 RH82 RH83 1 1 2 2 2.2K_0402_5%~D 2.2K_0402_5%~D 2.2K_0402_5%~D 2.2K_0402_5%~D 17 DMN66D0LDW-7_SOT363-6~D Connect EC, ALS @ RH105 PCH_SMLDATA 19,28,32,33 0_0402_5%~D SMBDATA Connect XDP QH3B PCH_SMBDATA 17 +3V_PCH A DMN66D0LDW-7_SOT363-6~D 0_0402_5%~D USB_OC2# 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D +3VS SPI_CLK_ROM 33_0402_5%~D Reserve for EMI please close to U48 SPI_PCH_DO3_32 SPI_CLK32 SPI_DO32 @EMI@ MC95 @EMI@ MR257 1 22P_0402_50V8J~D Issued Date SPI_CLK32 Compal Electronics, Inc Compal Secret Data Security Classification vPRO@ CH7 1U_0402_16V7K~D 2011/06/02 Deciphered Date 2013/10/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 33_0402_5%~D Reserve for EMI please close to U2 Date: SML1CLK SMBCLK SMBDATA SML1DATA +3.3V_M U2 vPRO@ W25Q32FVSSIQ_SO8 19,28,32,33 DMN66D0LDW-7_SOT363-6~D QH4B @ RH454 0_0402_5%~D 22P_0402_50V8J~D SML1DATA SPI ROM ( 4MByte ) VCC /HOLD/IO3 CLK DI/IO0 PCH_SMLCLK RH98 10K_0402_5%~D @ RH111 ROM is Quad SPI /CS DO/IO1 /WP/IO2 GND DMN66D0LDW-7_SOT363-6~D QH4A @RH453 @ RH453 0_0402_5%~D PCH_SPI_CLK 33_8P4R_5% QH3A SML1CLK vPRO@ RH256 +3VS nvPRO@ +3VS W25Q64FVSSIQ_SO8 nvPRO@ SPI_IO3_ROM SPI_CLK_ROM SPI_SI_ROM SD028150A80 VCC /HOLD(IO3) CLK DI(IO0) 15_0402_5%~D SD300001P00 U48 15_0804_8P4R_5% +3.3V_M R1205 100K_0402_5%~D SPI ROM ( 8MByte ) ROM is Quad SPI /CS DO(IO1) /WP(IO2) GND PCH_GPIO21 Q350 33_8P4R_5% B 0_0402_5%~D DII-DMN65D8LW-7~D G PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_SI PCH_SPI_IO3 SMBUS D 12P_0402_50V8J~D LPC S PCH_SPI_CLK PCH_SPI_CS# PCH_SPI_CS1# 33_0402_5%~D PCH_SPI_CLK LAD0 LAD1 LAD2 LAD3 LFRAME @EMI@ MC118 AU14 AW12 AY12 AW11 AV12 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# 1 vPRO@ RP4 SPI_SO_ROM SPI_IO2_ROM SPI_SI_ROM SPI_IO3_ROM 17,24,33 17,24,33 17,24,33 17,24,33 17,24,33 Closed to UCPU1 SPI_CLK_ROM vPRO@ RH258 R1200 100K_0402_5%~D HSW_ULT_DDR3L UCPU1G R1197 100K_0402_5%~D vPRO:SPI ROM (8M+4M) non vPRO:SPI ROM (8M) PCH_SPI_CS1# SPI_DIN32 SPI_PCH_DO2_32 Q348 +3VS_NGFF A CH23 15P_0402_50V8J~D 0_0402_5%~D DII-DMN65D8LW-7~D D TESTLOW1 TESTLOW2 TESTLOW3 TESTLOW4 S 1K_0402_5%~D PCH_SPI_IO3 SPI_CLK32 B35 A35 OF 19 D 1K_0402_5%~D PCH_SPI_IO2 RH56 S RH54 PCH_SPI_CS# SPI_SO_ROM SPI_IO2_ROM C Q346 B 1M_0402_5%~D YH2 24MHZ_12PF_7V24000020 XCLK_BIASREF reserved 30pcs, 15-pcs is OK after fine-tune D D PC828 PC819 PC829 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M PC818 PC809 22U_0805_6.3V6M PC827 22U_0805_6.3V6M PC817 PC808 22U_0805_6.3V6M PC826 22U_0805_6.3V6M PC816 @ PC807 @ 22U_0805_6.3V6M PC825 @ PC806 22U_0805_6.3V6M PC815 @ 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M PC824 @ PC805 22U_0805_6.3V6M PC823 @ PC814 @ 22U_0805_6.3V6M 22U_0805_6.3V6M PC813 PC804 @ 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M PC822 @ 22U_0805_6.3V6M PC812 PC803 22U_0805_6.3V6M PC821 @ 22U_0805_6.3V6M PC811 @ PC802 22U_0805_6.3V6M 22U_0805_6.3V6M C PC801 @ 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M +VCC_CORE PC810 @ PC820 C PC830 H0.85 B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P44-PWR_PROCESSOR_DECOUPLING Size Document Number Rev A00 LA-A161P Date: Wednesday, August 14, 2013 Sheet 44 of 49 D D C C B B A A Title P45-LED converter TPS61181A Size Date: Document Number Rev A00 Wednesday, August 14, 2013 Sheet 45 of 49 Version Change List ( P I R List ) Item Page# X Title XX XXX Date Request Owner XX'XX/XX Compal_XX Page Issue Description Solution Description XXXXX Rev Change PRXX from Xohm to XXKohm D D 36 20121008 Compal_Power create one more input cap for TPS51362 Vin add PC513_10U_0805_16V6K for TPS51362's input 34 20121012 Compal_HW create one more resistor for TPS62130 enable pin add PR342_2.2K_0402_5% design change, delete PU301~PU305, TPS62130 and related components, create PU301, TPS51225 for 3.3V and 5V power rails 34 35 20121018 Compal_Power 20121018 Compal_Power 36 36 design change, delete PU401, PU402, TPS62140 and TPS62150 and related components, create PU401and PU402, SY8003D for 1.5V and 1.8V power rails C C B B A A Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Issued Date Deciphered Date 2013/10/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: P46-PWR_PIR-1 Document Number Rev A00 LA-A161P Wednesday, August 14, 2013 Sheet 46 of 49 Version Change List ( P I R List ) Item Page# Title Date Request Owner XX'XX/XX Compal_XX Page Issue Description Solution Description Rev D D X XX XXX XXXXX Change PRXX from Xohm to XXKohm C C B B A A 2011/06/02 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2013/10/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: P47-PWR_PIR-2 Document Number Rev A00 LA-A161P Sheet Wednesday, August 14, 2013 47 of 49 A B C D +3V_PCH 2.2K SMBUS Address [0x9a] +3VS 2.2K @0-ohm 10K +3VS AP2 SMBCLK AH1 SMBDATA E 10K PCH_SMBCLK DMN66D0 PCH_SMBDATA XDP DMN66D0 +3V_PCH 499 PCH AN1 SML0CLK AK1 SML0DATA @0-ohm 499 +3VS +3V_PCH 2.2K 2.2K 4.7K @0-ohm AU3 [0x28] NFC 4.7K PCH_SMLCLK 0-ohm +3VS SML1CLK +3VNS_PWR PCH_SMLDATA 2.2K DMN66D0 AH3 ALS SML1DATA DMN66D0 0-ohm @0-ohm NC mos 2.2K [0x29] @0-ohm @0-ohm @ DMN66D0 DMN66D0 +3VNS_PWR @0-ohm @ +3VNS_PWR CS@ 2.2K CS@ 2.2K @ 2.2K +3VS @0-ohm I2C0_SCK_SNR G3 I2C0_SDA_SNR F3 Magnetic 0x3C Acceleration 0x32 B5 e-Compass + Accelerometer C5 Sensor HUB @ 2.2K [0xBA] I2C F3 I2C0_SCK @ 0-ohm Gyro Sensor +3VS F2 I2C0_SDA [0xD2] @ 0-ohm B8 4.7K A6 @ 0-ohm I2C0_SCK_DSP 27 +3VS_TP I2C0_SDA_DSP26 +3VS_TS ALS 5505 4.7K B8 PCH_SMLCLK 13 A6 PCH_SMLDATA 12 E5 EC_SMB_CK4 11 D5 EC_SMB_DA4 10 Keyboard @ 0-ohm 4.7K 4.7K @ 4.7K @ 4.7K PCH I2C1_SCK @ 0-ohm I2C1_SCK_TP G4 I2C1_SDA I2C1_SDA_TP F1 +3VALW_EC KBC Touch Pad @ 0-ohm @ 0-ohm 1K I2C1_SCK_TS I2C1_SDA_TS A8 EC_SMB_CK1 A7 EC_SMB_DA1 Touch Panel 1K 100-ohm [0x12] BATTERY CONN [0x16] 100-ohm Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2013/10/28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P48-SMBus Block Diagram Size Date: B Charger @ 0-ohm A Panel C D Document Number Rev A00 Wednesday, August 14, 2013 E Sheet 48 of 49 [AC in] EC pay attention timing Ta B+ +3VLP EC Output +3VLP Tc EC_ON EC Input Td EC Output Tc 1ns < Th < 4s PBTN_SW# EC_ON Td D Te +3VALW EC Input EC Output Te PM_SLP_SUS# T2 T3 +5VA T4 +5VDX_WALKPORT T5 20 mS EC Output PCH_DPWROK T6 EC Output PCH_RSMRST# EC Input mS ITEM T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T1 +1.05VA +3V_PCH T7 PCH_SUS_PWR_DN T8 < 90ms EC Output AC_PRESENT 20 mS 16ms < T9 < 4s 110 mS EC Output PBTN_OUT# C Minimum duration of PWRBTN # assertion = 16mS after SUSCLK stable T10 PCH Output SUSCLK T11 PCH Output PM_SLP_S5# 30us < T12 PCH Output PM_SLP_S4# T13 10ms 100ms