biostar n560b a2t tf560 a2 rev 5 0 sch

5 D COVER SHEET BLOCK DIAGRAM RESET&CLK MAP SPEC&CHANGE LIST PROCESSOR M2 940 5,6,7,8,9 DDR ADD/CTL/VTT TERMINATI 10 DDR 11 DDR 12 13,14,15 NV CHIPSET(MCP65) 16,17,18,19 C SHEET TITLE PCI 1&2&3 20 FRONT PANEL HEADER 21 PCI EXPRESS X16 & X1 22 IDE CONN 23 POWER CONN & FAN CONTROL 24 FLOOPY / KB / MOUSE / CMOS 25 Reserved 26 USB DEVICE 27 SERIAL & PARALLEL 28 AUDIO CODEC 29 AUDIO CONN 30 VCORE POWER SUPPLY 31 MEM_VREG/MEM_VTT 32 LPC SUPER IO(IT8712/8716) 33 FLASH ROM & H/W MON 34 POWER SEQUENCING 35 LAN 10/100 36 OVER VOLTAGE 37 N560B-A2T D VER:5.0 C B B MCP65 CORE 38 A A Title COVER SHEET Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 1 of 39 POWER SUPPLY CONN D VREG AMD M2 SOCKET 940 M2 MEMORY DDR2 D DDR DIMM(4) 128-BIT 400/533/667/800 MHZ HT 16X16 1GHZ PCI 33MHZ PEX X16 (1) PCI LAN RTL8110SC NFORCE PCI 33MHZ PEX X1 (1 OR 2) PCI SLOT (3) MCP65 (P/S/V) ATA 133 PRIMARY IDE AC97/HDA AUDIO CODEC 692BGA C C SATA CONN(X2/X4) INTEGRATED SATA 1/2 USB2.0 (X8/X10) LPC BUS 33MHZ FLOPPY CONN SIO ITE8716 USB2 PORTS 1-0 DOUBLE STACK PS2/KBRD CONN BACK PANEL CONN USB2 PORTS 3-2 LAN RJ45 PARALLEL CONN USB2 PORTS 5-4 FRONT PANEL HDR B B SERIAL CONN USB2 PORTS 7-6 H/W MON USB2 PORTS 9-8 RGMII MII/RGMII(/NI) 4MB FLASH A A Title SYSTEM BLOCK Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet of 39 M2 940 CPU M2 SKT 939 HT_MCP_PWRGD HT_CPU_TXCLK0 MEMORY_A1_CLK[2:0] CPU RST* CHANNEL A1 0-63 RESET MAP DIMM HT_CPU_TXCLK0* MEMORY_A1_CLK[2:0]* HT_CPU_RXCLK0 HT_CPU_RXCLK0* MEMORY_B1_CLK[2:0] HT_CPU_TXCLK1 MEMORY_B1_CLK[2:0]* D HT_MCP_RST* CPU PWRGD D DIMM PE_RESET* CHANNEL B1 64-127 HT_CPU_TXCLK1* MEMORY_A2_CLK[2:0] HT_CPU_RXCLK1 HT_CPU_RXCLK1* MEMORY_A2_CLK[2:0]* CPUCLK_IN* MEMORY_B2_CLK[2:0] PEX X16 CHANNEL A2 0-63 DIMM PEX X1 MCP65 DIMM MEMORY_B2_CLK[2:0]* CPUCLK_IN PEX X1 CHANNEL B2 64-127 8712/8716 CLKOUT_200MHZ CLKOUT_200MHZ* HT_MCP_RST* PWR SWTCH PE0_REFCLK PWRBT ON* PEX X16 PWRBTN* HT MCP PWRGD SLP S3* PS ON HT_CPU_RXCLK1 PE1_REFCLK HT_CPU_TXCLK1* HT_CPU_TXCLK1 PE1_REFCLK* HT_CPU_RXCLK0* PE2_REFCLK HT_CPU_RXCLK0 PE2_REFCLK* PEX X1 C HT_MCP_PWRGD SLP_S3* SLP_S3* HT_CPU_RXCLK1* HT MCP RST* PWR BUTTON PWR BUTTON* PE0_REFCLK* PWR CONN POWER_GOOD PCI RST0* PCIRST_SLOT1* PCI RST1* PCIRST_SLOT2* PWRGD PCI RST2* PCIRST_SLOT3-4* PCI RST3* PCIRST_IDE* LPC_RST* LPCRST_FLASH* AC_RESET* LPCRST_SIO* C PS ON PWR GOOD PEX X1 PWRGD_SB PWRGD SB CIRCUIT HT_CPU_TXCLK0* HT_CPU_TXCLK0 XTAL_IN MCP65 PWRGD_SB 27 MHZ (TV OUT ONLY) CLOCK DISTRIBUTION GPIO_AUX* PRI IDE SIO LAN_PHY RESET* PCI SLOT PCI SLOT2 PCI SLOT1 FLASH AUDIO_PHY RESET* PCI LAN XTAL_OUT PCI SLOT2 14MHZ OR 24MHZ BUF_SIO SUSCLK 32KHZ LPC_CLK0 33MHZ PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK_FB 33MHZ SIO PCI SLOT1 PCI SLOT RTC_XTAL B PCI LAN B 32.768 KHZ 33MHZ FLASH LPC_CLK1 AC97/AZALIA LINK XTAL_IN HDA CODEC AC_97CLK S-IO 25 MHZ AC_BITCLK XTAL_OUT LAN PHY(/NI) BUF_25MHZ A A Title RESET&CLOCK MAP Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet of 39 CPU VID TABLE D CRU51-M9 PCI INTERRUPT/IDSEL MAP VID [4 0] VDD VID [4 0] VDD BACK PANEL 0X00000 1.550V 0X10000 1.150V SLOT PCI BUS# DEVICE# IDSEL PIN PCI SLOT PCI SLOT PCI SLOT PCI SLOT INTA* INTB* INTC* INTD* REQ/GNT 0X00001 1.525V 0X10001 1.125V 01 0X05 22 P_INTY* P_INTZ* P_INTW* P_INTX* 1/1 0X00010 1.500V 0X10010 1.100V 01 0X06 24 P_INTW* P_INTX* P_INTY* P_INTZ* 2/2 23 P_INTX* P_INTY* P_INTZ* P_INTW* 3/3 0X00011 1.475V 0X10011 1.075V 01 0X07 0X00100 1.450V 0X10100 1.050V 01 0X08 0X00101 1.425V 0X10101 1.025V 01 0X09 0X00110 1.400V 0X10110 1.000V 01 0X0A 0X00111 1.375V 0X10111 0.975V 0X01000 1.350V 0X11000 0.950V 0X01001 1.325V 0X11001 0.925V 0X01010 1.300V 0X11010 0.900V 0X01011 1.275V 0X11011 0X01100 1.250V 0X01101 PCI DEVICE MAP CPU - AMD Socket 940(3-Phase Power) CHIPSET - NF MCP65 MEMORY -Dual Channel DDR SDRAM X (Max 4GB) SLOTS - PEX X16 (x1),PEX X1 (x2),PCI (x3) CODEC - Realtek ALC861VD 5.1 Channel Audio LAN PHY - RTL8201CN LPC/SIO - IT8716F SATA INTEGRATED(x4) PCB Size - 20.0cmx30.4cm, 4-Layer D CHANGE LIST DEVICE PCI BUS# FUNCTION IDSEL PIN DEVICE ID MCP65 0X01-0X0F 0.875V MCP51 LOGICAL PCI BUS 0X11100 0.850V MAC /MAC XA 0X56/57 3.PHY RST FOR S3 WAKE CAN WORK R134,C187 /NI, R136 1.225V 0X11101 0.825V PCI-PCI BRIDGE X9 0X005C 4.DEL VID[0 5] TO MCP51.IT8712 0X01110 1.200V 0X11110 0.800V SATA1 X8 0X0055 5.ADD C45 1U/10V , R16 10K > 100K FOR +2.6V 0X01111 1.175V 0X11111 OFF SATA0 X8 0X0054 6.ADD U5,R83,R82(22) R84,R81(0)/NI FOR ON BOARD VGA PLUG INTO THE MONITOR CAN'T BOOT UP IDE X6 0X0053 7.ADD HEATSINK FOR S/B MODEM CODEC X4 0X0058 8.R262.R264 20K > 56K FOR KBRST,A20GATE BECOMING 3.3V AUDIO CODEC X4 0X0059 9.DEL R217,R222 SLEEPBTNJ CHANGE FROM S/B EXSMI PIN R206 MOVE NEAR S/B USB 2.0 X2 0X005B 10.ADD OV >R222,R281,R282,R283 /NI,R217 USB 1.1 X2 0X005A 11.ADD LED >D14,D15,D16,D17,R64,R66,R67,R74,R108,R149, SW >PWRSW1,RSTSW2,R62,R63 SHAPE TRIM X1 0X005F 12.DEL CT31,PWRGD,C3,C4,C6,C7,C13,CT5,CT19,C209,C210,C230,C211,C212,C213,C227,C228,C229,C17(BOM) LDT X0 0X005E 13.AR19 /NI FOR AUDIO CLK TO 24Mhz SMBUS2 X1 0X0052 14.ADD FOR EMI BC92,AR23,AL8,FB24 LEGACY SLAVE ? ? 0X00D3 LPC X1 0X0050/51 LOGICAL PCI BUS ? ? ? 15.FOR EMI C9,C10,C12,C14 >47P C8,C193,C196,AC32,C331 >104P C395,C394,C393,C392,C391,C390,C389,C388,C383C387,C382,C386,C381,C385,C378,C384,C380 >100P C116,C119,C123 >33P AR22 >0 C343 >103P C342 >102P C336 >10P H1,H2 >COMMOM CHOKE C SMBUS ADDRESS MAP DEVICE SMBUS # 1.Q37 2N7002 CHANGE 2N3904 FOR POWER_SB TIMING 2.ADD C398 10U/10V FOR POWER_SB TIMING C ADDRESS SLOT DIMM 0 1010 000 = 0X50 DIMM 1010 001 = 0X51 DIMM 1010 010 = 0X52 DIMM 1010 011 = 0X53 SIO 0101 101 = 0X2D PCI SLOT 1 ARP PCI SLOT ARP PCI SLOT ARP PCI SLOT ARP DDC BUS A ? DDC BUS B ? 22U/25DE 5*7 mm 100U/16DE 6.3*11 mm 220U/10DE 6.3*11 mm 470U/16DE 8*11 mm 1000U/10DE 8*14 mm 1500U/16DE 10*25 mm 3300U/25DE 10*25 mm PCI SLOT PCI SLOT PCI SLOT PCI SLOT B B 16.DEL BOM FOR EMI FB6 /NI PCI SLOT 5.CHANGE HEATSINK FOR N/B TO SHORT D O D A D C KA O GI G S G S A O I C R G S B E A TO-263 TO-252 SOT-223 SOT-23 SOT-23 SOT-23 PHB55N03 90N02 20N03 TM3055TL-S PHD55N03 AMS1117 LM431 2N7002 SI2303S SI2301S 2N3904 BAT54C 2N3906 BAT54S MMBT2907A 2N2222A E BC ECB TO-92 TO-92 TO-92 LM431 78L05-D LM432 2N2222A 2N2097A HSD882-D K SOT-23 A A Title SPEC&CHANGE LIST Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet of 39 +1.2V_HT R64 49.9 1% 0402 R63 49.9 1% 0402 D 13 HTCPU_UPCNTL 13 HTCPU_UPCNTL_ C 13 HTCPU_UP[15 0] 13 HTCPU_UP_[15 0] CPU1A 13 HTCPU_UPCNTL1 13 HTCPU_UPCNTL1_ 13 HTCPU_UPCLK1 13 HTCPU_UPCLK1_ 13 HTCPU_UPCLK0 13 HTCPU_UPCLK0_ CPU1B HYPERTRANSPORT HTCPU_UPCLK1 HTCPU_UPCLK1_ HTCPU_UPCLK0 HTCPU_UPCLK0_ N6 P6 N3 N2 HTCPU_UPCNTL1 HTCPU_UPCNTL1_ HTCPU_UPCNTL HTCPU_UPCNTL_ V4 V5 U1 V1 HTCPU_UP15 HTCPU_UP_15 HTCPU_UP14 HTCPU_UP_14 HTCPU_UP13 HTCPU_UP_13 HTCPU_UP12 HTCPU_UP_12 HTCPU_UP11 HTCPU_UP_11 HTCPU_UP10 HTCPU_UP_10 HTCPU_UP9 HTCPU_UP_9 HTCPU_UP8 HTCPU_UP_8 U6 V6 T4 T5 R6 T6 P4 P5 M4 M5 L6 M6 K4 K5 J6 K6 HTCPU_UP7 HTCPU_UP_7 HTCPU_UP6 HTCPU_UP_6 HTCPU_UP5 HTCPU_UP_5 HTCPU_UP4 HTCPU_UP_4 HTCPU_UP3 HTCPU_UP_3 HTCPU_UP2 HTCPU_UP_2 HTCPU_UP1 HTCPU_UP_1 HTCPU_UP0 HTCPU_UP_0 U3 U2 R1 T1 R3 R2 N1 P1 L1 M1 L3 L2 J1 K1 J3 J2 L0_CLKIN_H(1) L0_CLKIN_L(1) L0_CLKIN_H(0) L0_CLKIN_L(0) L0_CLKOUT_H(1) L0_CLKOUT_L(1) L0_CLKOUT_H(0) L0_CLKOUT_L(0) L0_CTLIN_H(1) L0_CTLIN_L(1) L0_CTLIN_H(0) L0_CTLIN_L(0) L0_CTLOUT_H(1) L0_CTLOUT_L(1) L0_CTLOUT_H(0) L0_CTLOUT_L(0) L0_CADIN_H(15) L0_CADIN_L(15) L0_CADIN_H(14) L0_CADIN_L(14) L0_CADIN_H(13) L0_CADIN_L(13) L0_CADIN_H(12) L0_CADIN_L(12) L0_CADIN_H(11) L0_CADIN_L(11) L0_CADIN_H(10) L0_CADIN_L(10) L0_CADIN_H(9) L0_CADIN_L(9) L0_CADIN_H(8) L0_CADIN_L(8) L0_CADOUT_H(15) L0_CADOUT_L(15) L0_CADOUT_H(14) L0_CADOUT_L(14) L0_CADOUT_H(13) L0_CADOUT_L(13) L0_CADOUT_H(12) L0_CADOUT_L(12) L0_CADOUT_H(11) L0_CADOUT_L(11) L0_CADOUT_H(10) L0_CADOUT_L(10) L0_CADOUT_H(9) L0_CADOUT_L(9) L0_CADOUT_H(8) L0_CADOUT_L(8) L0_CADIN_H(7) L0_CADIN_L(7) L0_CADIN_H(6) L0_CADIN_L(6) L0_CADIN_H(5) L0_CADIN_L(5) L0_CADIN_H(4) L0_CADIN_L(4) L0_CADIN_H(3) L0_CADIN_L(3) L0_CADIN_H(2) L0_CADIN_L(2) L0_CADIN_H(1) L0_CADIN_L(1) L0_CADIN_H(0) L0_CADIN_L(0) L0_CADOUT_H(7) L0_CADOUT_L(7) L0_CADOUT_H(6) L0_CADOUT_L(6) L0_CADOUT_H(5) L0_CADOUT_L(5) L0_CADOUT_H(4) L0_CADOUT_L(4) L0_CADOUT_H(3) L0_CADOUT_L(3) L0_CADOUT_H(2) L0_CADOUT_L(2) L0_CADOUT_H(1) L0_CADOUT_L(1) L0_CADOUT_H(0) L0_CADOUT_L(0) AD5 AD4 AD1 AC1 HTCPU_DWNCLK1 HTCPU_DWNCLK1_ HTCPU_DWNCLK0 HTCPU_DWNCLK0_ Y6 W6 W2 W3 HTCPU_DWNCNTL HTCPU_DWNCNTL_ Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4 HTCPU_DWN15 HTCPU_DWN_15 HTCPU_DWN14 HTCPU_DWN_14 HTCPU_DWN13 HTCPU_DWN_13 HTCPU_DWN12 HTCPU_DWN_12 HTCPU_DWN11 HTCPU_DWN_11 HTCPU_DWN10 HTCPU_DWN_10 HTCPU_DWN9 HTCPU_DWN_9 HTCPU_DWN8 HTCPU_DWN_8 Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1 HTCPU_DWN7 HTCPU_DWN_7 HTCPU_DWN6 HTCPU_DWN_6 HTCPU_DWN5 HTCPU_DWN_5 HTCPU_DWN4 HTCPU_DWN_4 HTCPU_DWN3 HTCPU_DWN_3 HTCPU_DWN2 HTCPU_DWN_2 HTCPU_DWN1 HTCPU_DWN_1 HTCPU_DWN0 HTCPU_DWN_0 HTCPU_UP[15 0] HTCPU_DWN[15 0] HTCPU_UP_[15 0] HTCPU_DWN_[15 0] HTCPU_DWNCLK1 HTCPU_DWNCLK1_ HTCPU_DWNCLK0 HTCPU_DWNCLK0_ 13 13 13 13 HTCPU_DWNCNTL1 13 HTCPU_DWNCNTL1_ 13 HTCPU_DWNCNTL 13 HTCPU_DWNCNTL_ 13 MEM_MA0_CLK_H2 MEM_MA0_CLK_L2 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1 MEM_MA0_CLK_H0 MEM_MA0_CLK_L0 AG21 AG20 G19 H19 U27 U26 10,11 MEM_MA0_CS_L1 10,11 MEM_MA0_CS_L0 AC25 AA24 10,11 MEM_MA0_ODT0 AC28 10,11 10,11 10,11 10,11 10,11 10,11 MEM_MA1_CLK_H2 MEM_MA1_CLK_L2 MEM_MA1_CLK_H1 MEM_MA1_CLK_L1 MEM_MA1_CLK_H0 MEM_MA1_CLK_L0 AE20 AE19 G20 G21 V27 W27 10,11 MEM_MA1_CS_L1 10,11 MEM_MA1_CS_L0 AD27 AA25 10,11 MEM_MA1_ODT0 AC27 10,11 MEM_MA_CAS_L 10,11 MEM_MA_WE_L 10,11 MEM_MA_RAS_L AB25 AB27 AA26 10,11 MEM_MA_BANK2 10,11 MEM_MA_BANK1 10,11 MEM_MA_BANK0 N25 Y27 AA27 10,11 10,11 10,11 10,11 10,11 10,11 10,11 MEM_MA_CKE1 10,11 MEM_MA_CKE0 10,11 MEM_MA_ADD[15 0] HTCPU_DWN[15 0] HTCPU_DWN_[15 0] 13 13 11 MEM_MA_DQS_H[8 0] B 11 MEM_MA_DQS_L[8 0] 11 MEM_MA_DM[8 0] L27 M25 MEM_MA_ADD[15 0] MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0 MEM_MA_DQS_H[8 0] MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_L[8 0] MEM_MA_DM7 MEM_MA_DM6 MEM_MA_DM5 MEM_MA_DM4 MEM_MA_DM3 MEM_MA_DM2 MEM_MA_DM1 MEM_MA_DM0 MEM_MA_DM[8 0] M27 N24 AC26 N26 P25 Y25 N27 R24 P27 R25 R26 R27 T25 U25 T27 W24 AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28 D29 C29 C25 D25 E19 F19 F15 G15 AF15 AF19 AJ25 AH29 B29 E24 E18 H15 MEMORY INTERFACE A MA0_CLK_H(2) MA0_CLK_L(2) MA0_CLK_H(1) MA0_CLK_L(1) MA0_CLK_H(0) MA0_CLK_L(0) MA0_CS_L(1) MA0_CS_L(0) MA0_ODT(0) MA1_CLK_H(2) MA1_CLK_L(2) MA1_CLK_H(1) MA1_CLK_L(1) MA1_CLK_H(0) MA1_CLK_L(0) MA1_CS_L(1) MA1_CS_L(0) MA1_ODT(0) MA_CAS_L MA_WE_L MA_RAS_L MA_BANK(2) MA_BANK(1) MA_BANK(0) MA_CKE(1) MA_CKE(0) MA_ADD(15) MA_ADD(14) MA_ADD(13) MA_ADD(12) MA_ADD(11) MA_ADD(10) MA_ADD(9) MA_ADD(8) MA_ADD(7) MA_ADD(6) MA_ADD(5) MA_ADD(4) MA_ADD(3) MA_ADD(2) MA_ADD(1) MA_ADD(0) MA_DQS_H(7) MA_DQS_L(7) MA_DQS_H(6) MA_DQS_L(6) MA_DQS_H(5) MA_DQS_L(5) MA_DQS_H(4) MA_DQS_L(4) MA_DQS_H(3) MA_DQS_L(3) MA_DQS_H(2) MA_DQS_L(2) MA_DQS_H(1) MA_DQS_L(1) MA_DQS_H(0) MA_DQS_L(0) MA_DM(7) MA_DM(6) MA_DM(5) MA_DM(4) MA_DM(3) MA_DM(2) MA_DM(1) MA_DM(0) MA_DATA(63) MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54) MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43) MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33) MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22) MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11) MA_DATA(10) MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0) MA_DQS_H(8) MA_DQS_L(8) MA_DM(8) MA_CHECK(7) MA_CHECK(6) MA_CHECK(5) MA_CHECK(4) MA_CHECK(3) MA_CHECK(2) MA_CHECK(1) MA_CHECK(0) AE14 AG14 AG16 AD17 AD13 AE13 AG15 AE16 AG17 AE18 AD21 AG22 AE17 AF17 AF21 AE21 AF23 AE23 AJ26 AG26 AE22 AG23 AH25 AF25 AJ28 AJ29 AF29 AE26 AJ27 AH27 AG29 AF27 E29 E28 D27 C27 G26 F27 C28 E27 F25 E25 E23 D23 E26 C26 G23 F23 E22 E21 F17 G17 G22 F21 G18 E17 G16 E15 G13 H13 H17 E16 E14 G14 MEM_MA_DATA[0 63] MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA61 MEM_MA_DATA60 MEM_MA_DATA59 MEM_MA_DATA58 MEM_MA_DATA57 MEM_MA_DATA56 MEM_MA_DATA55 MEM_MA_DATA54 MEM_MA_DATA53 MEM_MA_DATA52 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA49 MEM_MA_DATA48 MEM_MA_DATA47 MEM_MA_DATA46 MEM_MA_DATA45 MEM_MA_DATA44 MEM_MA_DATA43 MEM_MA_DATA42 MEM_MA_DATA41 MEM_MA_DATA40 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA37 MEM_MA_DATA36 MEM_MA_DATA35 MEM_MA_DATA34 MEM_MA_DATA33 MEM_MA_DATA32 MEM_MA_DATA31 MEM_MA_DATA30 MEM_MA_DATA29 MEM_MA_DATA28 MEM_MA_DATA27 MEM_MA_DATA26 MEM_MA_DATA25 MEM_MA_DATA24 MEM_MA_DATA23 MEM_MA_DATA22 MEM_MA_DATA21 MEM_MA_DATA20 MEM_MA_DATA19 MEM_MA_DATA18 MEM_MA_DATA17 MEM_MA_DATA16 MEM_MA_DATA15 MEM_MA_DATA14 MEM_MA_DATA13 MEM_MA_DATA12 MEM_MA_DATA11 MEM_MA_DATA10 MEM_MA_DATA9 MEM_MA_DATA8 MEM_MA_DATA7 MEM_MA_DATA6 MEM_MA_DATA5 MEM_MA_DATA4 MEM_MA_DATA3 MEM_MA_DATA2 MEM_MA_DATA1 MEM_MA_DATA0 J28 J27 MEM_MA_DQS_H8 MEM_MA_DQS_L8 J25 MEM_MA_DM8 MEM_MA_CHECK[7 0] MEM_MA_CHECK7 MEM_MA_CHECK6 MEM_MA_CHECK5 MEM_MA_CHECK4 MEM_MA_CHECK3 MEM_MA_CHECK2 MEM_MA_CHECK1 MEM_MA_CHECK0 K25 J26 G28 G27 L24 K27 H29 H27 MEM_MA_DATA[0 63] 11 D C B MEM_MA_CHECK[7 0] 11 A A Title M2 HT/DDR 0-63 Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet of 39 CPU1C MEM_MB0_CLK_H2 MEM_MB0_CLK_L2 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 MEM_MB0_CLK_H0 MEM_MB0_CLK_L0 AJ19 AK19 A18 A19 U31 U30 10,12 MEM_MB0_CS_L1 10,12 MEM_MB0_CS_L0 AE30 AC31 10,12 MEM_MB0_ODT0 AD29 10,12 10,12 10,12 10,12 10,12 10,12 D MEM_MB1_CLK_H2 MEM_MB1_CLK_L2 MEM_MB1_CLK_H1 MEM_MB1_CLK_L1 MEM_MB1_CLK_H0 MEM_MB1_CLK_L0 AL19 AL18 C19 D19 W29 W28 10,12 MEM_MB1_CS_L1 10,12 MEM_MB1_CS_L0 AE29 AB31 10,12 MEM_MB1_ODT0 AD31 10,12 MEM_MB_CAS_L 10,12 MEM_MB_WE_L 10,12 MEM_MB_RAS_L AC29 AC30 AB29 10,12 MEM_MB_BANK2 10,12 MEM_MB_BANK1 10,12 MEM_MB_BANK0 N31 AA31 AA28 10,12 10,12 10,12 10,12 10,12 10,12 10,12 MEM_MB_CKE1 10,12 MEM_MB_CKE0 10,12 MEM_MB_ADD[15 0] C 12 MEM_MB_DQS_H[8 0] B 12 MEM_MB_DQS_L[8 0] 12 MEM_MB_DM[8 0] M31 M29 MEM_MB_ADD[15 0] MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0 MEM_MB_DQS_H[8 0] MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_L[8 0] MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0 MEM_MB_DM[8 0] N28 N29 AE31 N30 P29 AA29 P31 R29 R28 R31 R30 T31 T29 U29 U28 AA30 AK13 AJ13 AK17 AJ17 AK23 AL23 AL28 AL29 D31 C31 C24 C23 D17 C17 C14 C13 AJ14 AH17 AJ23 AK29 C30 A23 B17 B13 MEMORY INTERFACE B MB0_CLK_H(2) MB0_CLK_L(2) MB0_CLK_H(1) MB0_CLK_L(1) MB0_CLK_H(0) MB0_CLK_L(0) MB0_CS_L(1) MB0_CS_L(0) MB0_ODT(0) MB1_CLK_H(2) MB1_CLK_L(2) MB1_CLK_H(1) MB1_CLK_L(1) MB1_CLK_H(0) MB1_CLK_L(0) MB1_CS_L(1) MB1_CS_L(0) MB1_ODT(0) MB_CAS_L MB_WE_L MB_RAS_L MB_BANK(2) MB_BANK(1) MB_BANK(0) MB_CKE(1) MB_CKE(0) MB_ADD(15) MB_ADD(14) MB_ADD(13) MB_ADD(12) MB_ADD(11) MB_ADD(10) MB_ADD(9) MB_ADD(8) MB_ADD(7) MB_ADD(6) MB_ADD(5) MB_ADD(4) MB_ADD(3) MB_ADD(2) MB_ADD(1) MB_ADD(0) MB_DQS_H(7) MB_DQS_L(7) MB_DQS_H(6) MB_DQS_L(6) MB_DQS_H(5) MB_DQS_L(5) MB_DQS_H(4) MB_DQS_L(4) MB_DQS_H(3) MB_DQS_L(3) MB_DQS_H(2) MB_DQS_L(2) MB_DQS_H(1) MB_DQS_L(1) MB_DQS_H(0) MB_DQS_L(0) MB_DM(7) MB_DM(6) MB_DM(5) MB_DM(4) MB_DM(3) MB_DM(2) MB_DM(1) MB_DM(0) MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55) MB_DATA(54) MB_DATA(53) MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44) MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33) MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23) MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12) MB_DATA(11) MB_DATA(10) MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1) MB_DATA(0) MB_DQS_H(8) MB_DQS_L(8) MB_DM(8) MB_CHECK(7) MB_CHECK(6) MB_CHECK(5) MB_CHECK(4) MB_CHECK(3) MB_CHECK(2) MB_CHECK(1) MB_CHECK(0) AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13 MEM_MB_DATA[0 63] MEM_MB_DATA63 MEM_MB_DATA62 MEM_MB_DATA61 MEM_MB_DATA60 MEM_MB_DATA59 MEM_MB_DATA58 MEM_MB_DATA57 MEM_MB_DATA56 MEM_MB_DATA55 MEM_MB_DATA54 MEM_MB_DATA53 MEM_MB_DATA52 MEM_MB_DATA51 MEM_MB_DATA50 MEM_MB_DATA49 MEM_MB_DATA48 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA45 MEM_MB_DATA44 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA41 MEM_MB_DATA40 MEM_MB_DATA39 MEM_MB_DATA38 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA35 MEM_MB_DATA34 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA31 MEM_MB_DATA30 MEM_MB_DATA29 MEM_MB_DATA28 MEM_MB_DATA27 MEM_MB_DATA26 MEM_MB_DATA25 MEM_MB_DATA24 MEM_MB_DATA23 MEM_MB_DATA22 MEM_MB_DATA21 MEM_MB_DATA20 MEM_MB_DATA19 MEM_MB_DATA18 MEM_MB_DATA17 MEM_MB_DATA16 MEM_MB_DATA15 MEM_MB_DATA14 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10 MEM_MB_DATA9 MEM_MB_DATA8 MEM_MB_DATA7 MEM_MB_DATA6 MEM_MB_DATA5 MEM_MB_DATA4 MEM_MB_DATA3 MEM_MB_DATA2 MEM_MB_DATA1 MEM_MB_DATA0 J31 J30 MEM_MB_DQS_H8 MEM_MB_DQS_L8 J29 MEM_MB_DM8 K29 K31 G30 G29 L29 L28 H31 G31 MEM_MB_CHECK7 MEM_MB_CHECK6 MEM_MB_CHECK5 MEM_MB_CHECK4 MEM_MB_CHECK3 MEM_MB_CHECK2 MEM_MB_CHECK1 MEM_MB_CHECK0 MEM_MB_CHECK[7 0] MEM_MB_DATA[0 63] 12 D C B MEM_MB_CHECK[7 0] 12 A A Title DDR MEM 64-127 Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet of 39 +5V +2.5V +2.5V 1 C45 C3 + 1UF 16V 0805 Y5V CT1 10UF 10V 0805 Y5V C4 C48 10UF 10V 0805 Y5V 1UF 16V 0805 Y5V R40 49.9 1% 0402 R1 I O A Q14 C16 10UF 10V 0805 Y5V 100UF 16V 5X11 2mm D LAYOUT: PLACE 169 OHM WITHIN 600mils OF CPU AND TRACE TO AC CAPS LESS THAN 1250mil MISC C10 D10 BC4 0.1UF 16V Y5V 0402 13 A8 B8 C44 CPU_CLK_ CPU_CLK* HTCPU_PWRGD HTCPU_STOP_ HTCPU_RST_ 1 BC3 1UF 10V Y5V C43 3900P 50V X7R 0402 +1.8V_SUS R87 AL3 1K 1% 0402 R89 R91 1 300 0402 AL6 300 0402 AK6 R85 C 18 18 C9 D8 C7 300 0402 /NI THERM_SIC THERM_SID AL10 AJ10 AH10 AL9 A5 ROUTE AS DIFF PAIR 10/5/5/5/10 CPU_CORE_FB CPU_CORE_FB_ 31 CPU_CORE_FB 31 CPU_CORE_FB_ TP_VDDIOSENSE1 +1.8V_SUS +1.8V_SUS R92 R93 R53 R54 R55 R56 1 1 RN8 330 8P4R TP /NI G2 G1 E12 CPU_M_VREFF F12 39.2 1% 0402AH11 39.2 1% 0402AJ11 2 2 510 0402 510 0402 300 0402 300 0402 A10 B10 F10 E9 AJ7 F6 D6 E7 F8 C5 AH9 13 HTCPU_STOP_ 13 HTCPU_PWRGD 13 HTCPU_RST_ B 33,34 CPU_THERMDC 33 CPU_THERMDA E5 AJ5 AG9 AG8 AH7 AJ6 VDDA1 VDDA2 RN26 330 8P4R CLKIN_H CLKIN_L PWROK LDTSTOP_L RESET_L CPU_PRESENT_L SIC SID TDI TRST_L TCK TMS DBREQ_L VDD_FB_H VDD_FB_L VTT_SENSE M_VREF M_ZN M_ZP TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9 TEST17 TEST16 TEST15 TEST14 TEST12 TEST7 TEST6 THERMDC THERMDA TEST3 TEST2 31 31 31 31 31 K8_VID0 31 VID(5) VID(4) VID(3) VID(2) VID(1) VID(0) THERMTRIP_L PROCHOT_L TDO D2 D1 C1 E3 E2 E1 VID4 VID3 VID2 VID1 VID0 CPU_THERMTRIP AK7 AL7 PROCHOT CPU_THERMTRIP_ 13 13 TP_CPU_TDO1 TP /NI AK10 C DBRDY VDDIO_FB_H VDDIO_FB_L PSI_L HTREF1 HTREF0 TEST29_H TEST29_L CPU_DBREQ1 TP /NI TP /NI TP_VDDIOFB1 TP_VDDIOFB_1 TP /NI B6 AK11 AL11 F1 +1.2V_HT V8 V7 R62 R61 C11 D11 FBCLKOUT FBCLKOUT* 44.2 1% 0402 44.2 1% 0402 2 LAYOUT: PLACE WITHIN INCH OF CPU 5/10 CPU_CLK 3900P 50V X7R 0402 R59 169 1% 0402 2 BR2 16.9 1% 0402 CPU_CLK 1 11 13 K8_VID5 K8_VID4 K8_VID3 K8_VID2 K8_VID1 R57 80.6 1% 0402 8/5/8/20 LAYOUT: ROUTE 80 OHM DIFF IMPEDENCE LAYOUT: PLACE WITHIN INCH OF CPU TEST24 TEST23 TEST22 TEST21 TEST20 TEST28_H TEST28_L TEST27 TEST26 TEST10 TEST8 AK8 AH8 AJ9 AL8 AJ8 J10 H9 AK9 AK5 G7 D4 CPU_M_VREFF +1.8V_SUS CPU1D Vout=Vref (1.25V) X ( 1+R2/R1 ) =2.5V BR1 16.9 1% 0402 D ROUTE AS DIF 5/5/5/20 R2 R39 54.9 1% 0402 AZ1117H-ADJ SOT-223 +1.8V_SUS R94 300 0402 +1.8V_SUS R88 B 300 0402 A A Title M2 CNTL/STRAPS Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet of 39 +1.8V_SUS +1.2V_HT_CPU +V_CPU BC1 1UF 10V Y5V +V_CPU CPU1F C B A VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD150 VDD151 +V_CPU CPU1G VDD1 A4 A6 AA8 AA10 AA12 AA14 AA16 AA18 AB7 AB9 AB11 AC4 AC5 AC8 AC10 AD2 AD3 AD7 AD9 AE10 AF7 AF9 AG4 AG5 AG7 AH2 AH3 B3 B5 B7 C2 C4 C6 C8 D3 D5 D7 D9 E4 E6 E8 E10 F5 F7 F9 F11 G6 G8 G10 G12 H7 H11 H23 J8 J12 J14 J16 J18 J20 J22 J24 K7 K9 K11 K13 K15 K17 K19 K21 K23 L4 L5 L8 L10 L12 Y17 Y19 PLACE AT CPU SOCKET SOLDER SIDE CPU1H VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS240 VSS241 A3 A7 A9 A11 AA4 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5 AE9 AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 Y14 Y16 L14 L16 L18 M2 M3 M7 M9 M11 M13 M15 M17 M19 N8 N10 N12 N14 N16 N18 P7 P9 P11 P13 P15 P17 P19 R4 R5 R8 R10 R12 R14 R16 R18 R20 T2 T3 T7 T9 T11 T13 T15 T17 T19 T21 U8 U10 U12 U14 U16 U18 U20 V9 V11 V13 V15 V17 V19 V21 W4 W5 W8 W10 W12 W14 W16 W18 W20 Y2 Y3 Y7 Y9 Y11 Y13 Y15 Y21 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 +1.2V_HT_CPU VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 AK20 AK22 AK24 AK26 AK28 AK30 AL5 B4 B9 B11 B14 B16 B18 B20 B22 B24 B26 B28 B30 C3 D14 D16 D18 D20 D22 D24 D26 D28 D30 E11 F4 F14 F16 F18 F20 F22 F24 F26 F28 F30 G9 G11 H8 H10 H12 H14 H16 H18 H22 H24 H26 H28 H30 J4 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 K2 K3 K8 K10 K12 K14 K16 K18 K20 K22 Y18 AA20 AA22 AB13 AB15 AB17 AB19 AB21 AB23 AC12 AC14 AC16 AC18 AC20 AC22 AD11 AD23 AE12 AF11 L20 L22 M21 M23 N20 N22 P21 P23 R22 T23 U22 V23 W22 Y23 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 N17 N19 N21 N23 P2 P3 P8 P10 P12 P14 P16 P18 P20 P22 R7 R9 R11 R13 R15 R17 R19 R21 R23 T8 T10 T12 T14 T16 T18 T20 T22 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 W7 Y20 Y22 D CPU1I +1.2V_HT +0.9V_SUS VDD3 VDD2 C147 1UF 16V 0805 Y5V C143 10UF 10V 0805 Y5V D +V_CPU 2 ADD FOR EMI PLACE NEAR C80 C62 1UF 16V 0805 Y5V C68 10UF 10V 0805 Y5V VDDIO AJ4 AJ3 AJ2 AJ1 D12 C12 B12 A12 AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30 AF30 M24 M26 M28 M30 P24 P26 P28 P30 T24 T26 T28 T30 V25 V26 V28 V30 Y24 Y26 Y28 Y29 +1.8V_SUS VLDT_A1 VLDT_A2 VLDT_A3 VLDT_A4 VLDT_B1 VLDT_B2 VLDT_B3 VLDT_B4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT1 VTT2 VTT3 VTT4 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO29 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 H6 H5 H2 H1 AK12 AJ12 AH12 AG12 AL12 +0.9V_SUS K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10 M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15 C B A Title M2 PWR/GND Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet of 39 DECOUPLING BETWEEN PROCESSOR AND DIMMS PLACE AS CLOSE TO PROCESSOR AS POSSIBLE C162 BC14 BC10 BC7 1UF 16V 0805 Y5V D 1UF 16V 0805 Y5V 1UF 16V 0805 Y5V 2 1UF 16V 0805 Y5V /NI 2 1UF 16V 0805 Y5V BC24 D 1 1 +1.8V_SUS +V_CPU C135 C46 C144 C49 1UF 16V 0805 Y5V 1UF 16V 0805 Y5V 2 0.1UF 16V Y5V 0402 /NI 1UF 16V 0805 Y5V BC12 100UF 2V CD 1 1 +0.9V_SUS C153 C34 C150 C41 1UF 10V Y5V 0.1UF 16V Y5V 0402 1UF 10V Y5V 1UF 10V Y5V +1.8V_SUS PLACE BOTTOM SIDE DECOUPLING BC17 1UF 16V 0805 Y5V BC20 C167 1UF 16V 0805 Y5V 0.1UF 16V Y5V 0402 1UF 16V 0805 Y5V C54 1UF 16V 0805 Y5V 1UF 16V 0805 Y5V 10UF 10V 0805 Y5V 1 BC2 BC15 2 10UF 10V 0805 Y5V 1UF 16V 0805 Y5V BC23 BC6 BC22 1 1 1 +V_CPU C 1UF 10V Y5V C39 C 1 1 +0.9V_SUS B B BC9 BC5 1UF 16V 0805 Y5V 1UF 10V Y5V 2 BC26 1UF 16V 0805 Y5V 1UF 10V Y5V BC19 10UF 10V 0805 Y5V 2 1 BC8 1UF 16V 0805 Y5V C47 C159 0.1UF 16V Y5V 0402 /NI 2 C140 0.1UF 16V Y5V 0402 1UF 10V Y5V C56 1UF 10V Y5V 1 1 BC21 1UF 16V 0805 Y5V +0.9V_SUS C164 BC11 1UF 16V 0805 Y5V +1.8V_SUS A 1 BC16 1UF 16V 0805 Y5V 2 BC13 10UF 10V 0805 Y5V BC25 1UF 16V 0805 Y5V BC18 1 +V_CPU 0.1UF 16V Y5V 0402 A Title M2 DECOUPLING Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet of 39 1 5,11 MEM_MA1_CLK_H2 C154 C155 1.5P 50V NPO 0402 5,11 MEM_MA0_CLK_L2 5,11 MEM_MA1_CLK_L2 5,11 MEM_MA0_CLK_H1 5,11 MEM_MA1_CLK_H1 C152 6,12 MEM_MB0_CLK_L2 C40 6,12 MEM_MB0_CLK_H1 6,12 MEM_MB0_CLK_L1 C C104 6,12 MEM_MB0_CLK_H0 6,12 MEM_MB0_CLK_L0 C38 C105 5,11 MEM_MA1_CLK_L0 6,12 MEM_MB1_CLK_H2 C151 5,11 MEM_MA0_CLK_L0 6,12 MEM_MB0_CLK_H2 5,11 MEM_MA1_CLK_H0 6,12 MEM_MB1_CLK_L2 6,12 MEM_MB1_CLK_H1 C42 C106 5,11 MEM_MA0_CLK_H0 5,11 MEM_MA1_CLK_L1 6,12 MEM_MB1_CLK_L1 6,12 MEM_MB1_CLK_H0 C107 C35 5,11 MEM_MA0_CLK_L1 1.5P 50V NPO 04021.5P 50V NPO 04021.5P 50V NPO 04021.5P 50V NPO 04021.5P 50V NPO 0402 D 6,12 MEM_MB1_CLK_L0 LAYOUT: FRONT SIDE PLACE ALTERNATING GND AND 1.8V ALONG 0.9V VTT FILL 1.5P 50V NPO 04021.5P 50V NPO 0402 1.5P 50V NPO 0402 1.5P 50V NPO 0402 1.5P 50V NPO 0402 1.5P 50V NPO 0402 +0.9V_SUS 5,11 MEM_MA0_CLK_H2 +0.9V_SUS MEM_MA_ADD[15 0] 5,11 MEM_MA_ADD[15 0] RN24 MEM_MB_BANK0 MEM_MB_RAS_L MEM_MB1_CS_L0 MEM_MB0_CS_L0 MEM_MB_ADD1 MEM_MA_ADD3 MEM_MB_ADD3 MEM_MA_ADD4 MEM_MA_RAS_L MEM_MA_ADD0 MEM_MB_BANK1 MEM_MB_ADD10 MEM_MB_ADD15 MEM_MA_ADD11 MEM_MA_ADD9 MEM_MA_ADD12 MEM_MB1_ODT0 MEM_MA1_ODT0 MEM_MA0_ODT0 MEM_MB_CAS_L MEM_MA_CKE1 MEM_MA_CKE0 MEM_MA_ADD15 MEM_MB_BANK2 RN19 RN23 RN12 RN25 RN9 RN29 MEM_MB0_ODT0 MEM_MB1_CS_L1 MEM_MA0_CS_L1 MEM_MB0_CS_L1 MEM_MA_BANK1 MEM_MB_ADD0 MEM_MA_ADD10 MEM_MA_BANK0 RN22 MEM_MB_ADD[15 0] 6,12 MEM_MB_ADD[15 0] 47 8P4R MEM_MB_ADD12 MEM_MB_ADD9 MEM_MB_ADD11 MEM_MB_ADD7 47 8P4R MEM_MA_ADD6 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MB_ADD14 47 8P4R MEM_MA_ADD5 MEM_MB_ADD8 MEM_MB_ADD5 MEM_MB_ADD6 47 8P4R MEM_MB_ADD4 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MB_ADD2 MEM_MB_WE_L MEM_MA_WE_L MEM_MA0_CS_L0 MEM_MA1_CS_L0 MEM_MB_CKE0 MEM_MA_ADD14 MEM_MB_CKE1 MEM_MA_BANK2 MEM_MA_CAS_L MEM_MA_ADD13 MEM_MB_ADD13 MEM_MA1_CS_L1 47 8P4R 47 8P4R 47 8P4R RN14 47 8P4R RN11 47 8P4R RN17 47 8P4R RN20 47 8P4R RN27 47 8P4R RN10 47 8P4R RN28 47 8P4R D C 47 8P4R +0.9V_SUS +0.9V_SUS B +1.8V_SUS +1.8V_SUS C156 0.1UF 16V Y5V 0402 C95 0.1UF 16V Y5V 0402 C50 0.1UF 16V Y5V 0402 C57 0.1UF 16V Y5V 0402 +1.8V_SUS C165 C55 +1.8V_SUS C84 0.1UF 16V Y5V 0402 C67 0.1UF 16V Y5V 0402 C51 0.1UF 16V Y5V 0402 C148 1UF 10V Y5V C157 0.1UF 16V Y5V 0402 C53 0.1UF 16V Y5V 0402 C100 0.1UF 16V Y5V 0402 C145 0.1UF 16V Y5V 0402 C37 0.1UF 16V Y5V 0402 5,11 5,11 5,11 5,11 5,11 5,11 MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2 MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15 C119 C120 C69 C130 C129 C124 C111 C96 C99 C98 C91 C92 C87 C80 C88 C75 C116 C81 C76 C134 C70 C63 6,12 6,12 6,12 6,12 6,12 6,12 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2 MEM_MB_CAS_L MEM_MB_WE_L MEM_MB_RAS_L MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15 C115 C110 C64 C125 C126 C121 C112 C93 C97 C94 C89 C90 C82 C77 C83 C71 C117 C78 C72 C131 C65 C66 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 22P 50V NPO 0402 B 1UF 10V Y5V 1UF 16V 0805 Y5V 5,11 MEM_MA_BANK0 5,11 MEM_MA_BANK1 5,11 MEM_MA_BANK2 5,11 MEM_MA_CKE0 5,11 MEM_MA_CKE1 6,12 MEM_MB_BANK0 6,12 MEM_MB_BANK1 6,12 MEM_MB_BANK2 6,12 MEM_MB_CKE0 6,12 MEM_MB_CKE1 A A 5,11 5,11 5,11 5,11 MEM_MA0_CS_L0 MEM_MA0_CS_L1 MEM_MA1_CS_L0 MEM_MA1_CS_L1 6,12 MEM_MB0_CS_L0 6,12 MEM_MB0_CS_L1 6,12 MEM_MB1_CS_L1 6,12 MEM_MB1_CS_L0 5,11 MEM_MA0_ODT0 5,11 MEM_MA1_ODT0 6,12 MEM_MB0_ODT0 6,12 MEM_MB1_ODT0 Title 5,11 MEM_MA_CAS_L 5,11 MEM_MA_WE_L 5,11 MEM_MA_RAS_L 6,12 MEM_MB_CAS_L 6,12 MEM_MB_WE_L 6,12 MEM_MB_RAS_L Size Document Number Custom DDR ADD/CTL/VTT TERMINATI Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 10 of 39 D D FLOPPY CONNECTOR R233 150 1% 0402 D15 SS12/5817 SMA A K +3.3V_VBAT VBATREF A K 1K 1% 0402 D16 BAT1 SS12/5817 SMA BATTERY HOLDER-1 RN33 150 8P4R 10 12 14 16 18 20 22 24 26 28 30 32 34 11 13 15 17 19 21 23 25 27 29 31 33 18,33 R240 C333 C332 1UF 10V Y5V 10UF 10V 0805 Y5V C FDD1 +3.3V_STBY +5V FRWC- 33 FINDEXFMOAFDSBFDSAFMOBFDIRFSTEPFWDFWENFTRAK0FWPFRDATAFHEADFDSKCHG- 33 33 33 33 33 33 33 33 33 33 33 33 33 33 C BOX 2X17 N5 T C257 0.1UF 16V Y5V 0402 /NI KB_FB_VCC5L KB_FB_VCC5L 33 KDAT 33 KCLK 33 MDAT 33 MCLK KDAT FB2 BEAD 60 0805 1A FB3 KB_FB_VCC5 C2 0.1UF 16V Y5V 0402 RN6 2.2K 8P4R FB_KDAT FB4 MDAT FB5 FB_KCLK BEAD 60 0805 1A FB_MDAT BEAD 60 0805 1A MCLK FB6 MINI DIN CONN PC99 10 11 12 BEAD 60 0805 1A KCLK JKBMS1 FOR EMI FB_MCLK BEAD 60 0805 1A C10 C9 C8 C6 47P 50V NPO 0402 47P 50V NPO 0402 47P 50V NPO 0402 FOR EMI 47P 50V NPO 0402 G1 G2 G3 G4 G5 MTH'S KEYBOARD & MOUSE B B Data Switch solution A A Title FLOOY ,KEYBOARD & MOUSE ,CMOS CLEAR Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 25 of 39 A B C D E 4 MCP61 SPI CLK STRAP SPI_DO|SPI_CLK 00 = 500KHZ 01 = 1.8MHZ 10 = 2.5MHZ *11 = 25MHZ *DEFAULT +3.3V_STBY +3.3V_STBY R190 +3.3V_STBY 10K 1% 0402 18 18 18 18 SPI_CS SPI_CLK SPI_DO SPI_DI SPI_8 SPI_7 R192 R193 10K 1% 0402 U18 10K 1% 0402 VDD CE# HOLD# SO SCK WP# SI Vss R209 15 0402 SPI SOCKET 8PIN SPI_MISO_1 R191 R194 10K 1% 0402 /NI C269 10K 1% 0402 /NI 0.1UF 16V Y5V 0402 +3.3V R1347 10K 1% 0402 ICH_WPJ C168 1000P 50V X7R R210 10K 1% 0402 /NI FOR EMI 2 1 Title SPI ROM Size Document Number Custom Date: A B C D Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet E 26 of 39 R97 FOR EMI USB LAN KB_FB_VCC5L USB 0402 USB_PWR C36 D R58 JUSBLAN1A 0.1UF 16V Y5V 0402 B1 VCC0 FOR EMI USB_PWR C108 USB_1_0_OC_ 18 UST3- B2 UST3+ B3 B4 G1 G2 DATA0DATA0+ UST2- A2 C118 C122 C113 C114 CT10 10P 50V NPO 0402 10P 50V NPO 0402 10P 50V NPO 0402 100UF 16V 5X11 2mm 10P 50V NPO 0402 UST2+ A3 A4 C161 C158 C160 C163 10P 50V NPO 0402 10P 50V NPO 0402 10P 50V NPO 0402 10P 50V NPO 0402 FOR EMI NEAR C172 USB SIGNAL VIA C343 C33 0.1UF 0.1UF 16V Y5V 16V 0402Y5V 0402 C25 0.1UF 16V Y5V 0402 GND0 FOR EMI NEAR JCDIN1 USB_2 SIGNAL VIA G3 GND2 A1 USB CONN FB1 D FOR EMI 0805 /NI UST0UST0+ UST1UST1+ 18 +5V 0.1UF 16V Y5V 0402 PS1 POLY FUSE 1.1A JUSB1 0.1UF 16V Y5V 0402 G3 G4 USB_3_2_OC_ C137 +5V_DUAL G4 GND3 VCC1 G5 GND4 DATA1- G6 GND5 DATA1+ GND1 LANUSB_GBMA 0805 H3 USB_3_ 18 USB_3 18 USB_2_ 18 USB_2 18 8 UST3- UST3+ UST2- UST2+ C C SMD CHOKE 0.5A/90U /NI RN21 18 18 18 18 USB_0 USB_0_ USB_1 USB_1_ RN30 UST0+ UST0UST1+ UST1- 18 18 18 18 USB_2 USB_2_ USB_3 USB_3_ 10 8P4R USB_5_ 1 R267 USB_5 18 USB_4_ 18 USB_4 7 UST5+ UST4- UST4+ C318 0.1UF 16V Y5V 0402 C109 0.1UF 16V Y5V 0402 C169 0.1UF 16V Y5V 0402 +5V +5V_DUAL UST5- B 18 UST2+ UST2UST3+ UST3- 10 8P4R H1 18 VER095 FOR EMI PS2 0805 /NI POLY FUSE 1.1A USBPWR USB_7_6_OC_ B USBPWR 18 USB_9_8_OC_ C345 SMD CHOKE 0.5A/90U /NI 18 18 RN16 18 18 18 18 USB_4 USB_4_ USB_5 USB_5_ UST4+ UST4UST5+ UST5- USB_6_ USB_6 JUSB3 10 C346 0.1UF 16V Y5V 0402 USB_7_ USB_7 HEADER 2X5 N9 T 18 18 18 JUSB4 18 18 USB_8_ USB_8 0.1UF 16V Y5V 0402 10 USB_9_ USB_9 18 18 CT43 1000UF 6.3V 8X12 HEADER 2X5 N9 T 10 8P4R USB_PWR C133 A CT13 UST4UST4+ UST5UST5+ USB_5_4_OC_ JUSB2 0.1UF 16V Y5V 0402 G3 1000UF 6.3V 8X12 G4 18 G1 G2 A USB CONN C59 C58 C61 C60 10P 50V NPO 0402 10P 50V NPO 0402 10P 50V NPO 0402 10P 50V NPO 0402 Title USB INTERFACE Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 27 of 39 +3.3V_STBY D D14 D3 1N4148 SMD R264 RN65 RN61 RN63 RN59 2.2K 0402 2.2K 8P4R 2.2K 8P4R 2.2K 8P4R 2.2K 8P4R Ver091 Update D +5V -XRI1 1N4148 SMD LPT 8 8 RN7 7 7 PARALLEL - CONNECTOR 10K 8P4R 33 33 33 33 SER_RI_ C 18 E B Q19 2N3904 SOT23 33 33 33 33 33 33 33 33 WAKE ON LAN PD3 PD2 PD1 PD0 PD7 PD6 PD5 PD4 STB# ALF# INIT# SLCTIN# P_PRD3 P_PRD2 P_PRD1 P_PRD0 RN62 33 8P4R PRD3 PRD2 PRD1 PRD0 P_PRD7 P_PRD6 P_PRD5 P_PRD4 P_-STB P_-AFD P_-INIT P_-SLIN RN64 7 33 8P4R PRD7 PRD6 PRD5 PRD4 -STB AFD -INIT -SLIN 33 ACK# 33 EEROR# -STB AFD -SLIN P_-ACK PRD2 PRD0 -INIT P_-ERR PRD1 PRD6 PRD5 PRD4 RN60 33 8P4R PRD3 C C PRD7 COM1 +5V +12V JCOM1 D CONN 9PIN PC99 U4 DCD1# DSR1# SINA RTS1# SOUTA CTS1# DTR1# RI1# VCC ROUT1 ROUT2 ROUT3 DIN1 DIN2 ROUT4 DIN3 ROUT5 GND V+ RIN1 RIN2 RIN3 DOUT1 DOUT2 RIN4 DOUT3 RIN5 V- 10 RIN1 RIN2 RIN3 DOUT1 DOUT2 RIN4 DOUT3 -XRI1 ST75185CTR TSSOP C22 C23 C24 C26 C27 C28 C29 C30 -12V BUSY 33 PE 33 SLCT P_BUSY P_PE P_SLCT COM PORT G2 G1 FOR EMI 220P 50V X7R 0402 /NI 220P 50V X7R 0402 /NI 220P 50V X7R 0402 /NI 220P 50V X7R 0402 /NI 220P 50V X7R 0402 /NI 220P 50V X7R 0402 /NI 220P 50V X7R 0402 /NI 220P 50V X7R 0402 /NI PRD3 PRD4 PRD5 PRD6 PRD1 -SLIN -INIT PRD2 -STB AFD PRD0 P_-ERR 33 33 33 33 33 33 33 33 20 19 18 17 16 15 14 13 12 11 33 FOR EMI -STB PRD0 PRD1 PRD2 PRD3 PRD4 PRD5 PRD6 PRD7 P_-ACK P_BUSY P_PE P_SLCT B 11 13 15 17 19 21 23 25 JPRNT1 HEADER 2X13 N26 AFD P_-ERR -INIT -SLIN 10 12 14 16 18 20 22 24 B A A Title SERIAL & PARALLEL Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 28 of 39 ALC861VD : PORT D, E, F SUPPORT RE-TASKING(PIN#14, 15, 16, 17, 35, 36) ALC883/8 : B,C,E,F PORTS SUPPORT RE-TASKING 30 30 MIC2_L MIC2_R AC16 10UF 10V 0805 Y5V 100UF 16V 5X11 2mm 100UF 16V 5X11 2mm CD_GND AC20 1UF 10V Y5V CD_R AC19 1UF 10V Y5V MIC2_L AC23 10UF 10V 0805 Y5V MIC2_R AC22 10UF 10V 0805 Y5V PORT-E-L PORT-E-R FRONT_JD MIC1_JD SURR_JD LINE1_JD AR16 AR15 AR2 AR17 5.1K 1% 0402 20K 1% 0402 39.2K 1% 0402 10K 1% 0402 PORT-F-L PORT-F-R SENSE_A 30 SIDE_BACK_L 30 SIDE_BACK_R SIDE_BACK_L SIDE_BACK_R + + FRONT_JD MIC1_JD SURR_JD LINE1_JD ACT9 ACT5 PORT-H-L PORT-H-R 100UF 16V 5X11 2mm 100UF 16V 5X11 2mm KA LINE2_VREFO 26 42 LINE-IN AQ5 BAT54A SOT23 AC25 1UF 10V Y5V 24,30,36 GND_AUD LINE2_L LINE2_R LINE1_L AC15 10UF 10V 0805 Y5V LINE1_R AC18 10UF 10V 0805 Y5V MIC1_L AC17 10UF 10V 0805 Y5V MIC1_R ACT4 100UF 16V 5X11 2mm ACT3 100UF 16V 5X11 2mm 100UF 16V 5X11 2mm ACT8 EXT_VOL_CTRL JDREF SPDIFO MIC1_VREFO LINE1_VREFO MIC2_VREFO LINE2_VREFO SPDIFO 30 30 30 AR28 AR3 VCC3_L 30 LINE1_R 30 MIC1_L 30 MIC1_R 30 CEN_OUT 30 LFE_OUT 30 SURR_L 30 SURR_R 30 FRONT_IO_SENSE CEN_JD 30 SIDE_JD 30 10K 1% 0402CEN_JD 5.1K 1% 0402SIDE_JD AC26 10UF 10V 0805 Y5V 30 LINE1_L D 100UF 16V 5X11 2mm ACT11 30 LINEOUT_R MIC1_VREFO LINE1_VREFO 30 30 30 +3.3V GND_AUD +5VA MIC1 LINE2-L LINE2-R PORT-D-L PORT-D-R PORT-C-L PORT-C-R PORT-B-L PORT-B-R PORT-G-L PORT-G-R PORT-A-L PORT-A-R ALC888 LQFP48 AR29 AR31 2.2K 0402 2.2K 0402 SIDE 35 36 23 24 21 22 43 44 39 41 34 33 40 48 47 27 28 29 30 31 32 25 38 RESET# (I) FRONT_OUT_L (B) SYNC (I) FRONT_OUT_R (B) SDOUT (I) LINE_IN1_L (B) SDIN (O) LINE_IN1_R (B) BITCLK (I) MIC1_L (B) LINE_IN2_L (B) MIC1_R (B) LINE_IN2_R (B) CENTER_OUT (O) CD_L (I) LFE_OUT (O) SURR_L (B) CD_GND (I) SURR_R (B) CD_R (I) MIC2_L (B) SENSE_B (I) MIC2_R (B) DCVOL (I) SENSE_A (I) JDREF LINE1_VREFO_R (O) SPDIFO (O) SIDESURR_L (O) SPDIFI/EAPD (B) SIDESURR_R (O) VREF (O) PC_BEEP (I) MIC1_VREFO_L (O) GPIO0 (B) LINE1_VREFO-L (O) GPIO1 (B) MIC2_VREFO (O) GND1 (P) LINE2_VREFO (O) GND2 (P) MIC1_VREFO_R (O) VCC3_1 (P) VCC3_2 (P) AGND1 (P) AVCC_1 (P) AGND2 (P) AVCC_2 (P) GND_AUD LINE-OUT K SURR C 11 10 14 15 18 19 20 16 17 13 37 45 46 12 A CENBAS LINEOUT_L AU1 AC21 1UF 10V Y5V R0603 GND_AUD 30 30 30 30 LINEOUT_R KA ARN1 47K 8P4R AR30 CD_L LINEOUT_L 100UF 16V 5X11 2mm AC29 1UF 10V Y5V AC27 1UF 10V Y5V AC30 1UF 10V Y5V C AQ4 BAT54A SOT23 GND_AUD ALC861 PIN#2, 3, 29, 33, 37, 47 ARE NC PIN A LINE2_R 100UF 16V 5X11 2mm K 30 75 0402 ACT6 75 0402 ACT2 R0603 AR33 ACT10 + 47K 8P4R AC28 10P 50V NPO 0402 WAFER 1X4 BLACK CD_L CD_R CD_GND LINE2_L + ARN2 2 30 ACT7 + AC_RST_ AC_SYNC AC_SDOUT AC_SDIN_0 AC_BITCLK + JCDIN1 D + CONNECT TO SB + CD_IN 18 18 18 18 18 + + AR25 AR26 2.2K 0402 2.2K 0402 30 30 MIC2_R MIC2_L 7.1 Speaker Configuration MIC2_R MIC2_L +5VA AR27 10K 1% 0402 R0603 EXT_VOL_CTRL 861VC/VD >REMOVE 10K 888 >ADD 10K JDREF B AR32 20K 1% 0402 B 888/861VD >ADD 20K 861VC >ADD 4.99K GND_AUD PLACE CLOSE TO CODEC P04: DEL FOR ALC882 CIRCUITS AC1 0402 AR1 0805 R0603 GND_AUD GND_AUD IO_GND A A Configuration PORT-A PORT-B PORT-C PORT-D PORT-E PORT-F PORT-G PORT-H Function SURR MIC1 LINE1 LINEOUT LINE2 MIC2 CEN/LFE SIDE Location Rear Rear Rear Rear Front Front Rear Rear Title ALC888/861VD HDA CODEC Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 29 of 39 +5V Rear Panel Onboard Analog I/O FOR ALC883/888 AQ3 BAT54A SOT23 K LINE1_VREFO 29 LINE1_VREFO AR21 2.2K 0402 32 33 34 35 KA A AR22 2.2K 0402 29 LINE1_JD 29 LINE1_L 29 LINE1_R LINE1_L AL12 BEAD 60 0805 1A LINE1_LL LINE1_R AL8 BEAD 60 0805 1A LINE1_JD LINE1_RR G1 JAUDIO1A L34 AUDIO2D L32 LINE-IN L33 L31 L5 BLUE JACK AUDIOJACK 6HD PORT-C 10 G5 +12V AC14 100UF 16V 6.3X5 2.5mm SURR_JD SURR_R SURR_R AL1 BEAD 60 0805 1A R24 AUDIO2E R22 SURR-B R23 R21 AR7 22K 0402 /NI C 29 29 LINEOUT_L 29 LINEOUT_R AL11 BEAD 60 0805 1A LINEOUT_LL LINEOUT_R AL9 BEAD 60 0805 1A FRONT_JD LINEOUT_RR P2 29 CEN_OUT P1 LFE_OUT AL6 BEAD 60 0805 1A LFE_OUT AL2 BEAD 60 0805 1A SPDIF OUT +5V AC32 BEAD 60 0805 1A 2 AL13 GND_AUD AC31 1UF 16V 0805 Y5V PORT-G SPDIFO 29 WAFER 1X3 BLACK FOR EMI YELLOW JACK AR5 22K 0402 /NI ALC883/8 AC7 AC3 100P 50V NPO 0402 100P 50V NPO 0402 GND_AUD JSPDIF_OUT1 1UF 10V Y5V /NI R34 AUDIO2F R32 R33 CEN_LEF R31 AUDIOJACK 6HD P1 C PORT-D AUDIOJACK 6HD P4 Vout=Vref (1.25V) X ( 1+R2/R1 ) =5V CEN_JD CEN_OUT AR9 22K 0402 /NI 24,29,36 FOR EMI P2 29 R2 ACT1 100UF 16V 6.3X5 2.5mm AR20 390 1% 0402 GND_AUD AC12 AC10 100P 50V NPO 0402 100P 50V NPO 0402 29 AC24 1UF 10V Y5V JAUDIO1C AUDIO JACK 3HD /NI L24 AUDIO2C L22 SPK OUT L23 L21 L5 GREEN JACK AUDIOJACK 6HD CEN_JD P4 AZ1117H-ADJ SOT-223 AR12 22K 0402 /NI AUDIO2A P3 FRONT_JD LINEOUT_L AR14 22K 0402 /NI P3 22 23 24 25 AC5 AC2 100P 50V NPO 0402 100P 50V NPO 0402 AR19 130 1% 0402 + BLACK JACK AR4 22K 0402 /NI GND_AUD R1 I O A PORT-A AUDIOJACK 6HD AUDIO JACK 3HD /NI AQ1 BEAD 60 0805 1A G4 29 D + SURR_JD G4 G3 AL4 1: INTEL HD AUDIO DONGLE UNCONNECTED SURR_L SURR_L 18 0: INTEL HD AUDIO DONGLE CONNECTED GND_AUD 24,29,36 GND_AUD 29 29 GPI 39.2K 1% 0402 AR36 +5VA H1 G3 CONNECT TO SB 20K 1% 0402AR35 AUDIO ANALOG POWER AC13 AC9 100P 50V NPO 0402 100P 50V NPO 0402 G2 JAUDIOF1 HEADER 2X5 NON_PIN8 AR11 22K 0402 /NI G2 G1 AR18 22K 0402 /NI PORT-F AUDIO JACK 3HD /NI D MIC2_L MIC2_R LINE2_R FRONT_IO_SENSE LINE2_L 29 MIC2_L 29 MIC2_R 29 LINE2_R 29 FRONT_IO_SENSE 29 LINE2_L JAUDIO1D AR34 10K 1% 0402 PORT-E P07 : 3-Port & 6-Port Co-lay HDA Iterface ALC861VD Yes Yes DAC DAC 7.1Ch + Ch 7.1Ch B B 29 29 SIDE_BACK_L SIDE_JD SIDE_BACK_L AL5 BEAD 60 0805 1A SIDE_BACK_R AL3 BEAD 60 0805 1A AUDIO2G SIDE_JD 29 SIDE_BACK_R R4 R2 R3 R1 R5 SIDE_SURR AUDIOJACK 6HD FOR ALC88X/861 AQ2 BAT54A SOT23 29 MIC1_VREFO MIC1_VREFO K AR23 2.2K 0402 A AR24 2.2K 0402 AR8 22K 0402 /NI PORT-H DAC GRAY JACK AR6 22K 0402 /NI AC6 AC4 100P 50V NPO 0402 100P 50V NPO 0402 KA DAC SNR 95dB 90dB GPIO for Vref None None SPDIF-I Yes No SPDIF-O Yes Yes Re-Tasking 4-PORTS Port D,E,F JAUDIO1B AUDIO JACK 3HD /NI 29 29 MIC1_L 29 MIC1_R MIC1_JD MIC1_L AL10 BEAD 60 0805 1A MIC1_LL MIC1_R AL7 BEAD 60 0805 1A MIC1_JD MIC1_RR AUDIO2B L4 L2 L3 L1 L5 MIC-IN AUDIOJACK 6HD AR13 22K 0402 /NI A PORT-B PINK JACK AR10 22K 0402 /NI A AC11 AC8 100P 50V NPO 0402 100P 50V NPO 0402 24,29,36 GND_AUD GND_AUD *ALC883/888:B,C,E,F ports support I/P & O/P function But A,D,G,H ports not support MIC function Title AUDIO PORT Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 30 of 39 PC23 1UF 16V 0805 Y5V PL1 FDD8780 TO252 /NI FDD8780 TO252 PR19 VDIFF ISEN2+ ISEN2- +V_CPU PR6 CPU_CORE_FB PR7 PVCC3 VSEN BOOT3 RGND UGATE3 PHASE3 LGATE3 0402 17 CPU_CORE_FB_ 0402 PR8 100 1% 0402 8.2K 0402 PC10 S PQ6 27 G PR38 PR37 UG2 PR4 226 1% 0402 ISEN2 PC4 0.1UF 16V X7R 0402 PR35 LG2 PHASE2 8.2K 0402 PC3 42 PR27 2.7 0805 +12V 40 PC20 1UF 16V 0805 Y5V PC19 0.1UF 16V X7R 0402 G PQ4 PQ5 FDD8780 TO252 ISEN3 44 43 PC21 PQ9 G PC22 UG3 0.1UF 16V X7R 0402 PR42 PR41 11 45 PR12 PR21 PR30 ISEN4+ ISEN4- PC29 1UF 16V 0805 Y5V PL4 PWM4 EN_PH4 PR18 D D LG3 V_6312 PR39 2.7 0805 G PQ7 0402 /NI B H1 H2 POWER CONN ATX12V 2X2 G PQ8 23 FDD8780 TO252 PC30 1000P 50V X7R 0402 FDD8780 TO252 PC9 0402 /NI JATXPWR2 INDUCTOR 0.6UH 35A-KQ PR40 4.7 0805 21 22 24 +12V_P FDD8780 TO252FDD8780 /NI TO252 PH3 0.1UF 16V X7R 0402 OVPSEL/SDA REF FS SS/RST/A0 ISEN2 PQ12 G 2.7 0805 100K 0402 8.2K 0402 DRSEL/SCL C FDD8780 TO252 S SMB_SDA PC25 1000P 50V X7R 0402 PHASE2 S SMB_SCL 18,20,22,36,37 + G 3.3 1% 0402 PR28 GND 18,20,22,36,37 + PL2 INDUCTOR 0.6UH 35A-KQ PR29 226 1% 0402 OFS 820UF-S 2.5V 8X8 PR36 4.7 0805 2.7 0805 0.1UF 16V X7R 0402 49 12 820UF-S 2.5V 8X8 PCT8 FDD8780 TO252FDD8780 /NI TO252 VIN PR26 39 38 41 PCT10 ISEN1 PC32 1UF 16V 0805 Y5V G 2.7 0805 100K 0402 PHASE1 PH2 19 20 820UF-S 2.5V 8X8 S 3.3 1% 0402 0.1UF 16V X7R 0402 26 25 28 PCT5 PQ11 0.1UF 16V X7R 0402 PHASE3 PR29:-15mV offset PC24 1000P 50V X7R 0402 FDD8780 TO252 D PC15 0.1UF 16V X7R 0402 S ISEN3+ ISEN3- VIN ISEN1 PC16 D PR5 100 1% 0402 /NI PC5 0.01UF 50V X7R 0402 /NI PWM_OFSET 18 S PR22 226 1% 0402 PHASE1 820UF-S 2.5V 8X8 D FDD8780 TO252 PQ2 PR3 C D PCT7 PQ1 35 34 820UF-S 2.5V 8X8 G D 16 UGATE2 PHASE2 LGATE2 G S PR9 750 1% 0402 /NI BOOT2 FB IDROOP 2.7 0805 3.3 1% 0402 0.1UF 16V X7R 0402 32 33 30 PR23 PR15 COMP PR31 D PC6 470P 50V X7R 0402 /NI 14 15 LG1 820UF-S 2.5V 8X8 S 13 PC7 10P 50V NPO 0402 PC14 PCT4 PCT2 31 3900P 50V X7R 0402 PR10 2.2K 0402 D 10 ISEN1+ ISEN1- 29 D 20K 0402 BOOT1 UGATE1 PHASE1 LGATE1 INDUCTOR 0.6UH 35A-KQ PR32 4.7 0805 S VID_OUT5 VID_OUT4 VID_OUT3 VID_OUT2 VID_OUT1 VID_OUT0 PC12 1UF 16V 0805 Y5V D 7 7 7 PVCC1_2 +V_CPU PH1 S 18 CPU_VLD 18 CPUVDD_EN VCC PC18 PR20 PR24 0.1UF 16V Y5V 0402 1K 1% 0402 1K 1% 0402 37 PGOOD 36 EN PC17 0.1UF 16V Y5V 0402 46 VID7 47 VID6 48 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PR11 PC8 D PC11 1UF 16V 0805 Y5V PU1 ISL6322CR + 2.7 0805 100K 0402 + PR34 PR33 UG1 PQ10 G S V_6312 PQ3 G + PR16 PC13 PR17 2.7 0805 1UF 10V Y5V 2.7 0805 + D +3.3V_STBY +5V PR25 10K 1% 0402 VIN +12V D +5V S PHASE3 249K 1% 0402 121K 1% 0402 0.01UF 50V X7R 0402 B ISEN3 BOTTOM PAD CONNECT TO GND Through VIAs A PL3 INDUCTOR 1.0UH VIN +12V_P PCT3 + PCT6 + PCT1 ISL6322CR FOR K8 940 POWER CKT A + PC27 1UF 16V 0805 Y5V PC28 1UF 16V 0805 Y5V Title VCORE POWER SUPPLY 1500UF 16V 10X20X5 LR O 1500UF 16V 10X20X5 LR O 1500UF 16V 10X20X5 LR O Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 31 of 39 MEM_VDD MEM_STR +5V S 35 DUALS_FET_GATE +12V +5V_STBY R10 4.7K 0402 + G Q18 FDD8780 TO252 D R7 24,37 PWRGD_PS 4.7K 0402 B D +5V_DUAL C 4.7K 0402 B Q7 2N3904 SOT23 E D R9 C Q6 2N3904 SOT23 E G + CT5 1000UF 6.3V 8X12 D1 SS12/5817 SMA D R8 10K 1% 0402 + CT6 CT8 1000UF 6.3V 8X12 100UF 16V 5X11 2mm /NI G C1 D 0.1UF 16V Y5V 0402 /NI S S Q8 Q9 NDS352AP SOT23 /NI NDS352AP SOT23 /NI +5V_STBY +5V_DUAL R67 uP6103 >ADD >RA1,RA2,REMOVE >RA3,RA4,CA1,DA1 RT9214 >REMOVE >RA1,RA2,ADD >RA3,RA4,CA1,DA1 RA3 R68 L1 RH TYPE BEAD 30K 1% 0402 C79 DA1 K A RT9202NC/RT9214 2.7 0805 Q20 FDD8780 TO252 RT9202/RT9214NC 1K 1% 0402 /NI RA1 COMP BOOT UGATE R69 C85 PHASE 20K 0402 /NI C86 15P 50V NPO 0402 /NI FB LGATE 4700P 50V X7R 0402 /NI C347 1UF 16V 0805 Y5V /NI C VCC R31 R50 2.7 0805 GND 1_8V_REF R46 0805 + C31 CT7 1UF 16V 0805 Y5V 1000UF 6.3V 8X12 C74 0.1UF 25V Y5V L2 INDUCTOR 1UH D +1.8V_SUS R52 RA4 R73 + + Q21 2.7 0805 CT11 CT14 360 1% 0402 FDD8780 TO252 1000UF 6.3V 8X12 R47 R51 1000UF 6.3V 8X12 100K 0402 10K 1% 0402 /NI C32 CA1 1000P 50V X7R 0402 RA2 RT9214 SOP8 37 1UF 16V 0805 Y5V U5 R70 15K 0402 /NI D4 SS12/5817 SMA VIN_5V_DDR2 DDR2 CORE CONNECT FEEDBACK NEAR LOAD C VOUT=VREF X(1+R1/R2)=1.953V R1 +1.8VDIMM_FB 37 钡 VIA 癬ノ R72 249 1% 0402 GND R2 R74 1K 1% 0402 D +5V_DUAL SLP_S5_ R76 4.7K 0402 G Q22 S 18 10K 1% 0402 Q23 G 2N7002 SOT23 C102 C103 1UF 16V 0805 Y5V /NI 10UF 10V 0805 Y5V /NI S D R75 APM2300AAC SOT23 C101 10UF 10V 0805 Y5V /NI Ref + VOUT + CT19 +0.9V_SUS 1000UF 6.3V 8X12 100UF 16V 5X11 2mm /NI + + CT17 1000UF 6.3V 8X12 1000UF 6.3V 8X12 2.2K 8P4R RT9173BCL5 CT9 RN31 U7 B + CT16 CT12 1000UF 6.3V 8X12 GND VCTL VCTL C170 C172 1UF 16V 0805 Y5V + CT21 0.1UF 16V Y5V 0402 100UF 16V 5X11 2mm VTT_MEM +1.8V_SUS Vin +5V_STBY B +0.9V_SUS +0.9V_SUS C127 C52 C138 C132 C142 C73 0.1UF 16V Y5V 0402 0.1UF 16V Y5V 0402 0.1UF 16V Y5V 0402 /NI 0.1UF 16V Y5V 0402 0.1UF 16V Y5V 0402 /NI 0.1UF 16V Y5V 0402 A A +1.8V_SUS Title PLL DELAY / PWRGD / MEM VREG Size C Document Number Date: Wednesday, June 13, 2007 Rev 5.0 N560B-A2T Sheet 32 of 39 R45 R43 +5V KBC'S ROM:1/BUILT IN,0/EXT +5V 4.7K 0402 4.7K 0402 /NI PDR7 PDR6 PDR5 PDR4 PDR3 PDR2 PDR1 PDR0 R8 28 28 28 28 28 28 28 28 D DCD1# RI1# CTS1# DTR1# RTS1# DSR1# SOUTA SINA R44 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 STB# ALF# EEROR# INIT# SLCTIN# ACK# BUSY PE SLCT R6 680 0402 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 8716 >R6 >ADD 680 R8 >4.7K /NI 8712 >R6 >680 /NI R8 >ADD 4.7K GP35: To generate an event for the function THERMAL SHUTDOWN +5V To CK8-04 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 4.7K 8P4R 24 24 24 24 24 24 FAN1 FAN_CTL1 FAN2 FAN_CTL2 FAN3 FAN_CTL3 C 51K P/U is necessaried on IX version LPC I/O 37 37 37 37 37 37 37 24 24 +3.3V OV_LDTV1 OV_LDTV0 OV_CHIP1 OV_CHIP0 VDIMM2 VDIMM1 VDIMM0 LEDD1 LEDD0 R237 10K 1% 0402 +5V LPC_PD# LPCRST_SIO_ LPC_DRQ0_ 16 LPCRST_SIO_ 16 LPC_DRQ0_ BUSY PE SLCT VCC VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VREF TMPIN1 TMPIN2 TMPIN3 GNDA [5VSB PWR WELL] CIRRX/GP55 [5VSB PWR WELL] SCRPRES#/GP10 [5VSB PWR WELL] MCLK [5VSB PWR WELL] MDAT [5VSB PWR WELL] KCLK [5VSB PWR WELL] KDAT [5VSB PWR WELL] SCLK/GP40 [5VSB PWR WELL] SDAT/GP41 [5VSB PWR WELL] RING#/GP53 [5VSB PWR WELL] PSON#/GP42 [5VSB PWR WELL] PANSWH#/GP43 GNDD [5VSB PWR WELL] PME#/GP54 [5VSB PWR WELL] PWRON#GP44 [5VSB PWR WELL] PSIN/GP45 [5VSB PWR WELL] IRRX/GP46 VBAT [VBAT/5VSB PWR WELL] ] COPEN# VCCH IRTX/GP47 DSKCHG# DTR2# RTS2# DSR2# VCC SOUT2 SIN2 FAN_TAC1 FAN_CTL1 FAN_TAC2/GP52 FAN_CTL2/GP51 FAN_TAC3/GP37 FAN_CTL3/GP36 WTI#/GP35 VID4/GP34 GNDD VID3/GP33 VID2/GP32 VID1/GP31 VID0/GP30 JSBB2/GP27 JSBB1/GP26 JSBCY/GP25 JSBCX/GP24 JSAB2/GP23 JSAB1/GP22 JSACY/GP21 JSACX/GP20 MIDI_OUT/GP17 MIDI_IN/GP16 CIRTX/GP15 [PU51K] SCRRST/GP14 SCRFET#/GP13 SCRIO/GP12 SCRCLK/GP11 VCC LPCPD# LRESET# LDRQ# SERIRQ LFRAME LAD0 LAD1 LAD2 LAD3 KRST# GA20 PCICLK CLKRUN#/GP50 CLKIN GNDD DENSEL# MTRA# MTRB# DRVA# DRVB# WDATA# DIR# STEP# HDSEL# WGATE# RDATA# TRK0# INDEX# WPT# 18 CHIP_THERM_ 16,34 LPC_SERIRQ LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 SIO_KBRST_ A20GATE LPCCLK_SIO 18 BUF_SIO_CLK 24 MHz R228 30K 1% 0402 /NI From CPU CPU_THERMDA CPU_THERMDC C1 BEAD 60 0805 1A 34 34 34 34 34 34 34 +5V C312 2200P 50V X7R 0402 FB12 BEAD 60 0805 1A C2 8716 >C2 >ADD 2200P 8712 >C2 >ADD 3900P GP55: To provide BIOS Write Protection Function (Boot Block Lock) FWH_TBL_ SMB_ALLERT_ MCLK MDAT KCLK KDAT ACPI_LED IO_PME_ IO_POUT 4.7K 0402 21,34 +5V_STBY 1M 0402 +3.3V_VBAT 18,25 GP54: To generate an event for the function SLEEP BUTTON, POWER ON BY KB/MOUSE,RING-IN 10 0805 +5V_STBY B IO_PME_ 18 To Power Supplier PS_ON_ R218 FDSKCHGFWPFINDEXFTRAK0FRDATAFWENFHEADFSTEPFDIRFWDFDSBFDSAFMOBFMOAFRWC- BUF_SIO_CLK R274 4.7K 0402 LPC_PD# SUSCLK 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 R219 18 SUSCLK 33 0402 From Power Button 33 0402 To SB PWRBTN_ PWBTOUT_ 21,24 18 SLP_S3_ 18 C313 470P 50V X7R 0402 /NI A SMB_ALLERT_ SUSCLK 24 From SB 4.7K 8P4R R229 4.7K 0402 +5V_STBY Title LPC SUPER I/O IT8712F Size Document Number Custom Date: 34 To POWER LED circuit IO_PWIN R230 C 25 25 25 25 FOR BIOS SOLUTION R231 7,34 Routed by differential R1 C315 0.1UF 16V Y5V 0402 100UF 16V 5X11 2mm RN50 +3.3V 8716 >R7 >30K /NI 8712 >R7 >ADD 30K R7 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 SIO_KBRST_ A20GATE LPCCLK_SIO +3.3V C310 1UF 10V Y5V CT36 LPC_FRAME_ R273 4.7K 0402 A R4 R5 1UF 10V Y5V VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 D 10K 1% 0402 /NI +5V 10K 1% 0402 + 16 LPC_SERIRQ 16,34 16,34 16,34 16,34 18 18 16 R211 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VREF R214 R217 VIN3 VIN7 8712 : R1 >0 0805 8712 : C1 >1UF /NI C311 R232 16,34 LPC_FRAME_ NO USE FUNCTION ADD R4 R5 >10K IT8716FDX 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LPC_AD[3 0] 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 C314 0.1UF 16V Y5V 0402 B LPC_AD[3 0] 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 C328 0.1UF 16V Y5V 0402 8716 : R1 >BEAD 60 0805 1A 8716 : C1 >1UF U12 CTS2# RI2# DCD2# SIN1 SOUT1 DSR1# RTS1# DTR1# CTS1# RI1# DCD1# GNDD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 STB# AFD# ERR# INIT# SLIN# ACK# RN55 Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 33 of 39 D D ROM1 4MB FLASH 16,33 LPC_AD[3 0] LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 13 14 15 17 23 16,33 LPC_FRAME_ 31 16 LPCCLK_FLASH 16 LPCRST_FLASH_ FWH_WP_ 33 FWH_TBL_ FWH_TBL_ GND BIOS PROTECT FUNCTION 29 28 16 LAD0 LAD1 LAD2 LAD3 NC1 NC2 NC3 NC4 FRAME* INIT* LCLK RES1 RES2 RES3 RES4 RESET* WP* VDD1 VDD2 TBL* MODE CS* GND GPI0 GPI1 GPI2 GPI3 GPI4 C +3.3V +5V_STBY RN57 ID0 ID1 ID2 ID3 4.7K 8P4R ACPI_LED FWH_WP_ FLASH_INIT FWH_TBL_ ACPI_LED Voltage Sensing 22 26 27 24 FLASH_INIT +V_CPU 18 19 20 21 25 32 +1.2V +3.3V +5V +12V +1.8V_SUS +1.2V_HT +5V_STBY R223 R212 R224 R213 R215 R227 R216 10K 1% 0402 10K 1% 0402 30K 1% 0402 10K 1% 0402 10K 1% 0402 6.65K 1% 0402 49.9 1% 0402 +3.3V 33 33 33 33 33 33 33 30 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 12 11 10 C R225 R226 10K 1% 040210K 1% 0402 W49F002UP12B 21,33 PLCC SOCKET 32PIN /NI ADD SOCKET TO (BOM) MOTHERBOARD 7,33 CPU_THERMDC hardware monitor B B A A Title FLASH ROM & H/W MON Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 34 of 39 +3.3V_DUAL R245 10K 1% 0402 +5V_STBY 18 C MCP_PWRGD D D C335 R244 10K 1% 0402 10K 1% 0402 C336 D R241 Q47 2N7002 SOT23 G 10UF 10V 0805 Y5V /NI S 32 DUALS_FET_GATE E 0.1UF 16V Y5V 0402 2N3904 SOT23 B R243 Q48 10K 1% 0402 C334 R242 10UF 10V 0805 Y5V /NI 4.99K 1% 0402 +3.3V_DUAL +5V_STBY R208 10K 1% 0402 MEM_VLD R205 10K 1% 0402 18 C D C Q37 C308 2N7002 SOT23 0.1UF 16V Y5V 0402 /NI S C G +1.8V_SUS Q36 2N3904 SOT23 MEM_VLD_RC E 6.34K 1% 0402 B R207 C307 10UF 10V 0805 Y5V +3.3V_DUAL +3.3V_DUAL R196 15K 0402 R197 10K 1% 0402 R201 10K 1% 0402 D PWRGD_SB HT_VLD 18 POWER SEQUENCING C271 1UF 10V Y5V 15K 0402 PWRGD_Q1 Q31 2N7002 SOT23 G S E B R206 HT_BASE 2N3904 SOT23 4.7K 0402 D C +5V_STBY +1.2V_HT 6.34K 1% 0402 C270 10UF 10V 0805 Y5V /NI S R195 R200 18 Q28 R199 8.2K 0402 Q29 2N7002 SOT23 G B PWRGD_SB +5V_STBY C HT_VLD E +5V_STBY B B Q32 2N3904 SOT23 C272 10UF 10V 0805 Y5V C273 0.1UF 16V Y5V 0402 F0R BOOT UP A A Title POWER SEQUENCING Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 35 of 39 +3.3V_STBY FB11 0805 VDD33_G C204 VDD33_G C309 0.1UF 25V Y5V U10 LAN2_TX+3 LAN2_TX-3 AVDDL C R186 +5V R184 1K 1% 0402 ISOLATEB DVDD 15K 0402 16,20 PCI_INTZ_ VDD33_G 16,20 PCIRST_SLOT3_ 16 PCI_LANCLK 16 PCI_GNT_4 16,20 PCI_REQ_4 16,20 PCI_PME_ DVDD PCI_AD31 PCI_AD30 PCI_AD15 DVDD PCI_C/BE_1 PCI_PAR -SERR R183 0402 /NI R185 0402 /NI VDD33_G -PERR -STOP -DEVSEL -TRDY LAN2_TX-0 LAN2_TX+1 R9 AVDDL R86 DVDD R84 LAN2_TX-1 LAN2_TX+2 LAN2_TX-2 LAN2_TX+3 LAN2_TX-3 0402 /NI V_DAC 0402 /NI 10 SMBDT SMBCK GLED+ TXGLEDRX+ YLEDN/C1 YLED+ 11 LED1-100 13 R81 14 R82 RXGND1 GND2 GND3 GND4 330 1% 0402 VDD33_G R11 0402 LED3-1000 PCI_FRAME_ 16,20 16,20 330 1% 0402 PCI_INTZ_ PCI_GNT_4/PCI_REQ_4 PCI_PAR -SERR SMBDT SMBCK A_D25 PCI_PAR PCI_SERR_ SMB_SDA SMB_SCL PCI_C/BE_[3 0] PCI_AD[31 0] -PERR -STOP -DEVSEL -TRDY PCI_C/BE_0 PCI_C/BE_1 PCI_C/BE_2 PCI_C/BE_3 16,20 16,20 18,20,22,31,37 18,20,22,31,37 16,20 R80 0402 R16 PCI_AD[31 0] 16,20 PCI_PERR_ PCI_STOP_ PCI_DEVSEL_ PCI_TRDY_ PCI_C/BE_0 PCI_C/BE_1 PCI_C/BE_2 PCI_C/BE_3 16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20 CT47 CT37 100UF 16V 5X11 2mm /NI 100UF 16V 5X11 2mm I O A R1 DVDD RTL8110S : R16 > RTL8110(SB&SC) : R16 > RTL8100C : R16 >0.1UF C E E B FB10 0805 C200 C4 0.1UF 25V Y5V + + ACT12 CT34 100UF 16V 6.3X5 2.5mm 100UF 16V 6.3X5 2.5mm FOR 8100S(B) R6 R7 C5 R8 C7 C6 C8 B R12 R13 R14 R15 RTL8100C : C5 C6 >ADD 0.1UF C7 C8->/NI RTL8100C : R12 R13 R14 R15 > /NI RTL8110S : C5 C6 C7 C8 >ADD 0.01UF RTL8100S : R5 R6 R7 R8 > ADD 49.9 C268 C223 C202 C203 C249 C258 C265 RTL8110(SB&SC) : C5 C6 C7 C8 >/NI RTL8110(SB&SC) : R5 R6 R7 R8 R12 R13 R14 R15 > /NI C266 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V + Q46 DVDD_A RTL8100C : remove C4 R5 RTL8100C : remove C5 C243 +3.3V_STBY RTL8110(S&SB&SC)->ADD Q4,R4 (Q3 COLAY Q4) RTL8100C->Q3,Q4,R4->/NI Close to CHIP +5V_STBY + Q6 VDD33_G DVDD PCI_LANCLK Q4 BCP69 SOT-223 G1 G2 G7 G8 RTL8110(S&SB) : keep R9 R11 RTL8100C : REMOVE R9 R10 R11 RTL8110SC : REMOVE R9 R10 PCI_IRDY_ CTRL25 Q42 2N2907 SOT23 /NI 2N2907 SOT23 /NI R90 12 LANUSB_GBMA R10 C146 0.1UF 16V Y5V 0402 Q5 LED0-TX-G N/C2 N/C4 V_DAC GNDP RTL8110(S&SB&SC)->REMOVE Q5,Q6 Q45 TX+ N/C3 R221 0805 R4 Q44 Q43 2SB1202 TO252 /NI RTL8100C->ADD Q5,Q6 VDD33_G B Q3 0.1UF 25V Y5V CTRL18 C210 JUSBLAN1B LAN2_TX+0 D RTL8100C : remove C1,C2 RTL8110S(B,C)&8100C:ADD C3 RTL8110(S,SB,SC) :ADD C1,C2 RTL8100C:remove FB2,R3,keep FB3 RTL8100S:remove FB3,R3,keep FB2 RTL8110(SB,SC):remove FB3, keep R3,FB2 B C5 25MHZ 20PF 30PPM PCI_C/BE_3 C199 C198 22P 50V NPO 0402 22P 50V NPO 0402 0.1UF 25V Y5V 0.1UF 25V Y5V B E B E B C C C222 DVDD PCI_AD20 DVDD PCI_AD19 VDD33_G PCI_AD18 PCI_AD17 PCI_AD16 PCI_C/BE_2 XTAL2 PCI_AD22 PCI_AD21 X1 DVDD PCI_AD25 PCI_AD23 XTAL1 BUF_25M PCI_AD27 PCI_AD26 VDD33_G PCI_AD25 PCI_AD24 15 B C231 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V PCI_AD8 PCI_AD9 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PCI_AD29 PCI_AD28 C238 PCI_AD10 PCI_AD11 PCI_AD12 VDD33_G PCI_AD13 PCI_AD14 DVDD C3 C LAN2_TX+2 LAN2_TX-2 AVDDL DVDD FB9 0805 /NI C227 C R2 FOR RTL8100C ADD FB1 FOR RTL8110(S,SB,SC) REMOVE FB1 AVDDL CT33 100UF 16V 5X11 2mm R198 0402 C235 LAN2_TX+2 0.1UF 16V Y5V 0402 /NI 49.9 1% /NI R153 LAN2_TX-2 49.9 1% /NI R163 C248 LAN2_TX+3 0.1UF 16V Y5V 0402 /NI 49.9 1% /NI R172 LAN2_TX-3 49.9 1% /NI R173 V_12P Q2 Q41 2N2907 SOT23 Q30 2N2907 SOT23 FB3 LAN2_TX+0 R135 LAN2_TX-0 R136 0402 PCI_AD2 DVDD PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 VDD33_G PCI_AD7 PCI_C/BE_0 C267 FB7 FB1 BEAD 60 0805 1A /NI C206 0.1UF 16V Y5V 0402 /NI 49.9 1% /NI AVDDH R152 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AD2 VSSPST GND VDD18 AD3 AD4 AD5 AD6 VDD33 AD7 CBE0B VSSPST AD8 AD9 M66EN AD10 AD11 AD12 VDD33 AD13 AD14 VSSPST GND AD15 VDD18 CBE1B PAR SERRB SMBDATA GND SMBCLK VDD33 PERRB STOPB DEVSELB TRDYB VSSPST CLKRUNB C225 E LAN2_TX+1 LAN2_TX-1 AVDDL CTRL25 MDI0+ MDI0AVDDL VSS MDI1+ MDI1AVDDL CTRL25 VSS AVDDH HSDAC+ HSDACVSS MDI2+ MDI2AVDDL VSS MDI3+ MDI3AVDDL VSSPST GND ISOLATEB VDD18 INTAB VDD33 RSTB CLK GNTB REQB PMEB VDD18 AD31 AD30 GND AD29 AD28 VSSPST C263 V_12P C2 C RTL8100C->R2 /NI RTL8110S->R2 /NI RTL8110(SB&SC)->R2->0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AD27 AD26 VDD33 AD25 AD24 CBE3B VDD18 IDSEL AD23 GND AD22 AD21 VSSPST GND AD20 VDD18 AD19 VDD33 AD18 AD17 AD16 CBE2B FRAMEB GND IRDYB VDD18 LAN2_TX+0 LAN2_TX-0 AVDDL Q1 C226 AVDDH C201 VDD33_G CTRL25 C250 R3 0805 C1 VSS RSET LV2 CTRL18 LG2 HG XTAL2 XTAL1 HV VSSPST GND LED0 VDD18 LED1 LED2 LED3 GND EESK VDD18 EEDI EEDO VDD33 EECS LWAKE AD0 AD1 U11 C264 FB2 FB8 VDD33_G Q1,Q2 FOR RTL8110(S,SB,SC) RTL8100C >Q1,Q2 /NI PCI_AD0 PCI_AD1 2.49K 1% 0402 DVDD GND RSETG DVDD_A CTRL18 GND GND XTAL2 XTAL1 AVDDH GND GND R129 C236 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V /NI 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V C306 0.1UF 16V Y5V 0402 93C46A-2.7V SO8 RTL8110SC QFP128 R1 5.6K->RTL8100C R1 2.49K->RTL8110(S&SB&SC) CS VCC SK DC DI ORG DO GND 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 D R1 GND EESK_G DVDD EEDI/AUX_G EEDO_G VDD33_G EECS_G LED3-1000 LED1-100 LED0-TX-G LAN2_TX+1 R140 LAN2_TX-1 R141 EECS_G EESK_G EEDI/AUX_G EEDO_G 49.9 1% /NI +3.3V_STBY C209 0.1UF 16V Y5V 0402 /NI 49.9 1% /NI 3.6K 0402 E R130 C 49.9 1% /NI R222 210 1% 0402 R188 GND_AUD 24,29,30 + CT30 1000UF 6.3V 8X12 AZ1117H-ADJ SOT-223 R2 A R220 360 1% 0402 A Vout=Vref (1.25V) X ( 1+R2/R1 ) =3.3V Title LAN REL8211B/RTL8201N Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 36 of 39 OVCHIP +1.2V OVCHIP1_R1 C Q1 2N3904 SOT23 Q2 2N3904 SOT23 OVCHIP0_R OVCHIP1_R Q10 2N3904 SOT23 1.278V 1.320V 562 1% 0402 /NI OVLDT 1.275V 1.3V 1.325V 0 33 33 33 33 E B C E B C E B E B OV_DIMM0 +5V_STBY RN1 Q13 2N3904 SOT23 /NI R71 2.94K 1% 0402 OVCHIP0_R1 OVCHIP1_R1 LDT0_R1 LDT1_R1 +1.8VDIMM_FB K8_VID3 K8_VID2 K8_VID1 K8_VID0 VID_OUT3 VID_OUT2 VID_OUT1 VID_OUT0 7,31 7,31 7,31 7,31 33 33 33 33 OV_CHIP1 OV_CHIP0 OV_LDTV0 OV_LDTV1 OVCHIP1_R OVCHIP0_R LDT0_R LDT1_R 18,20,22,31,36 SMB_SCL 18,20,22,31,36 SMB_SDA 24,32 PWRGD_PS SCL SDA EN C U3 1V8 1V25 1V2 1_8V_REF 32 1_25V_REF 38 1_2V_REF 38 UP6261 SOT23-8 /NI VDIMM2 Default 1.95V 1 2.05V 1 2.15V 1 2.2V 1 2.25V 0 C348 C349 C350 1UF 16V 0805 Y5V /NI 1UF 16V 0805 Y5V /NI 1UF 16V 0805 Y5V /NI E B C 10K 8P4R RN5 VDIMM1 Q39 2N3904 SOT23 B E B E 7,31 7,31 7,31 7,31 R272 R271 10K 1% 0402 /NI R270 10K 1% 0402 /NI C11 10K 1% 0402 /NI 0.1UF 16V Y5V 0402 /NI VDIMM0 C C E B C B 7,31 7,31 +5V_STBY +1.8VDIMM_FB VDIMM0_R1 VDIMM0_R VDIMM1_R R204 VID_OUT5 VID_OUT4 32 Q34 2N3904 SOT23 Q38 2N3904 SOT23 10K 8P4R OV_DIMM1 Q33 2N3904 SOT23 RN2 OV_LDTV1 OV_LDTV0 OV_CHIP0 OV_CHIP1 1K 8P4R R202 1.47K 1% 0402 VDIMM1_R1 K8_VID5 K8_VID4 +5V_STBY Q4 2N3904 SOT23 /NI Q12 2N3904 SOT23 /NI OV_DIMM2 OV_LDT1 LDT0_R1 B OV_LDT0 Default 1.26V C C LDT1_RR1 Q3 2N3904 SOT23 /NI D 7,31 7,31 38 R4 174 1% 0402 /NI LDT0_R LDT1_R C327 0.1UF 16V Y5V 0402 0 LDT+1.2V LDT1_R1 C +3.3V E B 1.358V Q11 2N3904 SOT23 LDT0_RR1 R3 OV_CHIP1 EMI E B C E E B C B OVCHIP0_R1 OV_CHIP0 Default 1.240V C OVCHIP1_RR1 D 38 R2 1.1K 1% 0402 VCC 2.26K 1% 0402 GND R1 2 OVCHIP0_RR1 1.1K 1% 0402 +1.8VDIMM_FB 32 2.3V 2.4V 0 2.5V 0 C +5V_STBY 33 33 33 VDIMM0 VDIMM1 VDIMM2 33 33 33 VDIMM2 VDIMM1 VDIMM0 A E Q35 2N3904 SOT23 E B C B VDIMM2_R1 Q40 2N3904 SOT23 VDIMM2_R RN48 10K 8P4R RN49 10K 8P4R +5V_STBY RN47 8 VDIMM2_R VDIMM1_R VDIMM0_R VDIMM0_R1 VDIMM1_R1 VDIMM2_R1 A 1K 8P4R Title OVER VOLTAGE Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 37 of 39 +5V MCP65 CORE + R98 + 2.7 0805 CT42 CT24 1000UF 6.3V 8X12 100UF 16V 5X11 2mm /NI L4 RH TYPE BEAD DA1 K A D RT9202NC/RT9214 uP6103 >ADD >RA1,RA2,REMOVE >RA3,RA4,CA1,DA1 RT9214 >REMOVE >RA1,RA2,ADD >RA3,RA4,CA1,DA1 RA3 R102 30K 1% 0402 C171 VIN_5V RT9202/RT9214NC +1.2V_HT RN68 7 VCC 1K 1% 0402 /NI RA1 COMP R103 C173 20K 0402 /NI 15P 50V NPO 0402 /NI GND R20 1_25V_REF FB C174 4700P 50V X7R 0402 /NI C351 1UF 16V 0805 Y5V /NI +1.2V U8 BOOT UGATE PHASE LGATE R122 R127 C175 0.1UF 25V Y5V L3 + C197 CT25 1UF 16V 0805 Y5V 1000UF 6.3V 8X12 2.7 0805 INDUCTOR 1UH 28A +1.2V RA4 RT9214 SOP8 0805 HT +1.2V @ 10A AMPS MAX R1 R123 R100 + + Q25 2.7 0805 CT23 CT22 110 1% 0402 FDD8780 TO252 1000UF 6.3V 8X12 R101 R119 1000UF 6.3V 8X12 100K 0402 CA1 10K 1% 0402 /NI C196 1000P 50V X7R 0402 RA2 37 Q26 FDD8780 TO252 1UF 16V 0805 Y5V R104 15K 0402 /NI D D5 SS12/5817 SMA OVCHIP 8P4R ノ +1.2V >R5 >0 R16 0402 だ 秨 +1.2V >R5 >0/NI C R99 200 1% 0402 C5 1UF 16V 0805 Y5V /NI R2 R5 +5V R4 +3.3V_STBY R2 D ノ +1.2V >R4 5.1K/NI だ 秨 +1.2V >R4 5.1K R3 ノ +1.2V >R3 >10K,R2 >5.1K/NI R35 R36 だ 秨 +1.2V >R3 >10K/NI,R2 >5.1K 5.1K 0402 /NI 10K 1% 0402 4.7K 0402 G R37 ノ +1.2V >Q1 >7002 2N7002 SOT23 Q16 C14 だ 秨 +1.2V >Q1 >3904 C15 1UF 16V 0805 Y5V /NI R34 1K 1% 0402 G HTVDD_EN 1UF 16V 0805 Y5V /NI R1 C13 R13 Q15 10UF 10V 0805 Y5V /NI C12 2N7002 SOT23 1UF 10V Y5V /NI 1_2V_REF 37 S Q2 ノ +1.2V >Q2 >7002/NI OV_CHIP0 OV_CHIP1 +1.240V +1.278V +1.320V +1.358V 1 1 0 18 S だ 秨 +1.2V >Q2 >7002 CORE VOLTAGE D G S REF_2.5V R14 5.1K 0402 /NI D Q17 C +12V +2.5V 2N7002 SOT23 /NI 37 Vout=0.8(1+R1/R2) for RT9214 ぃ璶匡禬筁 K ohm R1 , R2 R15 COLAY 0402 /NI +12V ノ +1.2V >R1 >1K Q1 +3.3V だ 秨 +1.2V >R1 >10K 0402 /NI ノ +1.2V >RN1 >0 8P4R だ 秨 +1.2V >RN1 >0 8P4R/NI R38 680 0402 /NI C7 0.1UF 16V Y5V 0402 /NI R2 R33 U2C 590 1% 0402 /NI LM324 SO14 + RN1 Q24 FDD8780 TO252 /NI G 11 8P4R 10 B D R1 +1.2V S +1.2V_HT RN32 B +1.2V_HT OVLDT +1.2V_HT +1.23V +1.25V HT +1.2V_HT @ 850MA AMPS MAX R60 10 0402 /NI 37 + CT18 1000UF 6.3V 8X12 OV_HT0 Vout=1.22X(1+R1/R2) A A Title MCP61 CORE Size Document Number Custom Date: Rev 5.0 N560B-A2T Wednesday, June 13, 2007 Sheet 38 of 39 New JPANEL1 JPANEL1 2*11 (BAT1) D 筿 D JPANEL1(9_10) JPANEL1(15_16) HEADER 1X2 HEADER 1X2 JPANEL1(11_14) PLED 3V BATTERY SONY JPANEL1(1_4) JPANEL1(5_6) JPANEL1(7_8) SPK HLED RST PCB (CPU1) C C PCB N560B-A2T VER:5.0 AM2RM-T (PCB) JCMOS1(1_2) JUMPER 2P B (U9) 獁粗 爵床荐 (X3) X'TAL WIRE POLON 303x245 B B NB-C51XE-T (U18) FLASH ROM SPI W25X40 DIP A A Title Size A Date: Document Number N560B-A2T Wednesday, June 13, 2007 Rev 5.0 Sheet 39 of 39 ... 1 .07 5V 01 0X07 0X 001 00 1. 4 50 V 0X 101 00 1. 05 0 V 01 0X08 0X 001 01 1.425V 0X 101 01 1 .02 5V 01 0X09 0X 001 10 1. 400 V 0X 101 10 1 .00 0V 01 0X0A 0X 001 11 1.375V 0X 101 11 0. 975V 0X0 100 0 1. 3 50 V 0X1 100 0 0. 9 50 V 0X0 100 1... 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02... C 65 C66 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02 22P 50 V NPO 04 02