5 PCB STACK UP CH3 BLOCK DIAGRAM LAYER : TOP LAYER : SGND1 LAYER : IN1 LAYER : IN2 LAYER : SVCC LAYER : IN3 LAYER : SGND2 LAYER : BOT 01 PCI DEVICES IRQ ROUTING PCI DEVICE IDSEL# REQ# / GNT# AD25 REQ0# / GNT0# PCI8402 CPU THERMAL SENSOR CPU Merom Interrupts INT A/B/E# 14.318MHz PAG D 479P (uPGA)/35W PAG 3,4 CLK_CPU_BCLK,CLK_CPU_BCLK# CLOCK GEN CLK_MCH_BCLK,CLK_MCH_BCLK# DREFCLK,DREFCLK# CPU CORE SC452 VGACORE(1.025V)MAX1993 PAG 39 NORTH BRIDGE INT-VGACORE MAX8776 DDRII DDRII-SODIMM1 PAG 40 VCCP +1.5V AND GMCH 1.05V(TPS51124) PAG 41 PAG 18,19 PAG 14,15,16,17,18,19,20 LCD CON PAG 25 Crestline DDRII DDRII-SODIMM2 CRT PORT Santa Rosa 533,667 MHz PAG 24 PAG 12,13 C SATA - HDD PAG 33 PAG 42 DDR II SMDDR_VTERM 1.8V/1.8VSUS(TPS51116) PAG 43 PATA- CD-ROM PAG 33 SYSTEM CHARGER(MAX8724) USB2.0 I/O Ports X4 Bluetooth Mini_PCI_E Voltage Rails VCC_CORE ON S3 ON S4 ON S5 Ctl Signal X X X VR_ON VGA1.2 X X MAINON RVCC3 X VCCP SMDDR_VTERM PCI BUS / 33MHz Express Card PAG 27 PCI-E ICH-8M PAG 20,21,22,23 Azalia LPC Mini PCI-E Card ALC262 MAINON X Keyboard Touch Pad PC87541 PAG 29 VCC1.25 VCC1.5 VCC1.8 VCC2.5 VCC3 VCC5 PAGE 37 3VSUS 5VSUS Mini PCI-E Card LAN Express Card Marvell PCIE-LAN M8055 PAG 31 PAG 28 PAG 32 Audio Jack RJ45 PAG 35 PAG 32 Audio Amplifier MAINON MAIND MDC PAG 35 MAINON FAN MAIND PAG 34 BIOS MAIND X X X X X X X X X X X X PAG 37 SPEAKER MODEM RJ 11 A SUSON PAG 35 PAG 35 SUSD SUSD PROJECT : CH3 3VPCU 5VPCU 15VPCU X X X X X X 8734LDO5 Quanta Computer Inc 8734LDO5 Size 5VPCU Document Number R ev 1A BLOCK DIAGRAM Date: B MAINON X X X X X X PAG 30 1.8VSUS Robson WLAN PAG 31 RVCCD X MAINON MAINON Mem ory CardReader SOUTH BRIDGE PAG 34,35 VGACORE IEEE1394 PAG 26 PCI8402 PAG 26~28 USB2.0 Camera Voltage Rails NBSRCCLK, NBSRCCLK# DMI LINK PATA (66/100/133) C PAG 36 SATA0 150MB 0,1,2,3 PAG 45,46 ON S0~S2 HDMI CON PAG 5,6,7,8,9,10,11 SYSTEM POWER MAX8734 A DDR3 X NVDIA NB8P PCI-Express 16X 533,667 MHz PAG 12,13 B ICS9LPRS363AGLFT 64pinsTSSOP PAG DREFSSCLK,DREFSSCLK# PAG 38 hexainf@hotmail.com D Tuesday, February 06, 2007 Sheet 1 of 46 02 14.318MHz VCC3 BG614318F84 CLK_3.3V L16 BLM21PG600SN1D C133 0.1U/10V C662 30P CLK_XIN C160 0.1U/10V C158 0.1U/10V C154 0.1U/10V XTL-5_3X3_2-3_8-1_2H 1 C156 0.1U/10V C157 0.1U/10V 1 C159 0.1U/10V C132 0.1U/10V 10U_0805 C96 2 C895 3.3N/50V CLK_3.3V Y3 14.318MHZ/20P A Add 3.3N CAP for EMI suggestion Nicole 12/11 C664 internal build-in 33ohm damping resisteor VCC3 VDDCPU L17 BLM21PG600SN1D CLK_XIN C97 10U_0805 ICS9PR363DGLF *10K/F CLK_XOUT 57 22 PM_STPCPU# 22 PM_STPPCI# CGCLK_SMB CGDAT_SMB VDDA 22 10U_0805 2 C101 62 63 CPU_STOP# PCI/PCIEX_STOP# 54 55 SCLK SDATA C134 0.1U/10V 14M_ICH 14M_ICH 33_4 2.2K/F_4 10K/F_4 10K/F_4 R462 CLK_BSEL1 CLK_BSEL2 33_4 12 16 61 60 R59 10K 2N7002E VCC3 22 2N7002E CGCLK_SMB 6 C VCC3 R108 *56 R105 *1K CLK_BSEL0 R110 SRC PCI CLK_MCH_BCLK CLK_MCH_BCLK# 4P2R-S-33 CLK_PCIE_MINI_RB 31 CLK_PCIE_MINI_RB# 31 DREFSSCLK DREFSSCLK# RSRC_RB RSRC_RB# RP5 27FIX/LCD_SSCGT/PCIET_L0 27SS/LCD_SSCGC/PCIEC_L0 17 18 R_DREFSSCLK RP45 R_DREFSSCLK# *I@4P2R-S-33 SATACLKT_L SATACLKC_L 26 27 RSRC_SATA RSRC_SATA# RP42 4P2R-S-33 CLK_PCIE_SATA 20 CLK_PCIE_SATA# 20 PCIET_L1 PCIEC_L1 19 20 R_CLK_PCIE_VGARP44 R_CLK_PCIE_VGA# 4P2R-S-33 CLK_PCIE_VGA 14 CLK_PCIE_VGA# 14 PCIET_L2 PCIEC_L2 22 23 CLK_PCIE_NEW RP40 CLK_PCIE_NEW# 4P2R-S-33 CLK_PCIE_NEW_C 28 CLK_PCIE_NEW_C# 28 PCIET_L3 PCIEC_L3 24 25 RS RC_ICH RSRC_ICH# RP43 4P2R-S-33 CLK_PCIE_ICH 21 CLK_PCIE_ICH# 21 FSA/USB_48MHZ FSB/TEST_MODE FSC/REF1/TEST_SEL REF0 B 4P2R-S-33 CLK_PCIE_MINI_WLAN 31 CLK_PCIE_MINI_WLAN# 31 VDDCPU PCIET_L5 PCIEC_L5 RP3 4P2R-S-33 CLK_PCIE_3GPLL CLK_PCIE_3GPLL# VREF VDDA PCIET_L6 PCIEC_L6 39 38 RSRC1_LAN RSRC1_LAN# RP4 VDDA 47 45 4P2R-S-33 CLK_PCIE_LAN 32 CLK_PCIE_LAN# 32 PEREQ1#/PCIET_L7 PEREQ2#/PCIEC_L7 *PEREQ3# *PEREQ4# 41 40 32 33 10 VTTPWR_GD/PD# 14 15 34 PCIET_L9/DOTT_96MHZ PCIEC_L9/DOTC_96MHZL *PWRSAVE# 37 13 29 53 59 46 GND GND GND GND GND GND GND GNDA **REQ_SEL/PCICLK0 R_PCIE_REQ2#R68 R_PCIE_REQ3#R474 R_PCIE_REQ4#R65 475/F_4 475/F_4 475/F_4 R_PCLK_DEBUG R66 64 R_PCI_CLK_8402 PCICLK1 PCICLK2 *SELPCIEX0_LCD#/PCICLK3 SELPCIEX0_LCD# ITP_EN/PCICLK_F4 *SELLCD_27#/PCICLK_F5 R_PCLK_ICH R_PCLK_541 PCIE_REQ2# 31 PCIE_REQ3# 28 PCIE_REQ4# 33_4 PCLK_DEBUG R475 33_4 PCI_CLK_8402 R94 R103 33_4 33_4 PCLK_ICH PCLK_541 PCLK_DEBUG 31 PCI_CLK_8402 26 PCLK_ICH 21 PCLK_541 36 MCH_BSEL0 C * Internal pull up to VDD **Internal pull down to GND R_PCLK_DEBUG R67 10K_4 R96 VCC3 VCC3 10K_4 Update for Robson CLKREQ# nicole 9/20 CPU 4P2R-S-33 RSRC_MCH RSRC_MCH# *I@4P2R-S-33 R_DREFCLK R_DREFCLK# PWRSAVE# R_PCLK_541 FSC FSB FSA BSEL2 BSEL1 BSEL0 CLK_PCIE_MINI_ RP41 CLK_PCIE_MINI_# CPU Clock select R109 RP2 36 35 (96MHz) CPU_BSEL0 CPUT_L1F CPUC_L1F RHCLK_MCH RHCLK_MCH# 30 31 348_6 RP46 CLK_CPU_BCLK CLK_CPU_BCLK# 49 48 PCIET_L4 PCIEC_L4 CK_PWG DREFCLK DREFCLK# 4P2R-S-33 VDDREF VDDPCIEX VDDPCIEX VDDPCIEX VDDCPU 1K/F_4 R58 44 43 Q5 R60 RP1 56 21 28 42 50 CGDAT_SMB VCC3 RHCLK_CPU RHCLK_CPU# VDDPCI VDDPC1 VDD48 R57 10K 52 51 11 CLK_3.3V Q6 13,22,28,31 PCLK_SMB R107 R106 R95 R461 VCC3 22 13,22,28,31 PDAT_SMB CLKUSB_48 CLK_BSEL0 CLKUSB_48 CPUT_L0 CPUC_L0 CPUITPT_L2/PCIET_L8 CPUITPC_L2/PCIEC_L8 VCC3 Add 3.3N CAP for EMI suggestion Nicole 12/11 CPU_BSEL0 X2 VDDA C896 X1 R460 *10K/F C113 0.1U/10V 2 R459 L19 BLM21PG600SN1D 3.3N/50V 58 VDDCPU VCC3 PN change from B version to D version nicole 12/01 U19 VCC3 B A CLK_XOUT 30P REF R_PCLK_ICH Spread USB DOT % R476 PWRSAVE# R71 PCIE_REQ2# R457 SELPCIEX0_LCD# R477 R92 0 266.66 100 33.33 14.318 48 96 0.5 Down 0 133.33 100 33.33 14.318 48 96 0.5 Down 200.00 100 33.33 14.318 48 96 0.5 Down 1 166.66 100 33.33 14.318 48 96 0.5 Down 0 333.33 100 33.33 14.318 48 96 0.5 Down * 1 100.00 100 33.33 14.318 48 96 0.5 Down 400.00 100 33.33 14.318 48 96 0.5 Down 1 200.00 100 33.33 14.318 48 96 0.5 Down D PCLK_DEBUG C115 15P CLKUSB_48 C689 15P PCLK_541 C192 15P PCLK_ICH C193 15P PCI_CLK_8402 C688 15P 10K_4 10K_4 96/100M * R69 15P 10K_4 *10K_4 PCIE_REQ4# C657 *10K_4 10K_4 PCIE_REQ3# 14M_ICH Pin64 LATCH SELECT TABLE Pin8 PCIEXCLK * PEREQ# PCIE_REQ1# PCIE_L0 SRC Pair CPUITP Pair PCIE_L6 PCIE_REQ2# PCIE_L1 PCIE_L8 PCIE_REQ3# PCIE_L2 PCIE_L4 PCIE_REQ4# PCIE_L3 PCIE_L5 Pin5 Pin9 0 Pin14/15 Pin17/18 PCIEX9 27MHz PCIEX9 LCD * x DOT96 PCIEX0 REQ2# used for ROBSON REQ3# used for NEWCARD REQ4# used for GMCH PCIE_L7 D 1.Level Environment-related Substances Should NEVER be Used 2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners PROJECT : CH3 Quanta Computer Inc Size Document Number R ev 1A CLOCK GENERATOR Date: Tuesday, February 06, 2007 Sheet of 46 03 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 PROCHOT# THERMDA THERMDC THERMTRIP# H_HIT# H_HITM# ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET# R63 THERMAL H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# 5 5 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[0 63] T5 T6 T7 T4 T2 Layout Note: Place voltage divider within 0.5" of GTLREF pin VCCP D21 A24 B25 CPU_PROCHOT# H_THERMDA H_THERMDC C7 PM_THRMTRIP# R470 1K/F VCCP 5 H_THERMDA 30 H_THERMDC 30 PM_THRMTRIP# 6,20 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# H_DSTBN#1 H_DSTBP#1 H_DINV#1 R471 2K/F V_CPU_GTLREF AD26 CPU_TEST1 C23 CPU_TEST2 D25 CPU_TEST3 C24 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] H CLK BCLK[0] BCLK[1] A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# 2 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#[0 63] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 T3 75 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 CPU_BSEL0 T152 T151 MISC R64 R472 Merom Ball-out Rev 1a *1K/F *1K/F CPU_TEST1 T13 CPU_TEST2 T1 C672 *0.1U/10V CPU_TEST4 R466 CPU_TEST6 *0 CPU_TEST3 CPU_TEST5 For the purpose of testability, route these signals through a ground referenced Z0 = 55ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection R61 *54.9/F_4 FSB BCLK ITP_TMS R23 39/F_4 533 133 0 ITP_TDI R28 150/F_4 667 166 1 54.9/F_4 800 200 ITP_TRST# R24 BSEL0 BSEL1 R25 54.9/F R26 BSEL2 27/F 680/F_4 Resistor Value TDI 150 ohm +/- 5% VTT Within 2.0" of the ITP TMS 39 ohm +/- 1% VTT Within 2.0" of the ITP TRST# 500-680ohm +/- 5% GND Within 2.0" of the ITP TCK 27 ohm +/- 1% GND Within 2.0" of the ITP TDO 150 ohm +/- 5% VTT Within 2.0" of the ITP R27 27.4/F R469 54.9/F R468 27.4/F Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal ITP disable guidelines Signal C COMP0 COMP1 COMP2 COMP3 ITP_DBRESET# R22 Note: H_DPRTSTP need to daisy chain from ICH8 to IMVP6 to CPU H_DPRSTP# 6,20,37 H_DPSLP# 20 H_DPWR# H_PWRGD 20 H_CPUSLP# PM_PSI# 37 VCCP ITP_TCK B H_DSTBN#3 H_DSTBP#3 H_DINV#3 Place C close to the CPU_TEST4 pin Make sure CPU_TEST4 routing is reference to GND and away from other noisy signal ITP_BPM#5 H_D#[0 63] Merom Ball-out Rev 1a C ITP PU H_D#[0 63] A H_D#[0 63] 5 G6 E4 H_LOCK# H_RESET# HIT# HITM# VCCP H_INIT# 20 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 STPCLK# LINT0 LINT1 SMI# C1 F3 F4 G3 G2 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 D5 C6 B4 A3 H_STPCLK# H_INTR H_NMI H_SMI# RESET# RS[0]# RS[1]# RS[2]# TRDY# 56 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# 20 20 20 20 LOCK# H4 R62 H_IERR# D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# A20M# FERR# IGNNE# D20 B3 ICH A6 A5 C4 F1 IERR# INIT# E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 H_ADSTB#1 20 H_A20M# 20 H_FERR# 20 H_IGNNE# H_DEFER# H_DRDY# H_DBSY# H_BR0# H_D#[0 63] U17B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 Connect To Resistor Placement D D PROJECT : CH3 Quanta Computer Inc Size Document Number R ev 1A CPU Date: Tuesday, February 06, 2007 Sheet of 46 hexainf@hotmail.com A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# H5 F21 E1 H_D#[0 63] H_D#[0 63] DATA GRP B Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 ADDR GROUP H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# H_ADS# H_BNR# H_BPRI# H_A#[17 35] H_A#[17 35] K3 H2 K2 J3 L1 H1 E2 G5 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 BR0# CONTROL H_REQ#[0 4] DEFER# DRDY# DBSY# XDP/ITP SIGNALS H_ADSTB#0 H_REQ#[0 4] ADS# BNR# BPRI# DATA GRP 5 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# ADDR GROUP A J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 DATA GRP U17A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 DATA GRP H_A#[3 16] H_A#[3 16] RESERVED VCC_CORE VCC_CORE VCC_CORE 1 C650 10U/6.3V C65 10U/6.3V C74 10U/6.3V C58 10U/6.3V C80 10U/6.3V 2 VCC_CORE inside cavity, north side, secondary layer 1 C638 10U/6.3V C646 10U/6.3V C648 10U/6.3V C640 10U/6.3V C643 10U/6.3V 2 VCC_CORE VCC_CORE 1 C73 10U/6.3V C637 10U/6.3V C64 10U/6.3V C645 10U/6.3V C651 10U/6.3V 2 B inside cavity, south side, secondary layer C639 10U/6.3V C642 10U/6.3V C649 10U/6.3V C57 10U/6.3V C95 10U/6.3V C91 10U/6.3V 2 VCC_CORE inside cavity, north side, primary layer C90 10U/6.3V C94 10U/6.3V C56 10U/6.3V 1 C78 10U/6.3V C72 10U/6.3V 1 C66 10U/6.3V 2 C VCC_CORE AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 VCCSENSE AF7 VCCSENSE VCCSENSE 37 VSSSENSE AE7 VSSSENSE VSSSENSE 37 VCCP U17D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 ICCP: 1before vccore stable peak current is 4.5A 2.after vccore stable continue current is 2.5A + C75 330U/2.5V VCC1.5 ICCA 130mA C79 10U/6.3V VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] 37 37 37 37 37 37 37 C169 01U/25V C176 10U/6.3V Layout Note: Place C105 near PIN B26 Merom Ball-out Rev 1a inside cavity, south side, primary layer Update to 10u *32pcs OK VCC_CORE R43 100/F P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] A B C Merom Ball-out Rev 1a C100 0.1U/10V VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VCCSENSE VSSSENSE C55 0.1U/10V C99 0.1U/10V C54 0.1U/10V C98 0.1U/10V C53 0.1U/10V 2 1 VCCP 04 ICCODE: for Merom processors recommended design target is 44A C89 10U/6.3V VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] 1 C93 10U/6.3V C636 10U/6.3V 1 C635 10U/6.3V A 2 U17C A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 2 Layout out: Place these inside socket cavity on North side secondary R37 100/F D D Route VCCSENSE and VSSSENSE traces at 27.4ohms and length matched to within 25 mil Place PU and PD within inch of CPU PROJECT : CH3 Quanta Computer Inc Size Document Number R ev 1A CPU Date: Tuesday, February 06, 2007 Sheet of 46 05 H_A#[3 35] U25A H_D#[0 63] H_D#[0 63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 A VCCP R118 221/F H_SWING C191 0.1U/10V R114 100/F B VCCP 1 impedance 55 ohm R111 54.9/F 2 R116 54.9/F H_SCOMP H_SCOMP# H_RCOMP R113 24.9/F C Layout Note: H_RCOMP trace should be 10-mil wide with 15-mil spacing VCCP 3 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP B3 C2 H_SWING H_RCOMP H_SCOMP H_SCOMP# W1 W2 H_SCOMP H_SCOMP# B6 E5 H_CPURST# H_CPUSLP# H_RESET# H_CPUSLP# R134 1K/F E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B9 A9 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 K5 L2 AD13 AE13 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 M7 K3 AD2 AH11 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 3 3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L7 K2 AC2 AJ10 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 3 3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 M14 E13 A11 H13 B12 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 3 3 H_RS#_0 H_RS#_1 H_RS#_2 E12 D7 D8 H_RS#0 H_RS#1 H_RS#2 3 H_A#[3 35] A B 3 3 C H_AVREF H_DVREF CRESTLINE_1p0 C209 0.1U/10V 2 R127 2K/F 1 H_REF HOST Layout Note:55ohm Place the 0.1 uF decoupling capacitor within 100 mils from GMCH pins D PROJECT : CH3 Quanta Computer Inc Size Document Number R ev 1A NB Date: Tuesday, February 06, 2007 Sheet of 46 hexainf@hotmail.com D 13 SA_MA14 13 SB_MA14 T183 T75 T50 T40 11 MCH_CFG_12 11 MCH_CFG_13 T28 T31 11 MCH_CFG_16 T44 T64 11 MCH_CFG_19 11 MCH_CFG_20 R264 R255 R247 R177 R178 R240 0 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 BG20 BK16 BG16 BE13 M_A_CS#0 M_A_CS#1 M_B_CS#0 M_B_CS#1 12,13 12,13 12,13 12,13 16 16 16 LA_DATAN0 LA_DATAN1 LA_DATAN2 G51 E51 F49 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 BH18 BJ15 BJ14 BE16 M_A_ODT0 M_A_ODT1 M_B_ODT0 M_B_ODT1 12,13 12,13 12,13 12,13 16 16 16 LA_DATAP0 LA_DATAP1 LA_DATAP2 G50 E50 F48 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 SM_RCOMP SM_RCOMP# BL15 BK14 SMRCOMPP SMRCOMPN SM_RCOMP_VOH SM_RCOMP_VOL BK31 BL31 SM_RCOMP_VOH SM_RCOMP_VOL G44 B47 B45 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 SM_VREF_0 SM_VREF_1 AR49 AW4 SMDDR_VREF_MCH R276 *10K/F R269 *10K/F E44 A47 A45 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 E27 G27 K27 TVA_DAC TVB_DAC TVC_DAC F27 J27 L27 TVA_RTN TVB_RTN TVC_RTN MUXING 12,13 12,13 12,13 12,13 DDR DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# B42 C42 H48 H47 PEG_CLK PEG_CLK# K44 K45 VCC3 16,17,25 EDIDCLK 16,17,25 EDIDDATA 17,25 DIGON For Calero : 1.5K For Cresstline:2.4K I&E Dis/Enable setting 16 16 C375 0.1U/10V C376 0.1U/10V R270 1K/F_4 1K/F_4 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 PM_BMBUSY#_R ICH_DPRSTP#_R G41 L39 L36 PM_EXTTS#1_R J36 AW49 100 PLTRST_MCH# AV20 *0 PM_THRMTRIP#_GMCH N20 PM_DPRSLPVR_GMCH G36 GMCH pwrok is 3.3v tolerant SMDDR_VREF DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 AM47 AJ39 AN41 AN45 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AJ46 DMI_RXN0 AJ41 DMI_RXN1 AM40 DMI_RXN2 AM44 DMI_RXN3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AJ47 DMI_RXP0 AJ42 DMI_RXP1 AM39 DMI_RXP2 AM43 DMI_RXP3 PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 R237 R267 VCC3 DMI_RXN[3:0] 21 DMI_RXP[3:0] 21 16,24 CRT_B 16,24 CRT_G 16,24 CRT_R CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF GVR_VID0 GVR_VID1 GVR_VID2 GVR_VID3 DFGT_VR_EN H35 K36 G39 G40 TEST_1 TEST_2 A37 R32 39 39 39 39 CL_CLK0 22 CL_DATA0 22 ECPWROK 17,22,36 CL_RST#0 22 R76 *I@0 NB_R R265 R225 R86 *I@0 *I@0 *I@30 R90 *I@30 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC HSYNC/VSYNC serial R place close to NB J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 PEG_RXN0 14 PEG_RXN1 14 PEG_RXN2 14 PEG_RXN3 14 PEG_RXN4 14 PEG_RXN5 14 PEG_RXN6 14 PEG_RXN7 14 PEG_RXN8 14 PEG_RXN9 14 PEG_RXN10 14 PEG_RXN11 14 PEG_RXN12 14 PEG_RXN13 14 PEG_RXN14 14 PEG_RXN15 14 N45 C_PEG_TXN0 C714 U39 C_PEG_TXN1 C718 U47 C_PEG_TXN2 C721 N51 C_PEG_TXN3 C725 R50 C_PEG_TXN4 C728 T42 C_PEG_TXN5 C730 Y43 C_PEG_TXN6 C734 W46 C_PEG_TXN7 C737 W38 C_PEG_TXN8 C739 AD39 C_PEG_TXN9 C747 AC46 C_PEG_TXN10C750 AC49 C_PEG_TXN11C756 AC42 C_PEG_TXN12C761 AH39 C_PEG_TXN13C763 AE49 C_PEG_TXN14C767 AH44 C_PEG_TXN15C769 E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 M45 C_PEG_TXP0 C710 T38 C_PEG_TXP1 C715 T46 C_PEG_TXP2 C720 N50 C_PEG_TXP3 C724 R51 C_PEG_TXP4 C727 U43 C_PEG_TXP5 C729 W42 C_PEG_TXP6 C731 Y47 C_PEG_TXP7 C735 Y39 C_PEG_TXP8 C738 AC38 C_PEG_TXP9 C741 AD47 C_PEG_TXP10C749 AC50 C_PEG_TXP11C751 AD43 C_PEG_TXP12C758 AG39 C_PEG_TXP13C762 AE50 C_PEG_TXP14C766 AH43 C_PEG_TXP15C768 E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V E@.1U/10V PEG_TXN_C0 14 PEG_TXN_C1 14 PEG_TXN_C2 14 PEG_TXN_C3 14 PEG_TXN_C4 14 PEG_TXN_C5 14 PEG_TXN_C6 14 PEG_TXN_C7 14 PEG_TXN_C8 14 PEG_TXN_C9 14 PEG_TXN_C10 14 PEG_TXN_C11 14 PEG_TXN_C12 14 PEG_TXN_C13 14 PEG_TXN_C14 14 PEG_TXN_C15 14 In Crestline EDS Rev.1.0, Render Standby Voltage is not finalized yet(TBD), 1.05V for Graphic Voltage range(VCC_AXG) is between 0.9975V(min.) and 1.1025V(max.) Vgfx max at 1.1025V @ 8A (estimated) SDVO/PCIE/LVDS not implement, 16 lanes NC C DREFSSCLK R274 DREFSSCLK# R272 If no use DREFCLK PD and DREFCLK# PU E@0 E@0 VCCP only reserve AT3/5 not support IAMT, but design guide suggest to connection these pin ,do not NC R268 R266 E@0 E@0 VCCP R259 R231 R514 R511 R257 R239 R242 R260 If no use DREFCLK PD and DREFCLK# PU R246 R220 R200 R202 R223 R214 1 For E@ Connect to GND CRT R/G/B TV A/B/C HSYNC/VSYNC CLKREQ# ( MCH drives CLK_REQ# to control the PCI-E diff clk input itself ) 1.8VSUS E@0 E@0 E@0 E@0 E@0 E@0 E@0 E@0 DDC CLK DDCDATA L_DDC_CLK L_DDC_DATA L_CTRL_CLK L_CTRL_DATA TV_DCONSEL_0 TV_DCONSEL_1 Per desigen guide V1.1 p195 nicole 10/20 E@0/I@150 NB_B E@0/I@150 NB_G E@0/I@150 NB_R E@0 HSYN C11 E@0 VSYNC11 1 VCC1.25 For I@ Connect to 150ohm CRT R/G/B TV A/B/C Connect to 30ohm HSYNC/VSYNC R519 1K/F PROJECT : CH3 R146 20/F Quanta Computer Inc 2 R226 1K/F R516 392/F C315 2.2U/10V C745 0.1U/10V 2 SMRCOMPP SMRCOMPN MCH_CLVREF D R152 20/F 2 B PEG_TXP_C0 14 PEG_TXP_C1 14 PEG_TXP_C2 14 PEG_TXP_C3 14 PEG_TXP_C4 14 PEG_TXP_C5 14 PEG_TXP_C6 14 PEG_TXP_C7 14 PEG_TXP_C8 14 PEG_TXP_C9 14 PEG_TXP_C10 14 PEG_TXP_C11 14 PEG_TXP_C12 14 PEG_TXP_C13 14 PEG_TXP_C14 14 PEG_TXP_C15 14 Size Document Number Date: Tuesday, February 06, 2007 Rev 1A NB A PEG_RXP0 14 PEG_RXP1 14 PEG_RXP2 14 PEG_RXP3 14 PEG_RXP4 14 PEG_RXP5 14 PEG_RXP6 14 PEG_RXP7 14 PEG_RXP8 14 PEG_RXP9 14 PEG_RXP10 14 PEG_RXP11 14 PEG_RXP12 14 PEG_RXP13 14 PEG_RXP14 14 PEG_RXP15 14 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PCIE_REQ4# MCH_ICH_SYNC# 22 1 DDC CLK K33 DDCDATA G35 HSYN C11 F33 CRTIREF C32 VSYNC11 E33 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 I&E Dis/Enable setting T215 R212 3.01K/F C301 01U/25V H32 G32 K29 J29 F29 E29 06 MCH_CLVREF 1 C268 2.2U/10V C274 01U/25V NB_G 16,24 VSYNC_COM T178 update per design guide v1.1 9/29 AM49 AK50 AT43 AN49 AM50 SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# SM_RCOMP_VOL NB_B *I@0 DREFCLK DREFCLK# SM_RCOMP_VOH PM_EXTTS#0 PM_EXTTS#1 *I@0 R80 R277 24.9/F N43 VCC_PEG_R1 M43