8 CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV SCHEMATIC,MACBOOK PRO 17" ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE ? ? ? ? DATE ? 9/26/2006 D D (.CSA) DATE PAGE TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM CONTENTS SYNC 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 (.CSA) PAGE TABLE_TABLEOFCONTENTS_HEAD N/A Table of Contents N/A System Block Diagram (MASTER) Power Block Diagram (MASTER) BOM CONFIGURATION (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) Functional / ICT Test (MASTER) Signal Aliases (MASTER) CPU OF 2-FSB M59_MLB CPU OF 2-PWR/GND M59_MLB CPU Decoupling & VID 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM M59_MLB 10 CPU MISC1-TEMP SENSOR M59_MLB 11 CPU ITP700FLEX DEBUG (MASTER) 12 NB CPU Interface M59_MLB 13 NB PEG / Video Interfaces M59_MLB 14 NB Misc Interfaces M59_MLB NB DDR2 Interfaces M59_MLB 15 16 NB Power 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 08/08/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM M59_MLB 17 NB Power M59_MLB 18 NB Grounds M59_MLB 19 NB (GM) Decoupling M57_MLB_MG 20 NB Config Straps M59_MLB 21 SB: OF M59_MLB SB: of M59_MLB 22 23 SB: OF 08/08/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM M57_MLB_MG 24 SB: OF M59_MLB 25 SB Decoupling M59_MLB 26 SB Misc (MASTER) 27 M57 SMBUS CONNECTIONS (MASTER) 28 DDR2 SO-DIMM Connector A M59_MLB DDR2 SO-DIMM Connector B M59_MLB 29 30 Memory Active Termination (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) 31 Memory Vtt Supply M59_MLB 32 DDR2 VRef M59_MLB 33 CLOCKS M59_MLB 34 Clock Termination M59_MLB 37 Mobile Clocking M59_MLB PATA Connector (MASTER) 38 39 FireWire Link (TSB83AA22) M59_MLB 40 FireWire PHY (TSB83AA22) M59_MLB 41 ETHERNET CONTROLLER M59_MLB 42 Ethernet Connector M59_MLB Yukon Power Control M59_MLB 43 44 FW PHY Power Supply 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM M59_MLB 45 FireWire Port Power DATE (MASTER) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 CONTENTS SYNC 46 06/27/2006 FireWire Ports M59_MLB Camera Connector M59_MLB Internal USB Hub (MASTER) External USB Connector M59_MLB Left I/O Board Connector (MASTER) Current & Thermal Sensors (MASTER) PCI-E Connections (MASTER) SMC M59_MLB SMC Support M59_MLB LPC+ Debug Connector (MASTER) Thermal Sensors M59_MLB Current & Voltage Sensing M59_MLB SPI BOOTROM M59_MLB ALS Support (MASTER) Fan Connectors (MASTER) Sudden Motion Sensor (SMS) M59_MLB TPM M59_MLB IMVP6 CPU VCore Regulator M59_MLB 5V / 1.5V Power Supply M59_MLB 2.5V & 1.2V Regulators M59_MLB 1.8V Supply (MASTER) 3.3V / 1.05V Power Supplies (MASTER) 3.3V G3Hot Supply & Power Control M59_MLB Power Aliases (MASTER) DC-In & Battery Connectors (MASTER) PBus Supply & Batt Charger M59_LIO ATI M56 PCI-E (MASTER) GPU (M56) Core Supplies (MASTER) ATI M56 Core Power (MASTER) ATI M56 Frame Buffer I/F (MASTER) GPU Straps M57_MLB_MG GDDR3 Frame Buffer A (MASTER) GDDR3 Frame Buffer B (MASTER) ATI M56 GPIO/DVO/Misc (MASTER) 49 09/15/2006 50 (MASTER) 52 09/15/2006 55 (MASTER) 56 (MASTER) 57 (MASTER) 58 09/15/2006 59 09/15/2006 60 (MASTER) 61 09/15/2006 62 09/15/2006 63 09/15/2006 64 (MASTER) 65 (MASTER) 66 C 09/15/2006 67 09/15/2006 75 09/15/2006 76 09/15/2006 77 09/15/2006 78 (MASTER) 79 (MASTER) 80 09/15/2006 81 (MASTER) 82 (MASTER) 83 09/15/2006 84 (MASTER) 85 (MASTER) 86 (MASTER) 87 (MASTER) 88 08/08/2006 89 (MASTER) 90 (MASTER) 91 B (MASTER) 93 (MASTER) ATI M56 Video Interfaces (MASTER) Internal Display Connectors M57_MLB_MG External Display Connector M59_MLB M57 SPECIFIC CONNECTORS (MASTER) LVDS Interface Pull-downs M59_MLB Revision History (MASTER) Napa Platform Constraints (MASTER) More System Constraints (MASTER) M9 Spacing & Physical Constraints (MASTER) M57 NET PROPERTIES (MASTER) 94 08/08/2006 97 09/15/2006 98 (MASTER) 99 09/15/2006 100 (MASTER) 101 (MASTER) 102 (MASTER) 103 (MASTER) 104 (MASTER) TABLE_TABLEOFCONTENTS_ITEM ALIASES RESOLVED DIMENSIONS ARE IN MILLIMETERS A Apple Computer Inc METRIC XX X.XX DRAFTER Schematic / PCB #’s PART NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING QTY ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES DESCRIPTION REFERENCE DES CRITICAL 051-7164 SCHEM,TRUCKEE,M57 SCH CRITICAL 820-2059 PCBF,TRUCKEE,M57 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING SCHEMATIC,MACBOOK PRO 17 NONE DRAWING SIZE TITLE=TRUCKEE ABBREV=DRAWING THIRD ANGLE PROJECTION LAST_MODIFIED=Tue Sep 26 13:17:56 2006 MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7164 06004 SHT 1 OF 87 GDDR3 Core Duo (Merom) CPU Frame Buffer THERMAL 128MB/256MB SENSOR ITP700FLEX CPU Debug Connector 479 BGA INVERTER P.75-76 PWM P.10 P.11 CONNECTOR D P.7-9 D P.79 J2800 LCD Panel Dual-Channel LVDS FSB ATI M56P DDR2 SO-DIMM A Expansion/Lower Connector P.79,82 GPU S-Video/Composite DVI-I/DL Connector w/TV-Out Support PCIe x16 CH.A 945GM NB Dual-Channel TMDS P.80 P.70-74,77-78 LVDS Graphics MUX P.28 J2900 DDR2 SO-DIMM B CH.B DDR2 VTT Factory/Upper Connector P.78 & REGULATOR 1466UFCBGA P.29 RJ45 (Ethernet) ENET Yukon Gig-E Connector Yukon Power Controller P.41 BUFFER P.39 P.40 P.32 DMI x4 1394a/b (FireWire) FW TSB83AA22 FireWire Connectors C P.44 Controller P.37-38 Port Power P.43 Right USB 2.0 P.30-31 DDR2 VREF P.12-20 C PCIe x1 PCI PHY Power ICH7-M P.42 PCIe x1 USB Connector P.47 PCIe x1 USB 2.0 Hub/Sleep LED IR USB Left I/O & Connector SB P.46,81 HDD/BT Connectors SATA USB USB x2 Audio Board Connector USB P.81 Azalia (HD-Audio) P.48 Camera Connector 609 BGA USB P.45 P.21-26 B B Geyser KB / USB SMBus TP Connector Batt Chgr/ PBUS Supply P.45 ODD Connector PATA P.69 66MHZ 16BITS LPC 33MHZ P.36 BootROM Power SPI TPM P.56 CK410 Clock Controller SB SMBus H8S/2116 P.27 P.33-34 P.61-68,71 Connector P 60 Temperature P.53 System Block Diagram RT ALS SMC SMBus Sensors A Supplies LPC Debug SMC SMBus x5 P.57 SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY P.27 P.48,54 SMS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING P.59 Battery SMBus Fan Connector PWM/Tach Connectors II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Analog P.58 P.68 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE P.51-52 SIZE Sensors P.55 APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7164 06004 OF 87 A U8000 ENABLE J8290 Q7610 3.425 MLB DC in PPDCIN_G3H PP5V_S3 PP3V42_G3H G3Hot Connector 18.5V - 9V 5.0V 3.425V (LT3470) Q3820 SMC_PM_G2_ENABLE D D PP5V_S0_IDE_ODD ENABLE 1.5V 5V U8300 Q8250 PM_SLP_S3_L PM_SLP_S4_LS5V 5.0V Q7615 U7600 ENABLES PP18V5_G3H_CHGR 5.0V PBUS PPBUS_G3H 5V/1.5V SUPPLY 12.6 - 9V PP5V_S5 PP5V_S0 5.0V 5.0V ODD_PWR_EN_L (SB GPIO14) S5S0 (ISL6255AHRZ) Q4300 (LTC3728) ACIN_ENABLE_DIV_L J8290 PPBUS_G3H LIO Power Connector 12.6V - 9V PP1V5_S0 1.5V PP3V3_S3AC PM_SLP_S3_LS5V PGOOD 3.3V Q7945 NC SMC_PM_G2_ENABLE PP3V3_S3 PM_SLP_S3BATT 3.3V U7900 IMVP_VR_ON Q7720 ENABLE IMVP_PWRGD_IN C 2.5V PM_SLP_S4_LS5V PP3V3_S5 ENABLES C PP2V5_S0 3.3V U7530 S5 3.3V CPU VCore S0 (ISL9504) PM_SLP_S3BATT U7700 ENABLE (ISL6269B) PPVCORE_S0_CPU PGOOD PM_SLP_S3_LS5V_L Q7721 1.25V - 0.8V RSMRST_PWRGD "IMVP6" 2.5V PM_SLP_S3_L PGOOD S3 PP2V5_D3C 2.5V 2.5V (TPS62510) U7950 VR_PWRGOOD_DELAY PP2V5_S3 ENABLE J9450 PGOOD 1.05V Inverter P1V2R2V5DC3_EN_LS5V NC PM_SLP_S3BATT U7750 PP1V05_S0 S0 Connector 1.05V (ISL6269B) PM_SLP_S4_L B ENABLE 1.2V ENABLE IMVP_PWRGD_IN/ALL_SYS_PWRGD U8500 1.8V PP1V2_D3C 1.2V 1.2V (LTC3412) PP1V8_S3 S3 PP1V2_S3 S3 =GPUVCORE_EN_L 1.8V PGOOD ENABLE (TPS5117RGY) B Q7770 PGOOD U7800 P1V2R2V5D3C_EN_LS5V NC GPU VCore PGOOD PPVCORE_S0_GPU Q7947 S0 NC 1.1V - 0.95V PP3V3_S0 (ISL6269B) 3.3V PGOOD PM_SLP_S3_L NC Power Block Diagram U3100 PM_SLP_S3_LS5V ENABLE A SYNC_MASTER=(MASTER) Q7845 0.9V (Vtt) PP0V9_S0 PP1V8_D3C 0.9V 1.8V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING PPBUS_S5_FWPORT S0 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT (TPS51100) 12.6V - 9V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC PM_SLP_S3_LS5V_L SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY Q4565 SHT NONE REV 051-7164 SCALE FWPWR_EN DRAWING NUMBER D 06004 OF 87 A PART NUMBER QTY 338S0270 338S0274 341S1931 DESCRIPTION REFERENCE DES CRITICAL BOM OPTION IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO U4101 CRITICAL IC,SMC,HS8/2116 U5800 CRITICAL SMC_BLANK IC,PRGRM,SMC(NEW),M57 U5800 CRITICAL SMC_PRGRM 341S1797 IC,EEPROM,SERIAL IIC,8KBIT,SO8 U4102 CRITICAL TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-7814 TRUCKEE,2.33GHZ,B2,256VRAM,SAM,M57 VRAM_256SAM,M57_COMMON,CPU_2_33GHZ_B2,EEE_WJK 335S0384 IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8 U6301 CRITICAL BOOTROM_BLANK 341S1924 IC, BOOTROM, DEVELOPMENT, UNLOCKED ,M57 U6301 CRITICAL BOOTROM_DEVEL 341S1925 IC, BOOTROM, FINAL, LOCKED, M57 U6301 CRITICAL BOOTROM_FINAL 353S1461 IC,ISL9504,SYNC REG CTL,QFN 48 U7530 CRITICAL 359S0109 IC,LOW POWER CLOCK SYNTHESIZER,68PIN U3301 CRITICAL TABLE_BOMGROUP_ITEM D PART NUMBER 341S1789 PART NUMBER TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS QTY QTY DESCRIPTION REFERENCE DES IC, TPM, 28-PIN TSSOP U6700 CRITICAL BOM OPTION CRITICAL DESCRIPTION REFERENCE DES 337S3393 IC,MDC,B2,PRQ,2.33GHZ,34W,667M,4M,479 BGA U0700 CRITICAL 338S0269 IC,945GM,NORTHBRIDGE U1200 CRITICAL 343S0385 IC,ICH7M,BGA U2100 CRITICAL D TPM CRITICAL BOM OPTION CPU_2_33GHZ_B2 TABLE_BOMGROUP_ITEM VRAM_128SAM VRAM_128_SAMSUNG VRAM_256SAM GPU_MEM_256M,VRAM_256_SAMSUNG BOM GROUP BOM OPTIONS M57_COMMON ALTERNATE,COMMON,M57_COMMON1,M57_COMMON2,M57_COMMON3,M57_COMMON4,M57_DEBUG M57_COMMON1 ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3,ISL6255A,NO_3G M57_COMMON2 KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C C TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM M57_COMMON3 LVDS_PD,FW_PORT_FAULT_PU M57_COMMON4 BOOTROM_DEVEL,SMC_PRGRM M57_DEBUG ITP,LPCPLUS M57_TPM TPM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Extra TPM options: SMC_TPM_GPIO2 SMC_TPM_GPIO1 SMC_TPM_PP BAR CODE LABELS / EEE #’S PART NUMBER 826-4393 QTY DESCRIPTION REFERENCE DES CRITICAL LBL,P/N LABEL,PCB,28MM X MM [EEE:WJK] CRITICAL BOM OPTION EEE_WJK B B MODULE PARTS PART NUMBER QTY 338S0368 DESCRIPTION REFERENCE DES CRITICAL IC,ATI,M56P,GRPHSCTRL,880BGA,LF U8400 CRITICAL BOM OPTION 333S0354 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_SAMSUNG 333S0350 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_SAMSUNG 333S0358 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_HYNIX 333S0351 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_HYNIX 333S0376 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_INFINEON 333S0377 IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_INFINEON ALTERNATE PARTS TABLE_ALT_HEAD IS PART NUMBER ALTERNATE FOR PART NUMBER 376S0448 128S0083 BOM OPTION REF DES COMMENTS: 376S0445 ALL Si7806ADN for FDM6296 128S0073 C2516 1.86 MAX ALT TO 1.9 MAX 128S0093 128S0092 ALL KEMET IS ALT TO SANYO 353S1465 353S1461 ALL Screened ISL6262 for ISL9504 152S0287 152S0435 ALL Alternates for Coilcraft MSS5131 TABLE_ALT_ITEM BOM CONFIGURATION TABLE_ALT_ITEM TABLE_ALT_ITEM A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) TABLE_ALT_ITEM NOTICE OF PROPRIETARY PROPERTY TABLE_ALT_ITEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7164 06004 OF 87 A Power Supply NO_TESTs NO_TEST Functional Test Points EXPOSED_VIA TRUE IMVP6_RBIAS TRUE TRUE P5VS5_RUNSS P1V5S0_RUNSS TRUE TRUE P2V5S3_MODE P2V5S3_SHDNRT 61C7 Power Nets 62C4 66C6 I179 D TRUE TRUE P1V2S3_RT P1V2S3_RUNSS TRUE TRUE P1V8S3_COMP P1V8S3_FSET TRUE TRUE P3V3S5_COMP P3V3S5_FSET TRUE TRUE P1V05S0_COMP P1V05S0_FSET TRUE P3V42G3H_FB I178 I182 I183 63B6 I184 41C4 63B7 I185 I186 I267 I187 65C6 I188 65D6 I189 65A7 I190 65B7 I191 I192 66C3 I193 TRUE TRUE GPUVCORE_COMP GPUVCORE_FSET TRUE GPUBBP_ADJ Fan Connectors 71C7 I194 71C7 I195 I197 FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST PP0V9_S0 PP1V05_S0 PP1V2_D3C PP1V2_S3 PP1V5_S0 PP1V5_S0_NB PP1V8_S3 PP1V8_D3C PP2V5_S0 PP2V5_D3C PP3V3_S0 PP3V3_S3 PP3V3_S5 PP5V_S0 PP5V_S3 PP5V_S5 PPBUS_G3H GND 5A4 39A8 39D7 63B3 67D6 67D8 63C1 67A6 67A8 77A8 77C6 78C8 82D7 I199 I201 I202 I203 I204 C I205 I206 I207 I208 I209 I210 I211 I212 I213 I215 I214 I216 I217 I219 I218 I221 I220 I222 I223 I224 I225 TRUE TRUE FAN_LT_PWM FAN_LT_TACH B TRUE TRUE TRUE 65D8 66C5 67C3 67D3 67D5 79D5 24C3 25B6 25C8 25D2 26C5 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 56D4 63D8 65C8 65D1 65D2 5B2 45C3 52B8 62A2 67B1 67B3 81C4 81C6 66B8 66D8 67B1 67C1 67C3 25C8 47C7 52B5 62A4 62B2 62B6 62C8 64C8 65B7 65D6 71D7 5A1 41C6 42B8 43D8 55D3 61D4 61D7 62D7 64A6 64D7 65B7 65D6 67C1 67C3 68D5 69C1 71D7 79B7 IMVP_VR_ON IMVP_DPRSLPVR PM_SLP_S3_L PM_SLP_S3BATT PM_SLP_S4_L PM_SLP_S5_L P1V5P1V05S0_PGOOD CPU_DPRSTP_L IMVP6_VID FSB_CLK_CPU_N FSB_CLK_CPU_P PLT_RST_L PLT_RST_L PEG_RESET_L SMC_LRESET_L TPM_LRESET_L CPU_STPCLK_L FSB_CLK_NB_P FSB_CLK_NB_N CLK_NB_OE_L NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N NB_CLK_DREFCLKIN_P NB_CLK_DREFCLKIN_N NB_CLK_DREFSSCLKIN_P NB_CLK_DREFSSCLKIN_N CPU_THERMTRIP_R TP_SB_SUS_CLK 51D7 61C7 61C7 87C6 66C8 23C3 32B3 39C8 42A8 43C8 51C5 55C3 65B8 66B6 66C6 41B5 66B8 5C1 6A1 6A2 23C3 41B6 47C7 48C3 51C5 64C8 66A6 23C3 51C5 52A2 61C7 65B8 66B2 66B3 66B5 7B3 21C4 61C7 9C1 61C7 7C6 33C4 34D3 34D5 7C6 33C4 34D3 34D5 82A4 5C4 6C6 6C7 14B7 22A6 26A4 26B1 26C1 26C3 79A8 5C4 6C6 6C7 14B7 22A6 26A4 26B1 26C1 26C3 79A8 82A4 26B1 70A5 7C8 7D8 12C4 12D4 87D6 12A6 33C4 34D3 34D5 I142 I141 14C4 33B4 34C4 34C5 14C4 34B2 34B4 I140 14C4 34B2 34B4 I139 14B4 33B4 34B4 34B5 I143 14C4 33B4 34B4 34B5 I164 PP3V42_G3H PP5V_S0 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE LPC_AD LPC_AD LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L SMC_TMS DEBUG_RST_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L FWH_INIT_L PCI_CLK_PORT80_LPC LPC_AD LPC_AD INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L SV_SET_UP 7C8 7D8 12C4 87C6 I227 7D6 12C4 87D6 I228 7D6 12C4 87D6 I229 7B3 7B4 7C3 7C4 12B6 12C6 12D6 87D6 I230 7D6 12B4 87D6 I231 7B3 7B4 7C3 7C4 12B4 87D6 I232 7D6 12B4 87D6 I233 7B3 7B4 7C3 7C4 12B4 87D6 I235 7B3 7B4 7C3 7C4 12B4 87D6 I234 7D6 12B4 87D6 I236 7D6 12B4 87D6 I237 7D6 12B4 87D6 I238 7D8 12A4 12B4 87D6 I239 I241 I242 I243 opening for use as engineering probe point I244 I245 Misc EXPOSED_VIA Nets I246 I247 EXPOSED_VIA I280 I248 DMI_N2S_P DMI_N2S_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N USB_BT_P USB_BT_N I250 14B4 22D2 I249 14B4 22D2 I251 21B6 33B4 34C3 34C5 I253 21B6 33B4 34C3 34C5 I252 6C1 6C2 6C3 22C2 81A4 I254 6C1 6C2 6C3 22C2 81A4 I256 I255 I257 I258 Misc NO_TESTs NO_TEST I259 I260 EXPOSED_VIA I261 I281 I282 I283 TRUE TRUE TRUE USB2_CAMERA_P_F USB2_CAMERA_N_F TP_FW_CTL 45B5 I263 45B5 I262 37C3 I264 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I165 22B3 51C7 53B4 I166 51B5 52B2 53B4 26B1 53B4 51C1 53B4 51B5 52B2 53B4 51C1 53B4 47B5 51C7 52B2 52B3 53B4 21C4 51D5 52D3 52D5 53C5 I138 34D6 53C5 21D4 51C7 53C5 60C6 21D4 51C7 53C5 60C6 23C8 51C7 53C5 60C6 23C5 51C5 52A2 53B5 60C6 51B5 52B2 53B5 51C5 52B2 53B5 51C3 52D6 53B5 51C1 53B5 47B5 51C7 52B2 52B3 53B5 23B6 23C3 53B5 PP5V_S0_ISENSECAL PP1V8_S3 PP1V05_S0 PPVCORE_S0_CPU PPVCORE_D3C_GPU ISENSE_CAL_EN GND TRUE TRUE TRUE TRUE TRUE TRUE TRUE 67D8 34C8 55A4 65A2 67D6 25C4 25D3 34B8 34C6 19D7 21C1 24C3 24D3 19D1 19D2 19D5 19D6 16D3 17D3 17D6 19C8 12B7 12C2 13B5 16C8 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 8B5 8D7 9D7 55A6 55D7 61D1 67D1 67D3 55A5 55C7 67A6 67A8 71B7 71C1 72D8 77A7 51B7 55A8 FUNC_TEST I286 7B3 21C4 87C6 I169 21C4 I269 PP5V_S3 USB2_CAMERA_N USB2_CAMERA_P PP5V_S3_CAMERA_F TRUE TRUE TRUE TRUE 5D4 45C3 52B8 62A2 67B1 67B3 81C4 81C6 6D1 6D2 6D3 22C2 45C3 6D1 6D2 6D3 22C2 45B3 I285 45C5 14B7 23C3 61C8 87C6 62A8 62C1 66C5 25B6 25C2 25C6 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25C8 25D6 48B6 67C6 67C8 PP1V5_S0 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE ALS_GAIN LTALS_OUT ACZ_SDATAIN ACZ_SDATAOUT ACZ_BITCLK ACZ_RST_L EXCARD_OC_L LTUSB_OC_L LT2USB_OC_L PM_SLP_S3_LS5V PM_SLP_S4_L SYS_ONEWIRE MINI_CLKREQ_L SMC_EXCARD_CP EXCARD_CLKREQ_L SMC_EXCARD_PWR_EN LIO_PLT_RESET_L ACZ_SYNC USB2_LT_N USB2_LT_P USB2_EXCARD_N USB2_EXCARD_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N USB2_LT2_N USB2_LT2_P PCIE_MINI_R2D_C_N PCIE_MINI_R2D_C_P PCIE_MINI_D2R_N PCIE_MINI_D2R_P PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N SMBUS_SB_SCL SMBUS_SB_SDA PCIE_WAKE_L SMC_BC_ACOK SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA 6D5 48C4 51B5 48C3 57C7 21C7 48B3 87B4 21C7 48B3 87B4 21C7 48B3 87B4 21C7 48B3 87B4 6C1 6C3 22C4 22D8 48C3 52B3 6D1 6D3 22C4 22D8 48C3 6C1 6C3 22C4 22D8 48C3 6A1 6A2 48C3 62B3 66C6 66C7 64C8 5C4 6A1 6A2 23C3 41B6 47C7 48C3 51C5 66A6 66B8 48C3 51B7 52B2 33B4 34A3 34A4 48C3 48C3 51B7 52A2 C 33B4 34A3 34A4 48C3 48C3 51B7 26C1 48C3 21C7 48B3 87B4 6D1 6D2 6D3 22C2 48C6 6D1 6D2 6D3 22C2 48C6 6C1 6C2 6C3 22C2 48C6 6C1 6C2 6C3 22C2 48C6 48B6 50C5 50C6 48B6 50C5 50C6 22D4 50B5 22D4 50C5 48B6 50B3 50B6 48B6 50C3 50C6 33B4 34C3 34C5 48B6 33B4 34B3 34B5 48B6 6C1 6C2 6C3 22C2 48C6 6C1 6C2 6C3 22C2 48C6 48C6 50C5 50C6 48C6 50C5 50C6 22D4 50C5 22D4 50C5 33B4 48C6 48C6 50C3 50C6 48C6 50C3 50C6 34D4 34D5 33B4 34D4 34D5 48C6 46B6 48B3 81C3 28A6 29A6 33B6 23D5 27B6 27C6 27D6 27D7 27D8 23C8 39C6 48C3 48C3 51C5 52A2 68A6 69A6 81C3 27C3 27C5 27C6 48B6 51B5 81C3 81C3 48B3 33B6 28A6 27D7 27C6 23D5 27B6 27D6 27D8 29A6 46B6 B 27B3 27C3 27C5 27C6 48B6 51B5 Inverter Connector 7B3 21C4 87C6 D 27C1 27C2 27C3 51B5 68B2 TRUE 23C3 51D7 22A6 37C2 I273 23C1 51D7 I275 23C3 26A6 I277 21D6 26D4 I276 23C8 33C4 I278 GND_CHASSIS_INVERTER PPBUS_S0_INVERTER PP5V_INVERTER_SW INVERTER_PWM GND_CHASSIS_INVERTER TRUE TRUE TRUE TRUE TRUE 5B2 6A6 6A8 45B5 45C5 79A5 79A6 Left I/O Power Connector 79B5 79B5 FUNC_TEST 79A5 5B2 6A6 6A8 45B5 45C5 79A5 79A6 23C8 33C4 TRUE TRUE PP18V5_DCIN PPBUS_G3H TRUE GND 68B8 68C5 61D7 62D7 64A6 5C4 41C6 42B8 43D8 55D3 61D4 64D7 65B7 65D6 67C1 67C3 68D5 69C1 71D7 79B7 23C5 26B8 14B6 26B5 61C7 7D6 11B5 12C4 87D6 7A3 12A4 Request for at least 10 GND test points 7B3 12B4 87D6 14B6 22A6 78C7 78C7 78C7 78B7 78B7 66B6 54D4 33C7 78B7 26B4 24B3 20A4 20B4 5D4 10C5 14C7 14D6 21C3 21D3 25B8 25C4 27D5 27D8 49B5 49C4 62A6 65B3 82A4 82B3 33C5 67A3 67B3 67C3 67C5 71D2 79A8 79D3 57B6 58C4 58C7 60C7 60D4 61A5 61D8 33D3 33D8 34A8 36D6 40B6 26B6 26B8 26D1 27C3 27D3 24B5 24C3 24D3 25A4 25B4 Thermal Sensors FUNC_TEST (=PP3V3_S0_CK410) 17C6 19C6 19C7 TRUE 22B5 23B3 23D5 I173 25C6 25D3 25D8 28A6 29A3 29A6 TRUE 49C7 52D3 54B5 I174 65D6 66B1 66B5 TRUE 82C6 82D5 I172 TRUE I175 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 38D5 HSTHMSNS_DX_P HSTHMSNS_DX_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N Functional / ICT Test 54C5 SYNC_MASTER=(MASTER) 54D5 54C5 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING SMC TPs FUNC_TEST I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 38C6 6C3 6C5 6C6 38B2 38D5 42C1 I177 38D3 I176 PM_SYSRST_L SMC_ONOFF_L TRUE TRUE (=PP1V2_S3_ENET) (=PP3V3_S3_ENET) (=PP2V5_S3_ENET) II NOT TO REPRODUCE OR COPY IT 23C5 26C5 51B7 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 51C5 52B2 52C6 81C4 SIZE 5D4 39A8 39D7 63B3 67D6 67D8 39A5 39B4 39B5 39B8 39D6 39D8 41C4 67D1 67D3 39D3 63C3 63D3 63D4 67B6 67B8 APPLE COMPUTER INC DRAWING NUMBER D SCALE 39D5 40D5 REV 051-7164 SHT NONE 51C5 52B2 68B2 27C1 27C2 27C3 51B5 68B2 21C5 51C7 53C4 60C6 6C6 6C7 23C3 CPU_PWRGD TP_CPU_CPUSLP_L PM_DPRSLPVR CPU_DPSLP_L PM_LAN_ENABLE PCI_RST_L PM_RSMRST_L PM_SB_PWROK SB_RTC_RST_L PM_STPCPU_L PM_STPPCI_L VR_PWRGD_CK410 VR_PWRGOOD_DELAY FSB_CPURST_L FSB_SLPCPU_L FSB_DPWR_L NB_SB_SYNC_L PP2V5_S0_GPU_TPVDD PP2V5_S0_GPU_TXVDDR PP2V5_S0_GPU_AVDD PP2V5_S0_GPU_A2VDD PP2V5_S0_GPU_LPVDD PP2V5_S0_GPU_LVDDR PP3V3_S0 PP3V3_S0_CK410_VDD48 PP3V3_S0_CK410_VDD_PCI PP3V3_S0_CK410_VDD_REF PP3V3_S0_CK410_VDD_CPU_SRC PP3V3_S0_CK410_VDDA PP3V3_FWPHY PP3V3_FWPHY_AVDD PP3V3_FWPHY_PLLVDD PP1V95_FWPHY PP1V95_FWPHY_PLLVDD PP1V2_S3 PP3V3_S3AC PP2V5_S3 PP2V5_S3_ENET_AVDD 68B1 68B2 21D4 51D7 53C4 60C6 23C8 51C5 53C4 60C6 Request for at least GND TPs per resistor I167 SMC_BS_ALRT_L SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA 21D4 51D7 53C4 60C6 21C2 I168 TRUE TRUE TRUE 68A1 68A2 69B1 FUNC_TEST TRUE TRUE FUNC_TEST 14C4 33B4 34C4 34C5 BATT_POS BATT_NEG Left I/O Data Connector 12A6 33C4 34D3 34D5 14B6 33B4 TRUE TRUE 66D2 67D3 67D5 68B8 69A8 69B8 69C8 81D4 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 67B3 71A6 79B8 80A1 80B5 81B3 5D2 5D4 25D8 31C5 36D6 53C4 55A8 57B5 58C4 58C7 61D7 62B1 66B5 67A1 67B1 Resistor Calibration 7C8 21C4 87C6 FUNC_TEST should have a via with 10-mil soldermask I279 58B3 26B1 60B7 7D6 12C4 87D6 I240 A 58B3 26B1 51C7 MAC-1 TPs FSB_A_L FSB_ADS_L FSB_ADSTB_L FSB_BNR_L FSB_BREQ0_L FSB_D_L FSB_DBSY_L FSB_DINV_L FSB_DRDY_L FSB_DSTBN_L FSB_DSTBP_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L EXPOSED_VIA property indicates that the net TRUE TRUE TRUE TRUE TRUE TRUE 58B6 Camera Connector EXPOSED_VIA TRUE I135 58B6 LPC+ Debug Connector CPU FSB NO_TESTs TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FAN_RT_PWM FAN_RT_TACH 71A6 79B8 80A1 80B5 81B3 58C4 58C7 61D7 62B1 5D2 5D4 25D8 31C5 I134 36D6 53C4 55A8 57B5 66B5 67A1 67B1 67B3 FUNC_TEST Characterization TPs I200 PP5V_S0 TRUE TRUE FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 19A5 19B5 19B8 19C1 19C4 13C5 13D2 16D1 17B6 17C6 31C5 32C6 37B2 64A6 64C1 5B2 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 67B6 67B8 64A4 67B6 67B8 72B8 73A5 73A8 73B5 73B8 75D5 75D8 76D5 76D8 82D7 17C6 17D6 19A4 19A6 19A8 19C5 19D7 63D1 66B5 67A6 67A8 67B6 82C5 82D3 71B7 I198 FUNC_TEST 25D3 34B8 34C6 34C8 55A4 65A2 67D6 67D8 13B5 16C8 16D3 17D3 17D6 5B2 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 19C8 19D1 19D2 19D5 19D6 19D7 21C1 24C3 24D3 25C4 Request for at least 10 GND TPs NO_TEST Battery Connector 62C5 66A6 06004 OF 87 A USB Port "A" (Debug Port) = Right USB 2.0 Port R0600 51B5 48C4 5C1 ALS_GAIN RTALS_GAIN NC_CPU_A32_L NC_CPU_A32_L 6D7 7C8 MAKE_BASE=TRUE 6D8 7C8 28C3 NC_CPU_A33_L NC_CPU_A33_L 6D7 7B8 MAKE_BASE=TRUE 6D8 7B8 29C3 MEM_A_A 39C8 6D4 NC_ENET_CTRL12 MEM_B_A 39C8 6D4 NC_ENET_CTRL25 NC_MEM_B_A NC_CPU_A34_L NC_CPU_A34_L 6D7 7B8 MAKE_BASE=TRUE 6D8 7B8 TP_NB_CFG NO_TEST=TRUE NC_CPU_A35_L NC_CPU_A35_L 6D8 7B8 NO_TEST=TRUE 47C5 22D8 22C4 6D2 6D1 47C5 22D8 22C4 6D3 6D1 RTUSB_OC_L NC_CPU_A36_L 6D8 7B8 NC_CPU_A37_L 6D8 7B8 NC_ENET_CTRL12 6D5 39C8 NC_ENET_CTRL25 6D5 39C8 USB_TRACKPAD_P 81C4 22C2 6D3 6D1 81C4 22C2 6D2 6D1 USB_TRACKPAD_N 81C4 22C2 6D3 6D1 81C4 22C2 6D2 6D1 14C6 22D8 22C4 6D1 NB_CFG 14C6 NC_CPU_A38_L 6D8 7B8 NB_CFG 14C6 NC_CPU_A39_L 6D8 7B8 ENET_LOWPWR_EN UNUSED_USB_B_OC_L USB2_LT_P 48C6 22C2 6D3 6D1 5C1 48C6 22C2 6D2 6D1 5C1 USB2_LT_N 48C6 22C2 6D3 6D1 5C1 48C6 22C2 6D2 6D1 5C1 NB_CFG 14C6 22D8 22C4 SB_GPIO30 TP_NB_CFG NB_CFG TP_NB_CFG NO_TEST=TRUE NB_CFG 14C6 39B8 NC_CPU_APM0_L 6D8 7B8 6D2 6D3 22C2 81C4 USB_TRACKPAD_N 6D2 6D3 22C2 81C4 UNUSED_USB_B_OC_L 6D3 22C4 22D8 USB2_LT_P USB2_LT_P NOTE: NB_CFG require test access USB2_LT_N D 5C1 6D2 6D3 22C2 48C6 USB2_LT_N LTUSB_OC_L 5C1 6D2 6D3 22C2 48C6 LTUSB_OC_L 5C1 6D3 22C4 22D8 48C3 MAKE_BASE=TRUE USB Port "D" = Camera NOTE: BOM options "USB_G_OC_PU" and "ENET_LOWPWR_EN" are mutually-exclusive MAKE_BASE=TRUE NC_CPU_APM0_L USB_TRACKPAD_P MAKE_BASE=TRUE ENET_LOWPWR_EN 5% 1/16W MF-LF 402 MAKE_BASE=TRUE 6D7 7B8 MAKE_BASE=TRUE 48C3 22D8 22C4 6D1 5C1 14C6 NC_CPU_A39_L USB_TRACKPAD_N MAKE_BASE=TRUE TP_NB_CFG NO_TEST=TRUE 6D7 7B8 MAKE_BASE=TRUE USB_TRACKPAD_P USB Port "C" = Left USB 2.0 Port MAKE_BASE=TRUE NC_CPU_A38_L 6D2 6D3 22C4 22D8 47C5 MAKE_BASE=TRUE R0690 NO_TEST=TRUE 6D7 7B8 MAKE_BASE=TRUE 6D2 6D3 22C2 47B5 RTUSB_OC_L MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CPU_A37_L RTUSB_OC_L USB Port "B" = Trackpad (Geyser) Ethernet Powr Management Support TP_NB_CFG NO_TEST=TRUE 6D7 7B8 MAKE_BASE=TRUE 6D2 6D3 22C2 47B5 USB2_RT_N MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CPU_A36_L 6D7 7B8 MAKE_BASE=TRUE USB2_RT_P USB2_RT_N MAKE_BASE=TRUE MAKE_BASE=TRUE NB_CFG TP_NB_CFG USB2_RT_P MAKE_BASE=TRUE 47B5 22C2 6D2 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE 6D7 7B8 MAKE_BASE=TRUE 47B5 22C2 6D3 6D1 47B5 22C2 6D3 6D1 6D4 57C4 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE D NC_MEM_A_A MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE USB2_RT_P 6D1 USB2_RT_N 47B5 22C2 6D2 6D1 RTALS_GAIN MAKE_BASE=TRUE 5% 1/16W MF-LF 402 USB2_CAMERA_P 45B3 22C2 6D3 6D1 5B2 45B3 22C2 6D2 6D1 5B2 USB2_CAMERA_N 45C3 22C2 6D3 6D1 5B2 45C3 22C2 6D2 6D1 5B2 USB2_CAMERA_P USB2_CAMERA_P 5B2 6D2 6D3 22C2 45B3 USB2_CAMERA_N 5B2 6D2 6D3 22C2 45C3 UNUSED_USB_D_OC_L 6C3 22C4 22D8 USB2_EXCARD_P 5C1 6C2 6C3 22C2 48C6 MAKE_BASE=TRUE NO_TEST=TRUE USB2_CAMERA_N MAKE_BASE=TRUE NC_CPU_APM1_L 6C7 7B8 MAKE_BASE=TRUE NC_CPU_APM1_L 6C8 7B8 NC_CPU_EXTBREF 6C8 7B6 NC_CPU_HFPLL 6C8 7B8 TP_NB_CFG NB_CFG 22D8 22C4 6C1 14C6 MAKE_BASE=TRUE UNUSED_USB_D_OC_L MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_EXTBREF 6C7 7B6 MAKE_BASE=TRUE NO_TEST=TRUE FireWire Aliases 23C3 6C6 5B4 NC_CPU_HFPLL 6C7 7B8 MAKE_BASE=TRUE TP_SB_SUS_CLK TP_SB_SUS_CLK 5B4 6C7 23C3 MAKE_BASE=TRUE NC_CPU_SPARE0 44D3 43B2 6C3 NC_CPU_SPARE0 USB2_EXCARD_N 48C6 22C2 6C3 6C1 5C1 48C6 22C2 6C2 6C1 5C1 PPFW_PORTA_VP_UF USB2_EXCARD_P PPFW_PORTB_VP_UF 52B3 48C3 22D8 22C4 6C1 5C1 PPFW_PORTB_VP_UF USB2_EXCARD_N USB2_EXCARD_N 5C1 6C2 6C3 22C2 48C6 MAKE_BASE=TRUE 6C5 43B2 44D3 MAKE_BASE=TRUE 44B3 43A2 6C3 NC_CPU_SPARE1 PPFW_PORTA_VP_UF 6C8 7B6 NO_TEST=TRUE 6C7 7B6 MAKE_BASE=TRUE USB2_EXCARD_P 48C6 22C2 6C3 6C1 5C1 48C6 22C2 6C2 6C1 5C1 MAKE_BASE=TRUE NO_TEST=TRUE 6C7 7B6 MAKE_BASE=TRUE USB Port "E" = ExpressCard EXCARD_OC_L EXCARD_OC_L 5C1 6C3 22C4 22D8 48C3 52B3 MAKE_BASE=TRUE 6C5 43A2 44B3 MAKE_BASE=TRUE NC_CPU_SPARE1 6C8 7B6 NC_CPU_SPARE2 6C8 7B6 NC_CPU_SPARE4 6C8 7B6 USB Port "F" = USB 1.1 Hub NO_TEST=TRUE NC_CPU_SPARE2 6C7 7B6 MAKE_BASE=TRUE 44B8 44A8 43B8 42C4 38D7 38B5 6C5 6C3 5A4 44B8 44A8 43B8 42C4 38D7 38B5 6C6 6C3 5A4 PP3V3_FWPHY NO_TEST=TRUE NC_CPU_SPARE4 6C7 7B6 MAKE_BASE=TRUE Inverter PWM Reset Alias PP3V3_FWPHY PP3V3_FWPHY VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.20 mm MAKE_BASE=TRUE PP3V3_FWPHY 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 PP3V3_FWPHY NO_TEST=TRUE C 82A4 79A8 26C3 26C1 26B1 26A4 22A6 14B7 6C6 5C4 PLT_RST_L PLT_RST_L 5C4 6C7 14B7 22A6 26A4 26B1 26C1 26C3 79A8 82A4 USB_HUB_P 46B7 46B3 22C2 6C3 6C1 USB_HUB_N 46B3 46A7 22C2 6C3 6C1 USB_HUB_P USB_HUB_N 6C2 6C3 22C2 46B3 46B7 USB_HUB_N 6C2 6C3 22C2 46A7 46B3 MAKE_BASE=TRUE 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 PP3V3_FWPHY USB_HUB_P MAKE_BASE=TRUE USB Port "G" = Bluetooth (M13P) 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 81A4 22C2 6C2 6C1 5A7 USB_BT_P 81A4 22C2 6C3 6C1 5A7 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 81A4 22C2 6C2 6C1 5A7 USB_BT_N 81A4 22C2 6C3 6C1 5A7 USB_BT_P USB_BT_P 5A7 6C2 6C3 22C2 81A4 USB_BT_N 5A7 6C2 6C3 22C2 81A4 C MAKE_BASE=TRUE PP3V3_FWPHY USB_BT_N MAKE_BASE=TRUE 42C1 38D5 38B2 6C5 6C3 5A4 PP1V95_FWPHY 42C1 38D5 38B2 6C6 6C3 5A4 PP1V95_FWPHY PP1V95_FWPHY VOLTAGE=1.95V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE PP1V95_FWPHY 5A4 6C3 6C5 6C6 38B2 38D5 42C1 USB Port "H" = 2nd Left USB 2.0 Port 5A4 6C3 6C5 6C6 38B2 38D5 42C1 48C6 22C2 6C2 6C1 5B1 USB2_LT2_P 48C6 22C2 6C3 6C1 5B1 5B1 USB2_LT2_N 48C6 22C2 6C3 6C1 5B1 USB2_LT2_P USB2_LT2_P 5B1 6C2 6C3 22C2 48C6 MAKE_BASE=TRUE 48C6 22C2 6C2 6C1 51D7 37A8 6C3 SMC_RSTGATE_L SMC_RSTGATE_L 6C5 37A8 51D7 48C3 22D8 22C4 6C1 5C1 MAKE_BASE=TRUE 37C6 22A7 PCI_AD USB2_LT2_N USB2_LT2_N 5B1 6C2 6C3 22C2 48C6 MAKE_BASE=TRUE LT2USB_OC_L LT2USB_OC_L 5C1 6C3 22C4 22D8 48C3 MAKE_BASE=TRUE =FW_PCI_IDSEL 37B7 PCI_GNT3_L 6B5 22B6 37D3 46C3 6B2 TP_USB2_3G_P PCI_REQ3_L 6B5 22B6 26D2 37D3 46C3 6B2 TP_USB2_3G_N MAKE_BASE=TRUE 37D3 22B6 6B3 PCI_GNT3_L TP_USB2_3G_P MAKE_BASE=TRUE 37D3 26D2 22B6 6B3 6B3 46C3 MAKE_BASE=TRUE PCI_REQ3_L TP_USB2_3G_N MAKE_BASE=TRUE 6B3 46C3 MAKE_BASE=TRUE LVDS Pull Down Aliases Chassis connection to be made at the fan cutout near the right ALS NO STUFF NO STUFF R0601 GND_CHASSIS_FANFRAME SH0601 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V EMI-SPRING Thermal Module Holes Not stuffed at Proto 82C8 =LVDS_PD_L_CLK_N 82C8 =LVDS_PD_L_CLK_P 78A3 79D7 82C3 LVDS_L_DATA_N 78A3 79D7 82C3 MAKE_BASE=TRUE Top CPU TM Hole LVDS_L_DATA_P MAKE_BASE=TRUE Add one through via per hole to GND or blind vias per side per hole to GND Top GPU Right TM Hole 82D8 82C3 79D7 78A3 6B1 LVDS_L_DATA_P 82D8 82C3 79D7 78A3 6B1 LVDS_L_DATA_N LVDS_L_DATA_P 6B2 78A3 79D7 82C3 82D8 MAKE_BASE=TRUE 5% 1/16W MF-LF 402 0G-502620R LVDS_L_DATA_N 6B2 78A3 79D7 82C3 82D8 MAKE_BASE=TRUE 82D8 82C3 79D7 78A3 6B1 LVDS_L_CLK_N 82C8 82C3 79D7 78A3 6B1 LVDS_L_CLK_P LVDS_L_CLK_N 6B2 78A3 79D7 82C3 82D8 MAKE_BASE=TRUE Chassis connection to be made at the mounting hole northwest of the DVI connector Plated hole B ZT0600 195R106 82C8 GND_CHASSIS_DVI_TOP MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 82C8 C0600 GND_CHASSIS_DVI_TOP GND_CHASSIS_DVI_TOP GND 0.01UF 10% 50V Chassis connection to be made on FW shell X7R 402 6B6 6A6 6B6 6B8 80A3 80A5 Left CPU TM Hole 44C1 HOLE-VIA-P5RP25 44A1 40B2 6A6 GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT ZT0612 6A6 6B8 80A2 80B5 GND_CHASSIS_ENET =LVDS_PD_U_CLK_N 82B8 =LVDS_PD_U_CLK_P C0612 10% 50V X7R 402 6A6 6A8 40B2 44A1 44C1 6A6 6A8 40B2 44A1 44C1 LVDS_U_DATA_P =LVDS_PD_U_DATA_P C0613 C0610 0.01UF 0.01UF 10% 50V X7R 402 10% 50V X7R 402 82B8 C0611 82C3 82B8 79D7 78B3 6A1 10% 50V X7R 402 LVDS_U_CLK_N 82C3 82B8 79D7 78B3 6A1 LVDS_U_CLK_P SHLD-SM-LF 6A2 78B3 79D7 82B8 82C3 MAKE_BASE=TRUE Base net is PM_SLP_S3_LS5V PM_SLP_S4_L MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE GND_CHASSIS_BATTCONN_HOLE C0619 6A6 6A8 44A1 44A3 47B2 0.01UF 10% 50V X7R 402 6A6 6A8 44A1 44A3 47B2 6A6 6A8 44A1 44A3 47B2 PM_SLP_S4_L 66A6 64C8 51C5 48C3 47C7 41B6 23C3 6A1 5C4 5C1 66B8 1GND_CHASSIS_BATTCONN_HOLE 6A6 69A1 5C1 5C4 6A2 23C3 41B6 47C7 48C3 51C5 64C8 66A6 66B8 Base net is PM_SLP_S4_L 66C7 66C6 62B3 48C3 6A1 5C1 C0614 PM_SLP_S3_LS5V PM_SLP_S3_LS5V 5C1 6A2 48C3 62B3 66C6 66C7 0.01UF 10% 50V X7R 402 Signal Aliases SYNC_MASTER=(MASTER) C0602 GND_CHASSIS_LVDS GND_CHASSIS_LVDS GND_CHASSIS_LVDS GND_CHASSIS_LVDS 6A6 6A8 79B2 79C3 79D2 79D3 6A6 6A8 79B2 79C3 79D2 79D3 ZT0610 ZT0614 HOLE-VIA-P5RP25 SYNC_DATE=(MASTER) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V 6A6 6A8 79B2 79C3 79D2 79D3 GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER 5B2 6A6 6A8 45B5 45C5 79A=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7164 06004 OF 85 87 A M9 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO TABLE_SPACING_RULE_HEAD BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION SPACING_RULE_SET TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.2 DEFAULT LAYER LINE-TO-LINE SPACING WEIGHT 0.1 MM ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM MEM_CLK * BGA BGA_P2MM CLK_FSB * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_MED * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM TABLE_SPACING_RULE_ITEM * TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DEFAULT * Y =55_OHM_SE =55_OHM_SE 30 MM MM MM STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT TABLE_SPACING_RULE_ITEM BGA_P1MM * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM BGA_P2MM * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM BGA_P3MM * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET 55_OHM_SE LAYER TOP,BOTTOM ALLOW ROUTE ON LAYER? Y MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP D DIFFPAIR NECK GAP TABLE_SPACING_ASSIGNMENT_ITEM 0.100 MM TABLE_PHYSICAL_RULE_ITEM FB_CLK * BGA BGA_P2MM TABLE_PHYSICAL_RULE_ITEM FSB_DSTB FSB_DSTB BGA BGA_P3MM 0.100 MM TABLE_SPACING_ASSIGNMENT_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 50_OHM_SE TOP,BOTTOM Y 0.124 MM 0.124 MM TABLE_PHYSICAL_RULE_HEAD Allow 0.1 MM on blind-to-buried via dogbones (layers & 11) TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM 1.5:1_SPACING * 0.15 MM ? TABLE_SPACING_RULE_ITEM 1.5:1_SPACING ISL2,ISL11 0.1 MM 1.8:1_SPACING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET 45_OHM_SE LAYER TOP,BOTTOM ALLOW ROUTE ON LAYER? Y MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * 0.18 MM ? * Y TABLE_PHYSICAL_RULE_ITEM 1.8:1_SPACING ISL2,ISL11 0.1 MM 2:1_SPACING * 0.2 MM ? TABLE_PHYSICAL_RULE_ITEM 2.5:1_SPACING * 0.25 MM ? 0.105 MM 0.105 MM =STANDARD =STANDARD MINIMUM LINE WIDTH CLK_PCIE ISL2,ISL11 0.1 MM ? TABLE_SPACING_RULE_ITEM 2:1_SPACING ISL2,ISL11 0.1 MM ? 2.5:1_SPACING ISL2,ISL11 0.1 MM ? TABLE_SPACING_RULE_ITEM CLK_MED ISL2,ISL11 0.1 MM ? CLK_SLOW ISL2,ISL11 0.1 MM ? CPU_COMP ISL2,ISL11 0.1 MM ? CPU_GTLREF ISL2,ISL11 0.1 MM ? CPU_VCCSENSE ISL2,ISL11 0.1 MM ? DMI ISL2,ISL11 0.1 MM ? LVDS_PAIR2PAIR ISL2,ISL11 0.1 MM ? MEM_2OTHER ISL2,ISL11 0.1 MM ? PCIE ISL2,ISL11 0.1 MM ? SATA ISL2,ISL11 0.1 MM ? TMDS_PAIR2PAIR ISL2,ISL11 0.1 MM ? VGA ISL2,ISL11 0.1 MM ? TABLE_SPACING_RULE_ITEM MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM =STANDARD 3:1_SPACING LAYER ? 0.150 MM * 0.3 MM ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET 0.1 MM TABLE_SPACING_RULE_ITEM ? TABLE_SPACING_RULE_ITEM ALLOW ROUTE ON LAYER? ISL2,ISL11 DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM 45_OHM_SE CLK_FSB TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 0.150 MM TABLE_SPACING_RULE_ITEM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 3:1_SPACING ISL2,ISL11 0.1 MM DIFFPAIR NECK GAP 4:1_SPACING * 0.4 MM ? TABLE_SPACING_RULE_ITEM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 4:1_SPACING 0.1 MM ISL2,ISL11 TABLE_SPACING_RULE_ITEM ? TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.185 MM TABLE_SPACING_RULE_ITEM 0.185 MM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE * Y 0.131 MM 0.100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 35_OHM_SE TOP,BOTTOM Y 0.230 MM 0.230 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 35_OHM_SE C * Y 0.165 MM 0.165 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 27P4_OHM_SE TOP,BOTTOM Y 0.335 MM 0.335 MM 27P4_OHM_SE * Y 0.240 MM 0.240 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP C TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM Rules for "Topology #3" for FSB signals, Napa DG tables 4-7 & 4-12 TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET =STANDARD LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_OVERRIDE FSB_ADDR * TABLE_SPACING_RULE_OVERRIDE =2:1_SPACING ? FSB_DATA OVERRIDE OVERRIDE OVERRIDE * =2:1_SPACING ? OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP OVERRIDE DIFFPAIR NECK GAP OVERRIDE OVERRIDE TABLE_SPACING_RULE_OVERRIDE FSB_ADDR2ADDR TABLE_PHYSICAL_RULE_ITEM 35_55_OHM_SE TOP,BOTTOM Y 0.230 MM 0.100 MM 35_55_OHM_SE * Y 0.165 MM 0.076 MM * OVERRIDE OVERRIDE ? FSB_DATA2DATA OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD TABLE_SPACING_RULE_OVERRIDE =STANDARD * OVERRIDE =STANDARD ? OVERRIDE OVERRIDE TABLE_SPACING_RULE_OVERRIDE =STANDARD FSB_ADSTB * OVERRIDE OVERRIDE TABLE_SPACING_RULE_OVERRIDE =2:1_SPACING ? FSB_DSTB OVERRIDE OVERRIDE OVERRIDE * OVERRIDE =2:1_SPACING ? OVERRIDE OVERRIDE TABLE_SPACING_RULE_OVERRIDE Unsupported rule FSB_ADDR2ADSTB PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 75_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD * OVERRIDE TABLE_PHYSICAL_RULE_HEAD OVERRIDE TABLE_SPACING_RULE_OVERRIDE =2:1_SPACING ? FSB_DATA2DSTB OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM * OVERRIDE =2:1_SPACING ? OVERRIDE OVERRIDE TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_ASSIGNMENT_ITEM LVDS * LVDS_100D TMDS * TMDS_100D TMDSCONN * TMDS_100D MEM_2OTHER TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_OVERRIDE OVERRIDE * OVERRIDE TABLE_SPACING_RULE_OVERRIDE 0.5 MM ? PCI_2PCI OVERRIDE OVERRIDE OVERRIDE * OVERRIDE 0.1 MM ? OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * Y 0.149 MM 0.149 MM =STANDARD 0.125 MM 0.125 MM 70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.185 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 75_OHM_DIFF * Y 0.131 MM 0.131 MM =STANDARD 0.125 MM 0.125 MM 75_OHM_DIFF TOP,BOTTOM Y 0.161 MM 0.161 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCI PCI * PCI_2PCI TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM VGA * TABLE_SPACING_ASSIGNMENT_ITEM VGA_75S TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ENETCONN * * ENET TMDSCONN * * TMDS TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM B TABLE_SPACING_ASSIGNMENT_ITEM B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF * Y 0.115 MM 0.111 MM =STANDARD 0.125 MM 0.125 MM "Stale" physical / spacing types TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET FSB_ANALOG * * FSB_COMMON TABLE_PHYSICAL_RULE_ITEM 80_OHM_DIFF TOP,BOTTOM Y 0.140 MM 0.140 MM 0.125 MM 0.125 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM FSB_P2MM * * FSB_COMMON TABLE_PHYSICAL_RULE_ITEM I2C * * SMB TABLE_PHYSICAL_RULE_ITEM GND * * STANDARD MEM_PP1V8_S3 * * STANDARD FB_PP1V8 * * STANDARD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_ASSIGNMENT_ITEM 85_OHM_DIFF * Y 0.101 MM 0.101 MM 85_OHM_DIFF TOP,BOTTOM Y 0.125 MM 0.125 MM =STANDARD 0.125 MM 0.125 MM 0.125 MM 0.125 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_ASSIGNMENT_ITEM DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF * Y 0.102 MM 0.102 MM 90_OHM_DIFF TOP,BOTTOM Y 0.130 MM 0.130 MM =STANDARD 0.220 MM 0.220 MM 0.220 MM 0.220 MM FSB_ANALOG TABLE_PHYSICAL_RULE_ITEM FSB_P2MM I2C TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF * Y 0.080 MM 0.080 MM =STANDARD 0.200 MM 0.200 MM GND MEM_PP1V8_S3 TABLE_PHYSICAL_RULE_ITEM FB_PP1V8 TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF TOP,BOTTOM Y 0.099 MM 0.099 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 0.200 MM 0.200 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI PCI_55S M9 Spacing & Physical Constraints TABLE_PHYSICAL_RULE_HEAD A MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF * Y 0.077 MM 0.077 MM =STANDARD 0.330 MM LAYER 0.330 MM ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP 110_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM 0.330 MM 0.330 MM MEM_45S * OVERRIDE OVERRIDE * OVERRIDE NOTICE OF PROPRIETARY PROPERTY 0.100 MM OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MEM_70D OVERRIDE SYNC_DATE=(MASTER) DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SYNC_MASTER=(MASTER) 0.100 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_PHYSICAL_RULE_ITEM MEM_85D * OVERRIDE OVERRIDE II NOT TO REPRODUCE OR COPY IT 0.100 MM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7164 06004 OF 86 87 A NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING MEM_CLK D FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_DATA FSB_55S FSB_DATA FSB_55S FSB_DSTB FSB_55S FSB_DSTB FSB_55S FSB_ADDR FSB_55S FSB_ADDR FSB_55S FSB_ADSTB CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S C CPU_55S CPU_2TO1 CPU_55S CPU_2TO1 CPU_55S CPU_2TO1 CPU_55S CPU_GTLREF CPU_55S CPU_COMP CPU_27P4S CPU_COMP CPU_55S CPU_COMP CPU_27P4S CPU_COMP CPU_55S CPU_ITP CLK_FSB_100D CPU_ITP CLK_FSB_100D CPU_ITP CPU_55S CPU_ITP CPU_55S CPU_2TO1 CPU_55S CPU_2TO1 THERM CPU_27P4S CPU_VCCSENSE THERM CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_RS_L FSB_TRDY_L FSB_CPURST_L FSB_D_L FSB_DINV_L FSB_DSTBP_L FSB_DSTBN_L FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_IERR_L FSB_FERR_L CPU_PWRGD CPU_INTR CPU_NMI CPU_A20M_L CPU_DPSLP_L CPU_IGNNE_L CPU_INIT_L CPU_SMI_L CPU_STPCLK_L CPU_THERMTRIP_L PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_BPM_L CPU_XDP_CLK_P CPU_XDP_CLK_N ITPRESET_L CPU_VID CPU_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N MEM_70D 5B7 7D6 12C4 MEM_CTRL MEM_45S 5B7 7D6 12C4 MEM_CMD MEM_55S 7D6 12C4 MEM_DATA MEM_55S 5B7 7D6 12C4 MEM_DQS MEM_85D FB_CLK FB_75D FB_ADCTRL FB_35S_TO_55S FB_ADCTRL FB_55S FB_DATA FB_40S 5B7 7D6 12B4 LVDS LVDS_100D 5A7 7D6 12B4 TMDS TMDS_100D 7D6 12A4 VGA VGA_75S PCIE PCIE_100D DMI DMI_100D SATA SATA_100D IDE IDE_55S USB2 USB2_90D ENET ENET_100D FW FW_110D SMB SMB_55S SPI SPI_55S CLK_FSB CLK_FSB_100D 5B4 7B3 21C4 CLK_PCIE CLK_PCIE_100D 7C8 21C4 CLK_MED CLK_MED_55S 7C8 21C4 CLK_SLOW CLK_SLOW_55S 5B7 7D6 12B4 7D6 12B4 5A4 7B3 12B4 5B7 7D6 12B4 5B7 7D6 12B4 D 7D6 12A4 5A4 7D6 11B5 12C4 5B7 7B3 7B4 7C3 7C4 12B6 12C6 12D6 5B7 7B3 7B4 7C3 7C4 12B4 5B7 7B3 7B4 7C3 7C4 12B4 5B7 7B3 7B4 7C3 7C4 12B4 5B7 7C8 7D8 12C4 12D4 5A7 7D8 12A4 12B4 5B7 7C8 7D8 12C4 7D6 7C8 21C4 5B4 7B3 21C4 7C8 21C4 7D6 21C4 7C8 21C4 5C4 7C8 21C4 5B4 14B7 23C3 61C8 C 5C4 61C7 7B4 7B3 7B3 7B3 7B3 7C6 11B3 11B3 33C4 34D3 34D5 11B3 33C4 34D3 34D5 11B3 8B7 9C2 87B6 8B7 9C2 87B6 8B6 61B1 8B6 61A1 61A3 61A3 AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO TMDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS I70 TMDS TMDS I71 TMDS TMDS TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN I72 TMDSCONN TMDSCONN I73 TMDSCONN TMDSCONN B SB_ACZ_BITCLK ACZ_BITCLK SB_ACZ_SYNC ACZ_SYNC SB_ACZ_RST_L ACZ_RST_L ACZ_SDATAIN SB_ACZ_SDATAOUT ACZ_SDATAOUT 21C6 5C1 21C7 48B3 21C6 5C1 21C7 48B3 B 21C6 5C1 21C7 48B3 5C1 21C7 48B3 21C6 5C1 21C7 48B3 TMDS_CLK_P TMDS_CLK_N TMDS_DATA_P TMDS_DATA_N TMDS_DATA_P TMDS_DATA_N TMDS_CLK_F_P TMDS_CLK_F_N TMDS_DATA_F_P TMDS_DATA_F_N TMDS_DATA_F_P TMDS_DATA_F_N 78C3 79C7 80B8 78C3 79C7 80C8 78C3 79C7 80A8 80B8 78C3 79C7 80A8 80B8 78C3 79C7 80C8 80D8 78C3 79C7 80C8 80D8 80B5 80B6 80D1 80A5 80C6 80D1 80A6 80B3 80B5 80B6 80D1 80A6 80B3 80B5 80B6 80D1 80B3 80B5 80C6 80D1 80D6 80B3 80B5 80C6 80D1 80D6 M57 NET PROPERTIES A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7164 06004 OF 87 87 A ... IN CONFIDENCE P.51-52 SIZE Sensors P.55 APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051- 7164 06004 OF 87 A U8000 ENABLE J8290 Q7610 3.425 MLB DC in PPDCIN_G3H PP5V_S3 PP3V42_G3H G3Hot... COMPUTER INC PM_SLP_S3_LS5V_L SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY Q4565 SHT NONE REV 051- 7164 SCALE FWPWR_EN DRAWING NUMBER D 06004 OF 87 A PART NUMBER QTY 338S0270 338S0274 341S1931... REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051- 7164 06004 OF 87 A Power Supply NO_TESTs NO_TEST Functional Test Points EXPOSED_VIA TRUE IMVP6_RBIAS