820 3209 a

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ECN DESCRIPTION OF REVISION CK APPD DATE 2012-02-23 SCHEM,MLB,J13 2/23/12 D (.csa) Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 45 46 47 49 50 51 52 53 Contents Date Sync TABLE_TABLEOFCONTENTS_HEAD 11/10/2011 TABLE_TABLEOFCONTENTS_ITEM Table of Contents J30_MLB System Block Diagram J13_MLB_NON_POR 11/10/2011 Revision History J13_MLB_NON_POR 07/27/2011 Revision History (.csa) Page 07/27/2011 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM J30_MLB 07/27/2011 BOM Configuration J30_MLB Functional Test / No Test K21_MLB Power Aliases K21_MLB TABLE_TABLEOFCONTENTS_ITEM 07/29/2011 TABLE_TABLEOFCONTENTS_ITEM 07/29/2011 TABLE_TABLEOFCONTENTS_ITEM Signal Aliases 11/10/2011 J13_MLB_NON_POR TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM CPU DMI/PEG/FDI/RSVD 10/17/2011 J13_MLB_NON_POR 07/27/2011 TABLE_TABLEOFCONTENTS_ITEM CPU CLOCK/MISC/JTAG J30_MLB 07/27/2011 TABLE_TABLEOFCONTENTS_ITEM CPU DDR3 INTERFACES J30_MLB 11/10/2011 TABLE_TABLEOFCONTENTS_ITEM CPU POWER J13_MLB_NON_POR CPU GROUNDS 07/27/2011 TABLE_TABLEOFCONTENTS_ITEM 10/03/2011 TABLE_TABLEOFCONTENTS_ITEM 07/29/2011 TABLE_TABLEOFCONTENTS_ITEM 07/27/2011 TABLE_TABLEOFCONTENTS_ITEM 07/27/2011 TABLE_TABLEOFCONTENTS_ITEM 11/10/2011 TABLE_TABLEOFCONTENTS_ITEM J30_MLB CPU DECOUPLING-I J11_MLB CPU DECOUPLING-II K21_MLB PCH SATA/PCIe/CLK/LPC/SPI J30_MLB PCH DMI/FDI/PM/Graphics PCH PCI/USB/TP/RSVD J30_MLB J13_MLB_NON_POR PCH GPIO/MISC/NCTF J11_MLB PCH POWER J11_MLB PCH GROUNDS J30_MLB PCH DECOUPLING 09/16/2011 TABLE_TABLEOFCONTENTS_ITEM 09/30/2011 TABLE_TABLEOFCONTENTS_ITEM 07/27/2011 TABLE_TABLEOFCONTENTS_ITEM 10/03/2011 TABLE_TABLEOFCONTENTS_ITEM 10/17/2011 TABLE_TABLEOFCONTENTS_ITEM J11_MLB CPU & PCH XDP J13_MLB_NON_POR 11/10/2011 USB HUB & MUX Clock (CK505) and Chipset Support CPU Memory S3 Support J13_MLB_NON_POR 07/29/2011 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB 11/10/2011 TABLE_TABLEOFCONTENTS_ITEM J13_MLB_NON_POR 07/28/2011 DDR3 DRAM CHANNEL A (0-31) K21_MLB DDR3 DRAM CHANNEL A (32-63) K21_MLB TABLE_TABLEOFCONTENTS_ITEM 07/28/2011 TABLE_TABLEOFCONTENTS_ITEM 07/28/2011 TABLE_TABLEOFCONTENTS_ITEM DDR3 DRAM CHANNEL B (0-31) K21_MLB DDR3 DRAM CHANNEL B (32-63) K21_MLB FSB/DDR3/FRAMEBUF Vref Margining J11_MLB DDR3 Bypassing/Termination K21_MLB SecureDigital Card Reader 11/10/2011 J13_MLB_NON_POR Thunderbolt Host (1 of 2) J11_MLB Thunderbolt Host (2 of 2) J11_MLB TBT Power Support 11/10/2011 J13_MLB_NON_POR X21 WIRELESS CONNECTOR J11_MLB SSD CONNECTOR J13_MLB_NON_POR External A USB3 Connector J11_MLB 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 54 55 56 57 61 62 69 70 71 72 73 74 75 76 77 78 79 90 94 97 100 101 102 103 105 106 108 109 D Date Contents Sync 10/17/2011 High Side Current Sensing J13_MLB_NON_POR Thermal Sensors J11_MLB Fan K21_MLB 08/03/2011 07/28/2011 11/10/2011 IPD / KBD Backlight J13_MLB_NON_POR 07/28/2011 SPI ROM K21_MLB 09/30/2011 AUDI0: SPEAKER AMP J11_MLB DC-In & Battery Connectors J13_MLB_NON_POR PBus Supply & Battery Charger 11/10/2011 J13_MLB_NON_POR System Agent Supply 10/17/2011 J13_MLB_NON_POR 5V / 3.3V Power Supply 10/17/2011 J13_MLB_NON_POR 1.5V DDR3 Supply J11_MLB CPU IMVP7 & AXG VCore Regulator J11_MLB CPU IMVP7 & AXG VCore Output J13_MLB_NON_POR CPU VCCIO (1.05V) Power Supply 10/17/2011 J13_MLB_NON_POR Misc Power Supplies K21_MLB Power FETs K21_MLB 11/10/2011 12/02/2011 10/14/2011 10/17/2011 07/28/2011 07/28/2011 C 11/10/2011 Power Control 1/ENABLE J13_MLB_NON_POR 07/28/2011 Internal DisplayPort Connector K21_MLB 10/03/2011 Thunderbolt Connector A J11_MLB 07/28/2011 LCD Backlight Driver K21_MLB CPU Constraints J13_CONSTRAINTS Memory Constraints J13_CONSTRAINTS 01/11/2012 01/11/2012 01/11/2012 PCH Constraints J13_CONSTRAINTS 01/11/2012 PCH Constraints J13_CONSTRAINTS 01/11/2012 Thunderbolt Constraints J13_CONSTRAINTS 01/11/2012 SMC Constraints J13_CONSTRAINTS Project Specific Constraints J13_CONSTRAINTS PCB Rule Definitions J13_CONSTRAINTS 01/11/2012 01/11/2012 07/28/2011 08/04/2011 07/28/2011 B 09/30/2011 10/04/2011 10/11/2011 10/17/2011 Left I/O (LIO) Connector SMC 09/30/2011 11/10/2011 J13_MLB_NON_POR 10/17/2011 J13_MLB_NON_POR 11/10/2011 SMC Support LPC+SPI Debug Connector J13_MLB_NON_POR 09/08/2011 J11_MLB 10/04/2011 SMBus Connections J11_MLB Voltage & Load Side Current Sensing J11_MLB 12/02/2011 TABLE_TABLEOFCONTENTS_ITEM A A DRAWING TITLE SCHEM,MLB,J13 DRAWING NUMBER Schematic / PCB #’s PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL 051-9277 SCHEM,MLB,J13 SCH CRITICAL 820-3209 PCBF,MLB,J13 PCB CRITICAL Apple Inc BOM OPTION NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED DRAWING TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Thu Feb 23 17:52:06 2012 051-9277 REVISION 2.8.0 R BRANCH PAGE OF 109 SHEET 1 OF 73 SIZE D J2500 U1000 J9000 EDP EDP CONN DP0, x1 PG 10 U3100-U3130 U3200-U3230 IVY BRIDGE 2C-35W PG PG 63 CPU XDPPG 23CONN JTAG INTEL CPU EDP MEMORY x8 B AXG=GT2, ULV, 1023P A PCI-E PG MEMORY PCIE1 FDI DMI PG PG PCIE0 PG 29,30 DUAL Channel DDR3-1600MHZ 64-bit U2900-U2930 U3000-U3030 MEMORY x8 PG 11 J6950,U7000 CHARGER PG 27,28 J4501 U4510 POWER CIRCUIT D SATA D PG 54-60 MUX Conn PG 52,53 PG 38 HDD PG 38 U5510 CPU TEMP SENSOR 32KHz PG 47 RTC FDI PG 16 PG 17 PG 17 U5410 GPIOs DMI TBT/MLBBOT/INLET TEMP SENSOR PG 46,47 PG 19 VOLTAGE/CURRENT SENSOR PG 45,46 CLK U2700 J5600 FAN CONN BUFFER SYSTEM CLOCK Misc PG 48 25MHz PG 19 PG 25 25MHz Xtal PG 16 U6100 U4900 SPI Boot ROM SPI SMB_5 SMB_1 SMB_3 ADC FAN0 KBD DRIVER RGB OUT DISPLAY PORT / TBT DPMLO PG 64 TMDS OUT SMB_2 PM_SLP S3/S4 C USB PG 16 HDMI OUT PA_DPSRC_1 MUX PG 41 SERIAL PORT PG 43 LPC 1017P AUXIO PA_AUX LPC+SPI CONN U1800 LVDS OUT LID J5100 PANTHER POINT - MPCH U3600 C SMC INTEL PG 16 TBT Host PA_DPSRC_3 PG 64 DVI OUT SNK0 x4 DPB SNK1 x4 DPC DP OUT J5700 J3500 SD CARD CONN PWR CTRL PA_LSTX/LSRX TRACKPAD PG 49 PG 35 PG 17 PCIe x4 PA_CIO1 PG 17 PA_CIO0 U3500 PG 49 Bluetooth (ON AP) PG 37 USB HUB U2600 U3690 J4600 U4650 MOJO SMC EXTERNAL USB A DEBUG MUX J4001 X21 WIRELESS CONN PG 24 USB PCI-E PG 16 UP TO LANES PG 18 PG 34 (UP TO 10 DEVICES) EEPROM B PG 39 PG 39 PG 16 SMBUS PG 16 PCI HDA PG 18 PG 16 JTAG PG 18 PG 37 USB B USB MUX PG 35 37 PG 34,35 J4001 U5700 SD CARD CONTROLLER SPI PG 49 PG 49 UP TO U9420 KBD CONN KBDLED SATA J9400 J5715 U5750 PG 50 PG 16 SATA0 U2660 U4700 XHCI/EHCI2 MUX USB3 Re-DRIVER J6903 U6210 SPEAKER AMP PG 24 PG 40 PG 51 RIGHT SPEAKER CONN PG 52 J2550 PCH XDP CONN PG 23 J4700 HDA USB CAMERA SPK LEFT USB EXTB LEFT L/O CONN I2C LID PG 40 U6201 U6620 PG SPEAKER AMP LINE IN FILTER PG 10 J4610 CAMERA +ALS CONN PG A I2C J4720 Audio Codec U4730 USB PORT B (LEFT PORT) I2C J4750 THERMAL SENSOR HALL EFFECT PG PG PG HEADPHONE Filter PG SYNC_MASTER=J13_MLB_NON_POR J6701 J6702 J6700 LEFT SPEAKER CONN HEADPHONE/ LINE IN JACK PG 11 PG 11 System Block Diagram LIO BOARD DRAWING NUMBER Apple Inc MIC CONN 051-9277 REVISION 2.8.0 R PG 11 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SYNC_DATE=11/10/2011 PAGE TITLE PG BRANCH PAGE OF 109 SHEET OF 73 SIZE D A J13 POWER SYSTEM ARCHITECTURE D6905 PPVIN_G3H_P3V42G3H PPDCIN_G3H_OR_PBUS ENABLE R0954 PP5V5_CHRG_VDDP D PP5V5_CHAR_VDDP LT3470A A (PAGE 53) AC CPUVCCIOS0_EN ISL95870 U7600 EN 21 F7040 DCIN(14.5V) U3816/U3820 (PAGE 36) A VIN U7000 VIN PPVBAT_G3H_CHRG_RET 24 PBUS SUPPLY/ BATTERY CHARGER R7050 SMC_RESET_L MAX15120 R7550 SMC_GFX_ISENSE U7400 CPUIMVP_VR_ON VR_ON A A VOUT PPVCORE_S0_AXG_REG (PAGE 57) (PAGE 53) 26 25-1 CPUIMVP_PGOOD PGOOD Q7055 (6 TO 8.4V) PM_PWRBTN_L SYS_RERST# PM_SYSRST_L RSMRST# PM_RSMRST_L U2750 V CHGR_BGATE COUGAR-POINT (PCH) PWRBTN# CPUIMVP_AXG_PGOOD PGOODG PPVBAT_G3H_CHGR_R PPVBATT_G3H_CONN TBT_PWR_EN CPU VCORE SMC_BATT_ISENSE J6950 25 PPVCORE_S0_CPU_REG A VOUT VOUT ISL6259HRTZ PP1V05_TBTCIO_FET EN R7510 SMC_CPU_ISENSE SMC_DCIN_ISENSE 2S3P TPS22920 PPBUS_G3H IN 22-1 CPUVCCIOS0_PGOOD PGOOD (PAGE 59) D 22 PPCPUVCCIO_S0_REG SMC_CPU_FSB_ISENSE R7020 ADAPTER C A 1.05V VOUT VCC SMC_RESET_L R7640 VIN PP5V_S0_CPUVCCIOS0 U7090 F6901 6A FUSE 15 ENABLE SMC POWER SN0903048 U5010 (PAGE 42) U6990 (PAGE 52) D7005 J6900 PP3V42_G3H_REG LT3470A R6906 Q5310 SMC_GFX_VSENSE 3.425V G3HOT R6905 V Q5300 SMC_PBUS_VSENSE VIN DDRREG_EN 1.5V S5 DDRVTT_EN R7350 VLDOIN A VOUT1 S3 0.75V U1800 DPWROK PM_PCH_PWRGD SMC_DELAYED_PWRGD 16-1 PGOOD 27 16 PPDDR_S3_REG PPVTT_S0_DDR_LDO VOUT2 TPS51916 U7300 SMC PM_S0_PGOOD U2760 PROCPWRGD DRAMPWROK ALL_SYS_PWRGD Q7801 DDRREG_PGOOD PLTRST# (PAGE 16~21) RC P60 PP5V_S0_VCCSA (PAGE 41) VCC PVCCSA_EN 22 EN CPU_VCCSA_VID PM_SLP_S5_L PG 17 SLP_S5#(E4) (PCH) 11 (PAGE 54) CPU_VCCSA_VID VID0 SLP_SUS# U7940 RC P5V_3V3_SUS_EN P3V3S3_EN RC DDRREG_EN DELAY B 13 PG62 USB_PWR_EN U1800 13-1 PG61 PG62 DELAY PG62 P5VS3_EN EN1 VOUT1 PP3V3_S5_REG 3.3V P3V3S5_EN EN2 PM_SLP_S4_L PG 17 13 P5VS0_EN PP5V_S0_KBDLED 14-1 10-3 LCD_BKLT_EN PP3V3_SUS_FET && BKLT_PLT_RST_L PM_SLP_S3_L SLP_S3#(F4) PG 17 14 (PAGE 16~21) U7740 (PAGE 9~13) CPUVCCIOS0_PGOOD PVCCSA_PGOOD EN SMC ALL_SYS_PWRGD 25 PP3V3_S0_VMON S5_PWRGD R7962 RSMRST_OUT(P15) ISL88042IRTEZ PP1V5_S3RS0_VMON IMVP_VR_ON(P16) SYSRST(PA2) V4MON PPVOUT_SW_LCDBKLT P17(BTN_OUT) (PAGE 62) PM_SLP_S5_L PP3V3_S3_FET 14-1 SLP_S5_L(P95) PM_SLP_S4_L RST* CPUIMVP_VR_ON 26 PM_SYSRST_L PM_PWRBTN_L SMC_RESET_L 6-1 SLP_S4_L(P94) Q7810 PM_SLP_S3_L SLP_S3_L(P93) 16 PP3V3_S0 Q5300 B PM_RSMRST_L 99ms DLY PWR_BUTTON(P90) V3MON 10 PM_DSW_PWRGD 12 RSMRST_IN(P13) U7960 V2MON P15 PWRGD(P12) SMC_ONOFF_L VDD PP5V_S0_VMON VOUT PG62 RESET* KBDLED_ANPDE PP1V05_S0_VMON U9701 EN UNCOREPWRGOOD P3V3S5_PGOOD U5750 MIC2292 PP1V05_SUS_LDO TPS720105 P5V_3V3_SUS_EN (PAGE 65) R7978 VIN 10-4 (PAGE 60) Q7820 VIN LP8550 BKL_EN 23-1 P5VS3_PGOOD PAGE49 CPU U1000 OUT SMC_SYS_KBDLED P5VS3_PGOOD Q9706 SM_DRAMPWROK 23 15 VOUT2 P3V3S5_PGOOD SLP_S4#(H4) PVCCSA_PGOOD PP5V_S0_FET PP3V3_S5 (R/H) (PAGE 55) PGOOD 3A 32V A Q7860 PP5V_S3_REG (L/H) 15 13-2 PPVCCSA_S0_REG P1V8S0_PGOOD 14 VIN 5V TPS51980 U7201 F9700 P5VS3_EN R7140 VOUT PGOOD PPVIN_S5_P5VP3V3 A 10-1 PM_SLP_SUS_L ISL95870AH U7100 VID1 R5430 COUGAR-POINT C PM_MEM_PWRGD PP1V5_S3RS0_FET DELAY SMC_PM_G2_EN 29 28 P1V5CPU_EN P3V3S5_EN CPU_PWRGD 30 (PAGE 56) U4900 PM_DSW_PWRGD PLT_RERST_L P3V3S3_EN P1V8S0_PGOOD U4900 (PAGE 41) SMC_PBUS_VSENSE PM_SLP_S3_R_L P1V8_S0_EN PP5V_SUS_FET PBUSVSENS_EN Q7840 10-2 17 ISL8014A EN U7720 PP1V8_S0_REG (PAGE 60) 18 19 P5V_3V3_SUS_EN A RC CPUVCCIOS0_EN DELAY RC PVCCSA_EN 21 21 22 Q3880 1V05_S0_LDO_EN P5VS0_EN P3V3S0_EN DELAY RC P1V5S0_EN 19 DELAY RC P1V8S0_EN DELAY PBUSVSENS_EN 14-1 14-1 14-1 TBTBST_EN_UVLO VIN LT3957 Q7830 SYNC_DATE=11/10/2011 PAGE TITLE VOUT PP15V_T29_REG T29_PWR_EN TPS22924 DRAWING NUMBER EN U3810 NOTICE OF PROPRIETARY PROPERTY: (PAGE 36) A THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED R4599 PP3V3_S0_SSD_R Apple Inc 051-9277 REVISION 2.8.0 R PP3V3_T29_FET PP1V5S0_EN Revision History PP1V5_S0_REG (PAGE 60) EN R7831 A U3890 14 PP1V05_S0_LDO U7770 P3V3S0_EN U7780 TPS72015 (PAGE 36) 17 TPS720105 EN (PAGE 60) T29_A_HV_EN EN/UVLO 1V05_S0_LDO_EN BRANCH PAGE OF 109 SHEET OF 73 SIZE D A BOM Variants BOM NAME BOM OPTIONS 085-3939 J13 MLB DEVELOPMENT BOM J13_DEVEL:ENG PART NUMBER TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 607-9090 CMN PTS,PCBA,MLB,J13 J13_COMMON TABLE_BOMGROUP_ITEM 639-3552 PCBA,MLB,1.7GHZ,SA 4GB,J13 J13_CMNPTS,EEEE:DYRQ,CPU:1.7GHZ,DDR3:SAMSUNG_4GB 639-3553 PCBA,MLB,1.5GHZ,SA 4GB,J13 J13_CMNPTS,EEEE:DYRM,CPU:1.5GHZ,DDR3:SAMSUNG_4GB 639-3554 PCBA,MLB,1.5GHZ,HY 4GB,J13 J13_CMNPTS,EEEE:DYRN,CPU:1.5GHZ,DDR3:HYNIX_4GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D 639-3555 PCBA,MLB,1.5GHZ,HY 8GB,J13 J13_CMNPTS,EEEE:DYRL,CPU:1.5GHZ,DDR3:HYNIX_8GB 639-3556 PCBA,MLB,1.7GHZ,HY 8GB,J13 J13_CMNPTS,EEEE:DYRK,CPU:1.7GHZ,DDR3:HYNIX_8GB 639-3557 PCBA,MLB,1.7GHZ,HY 4GB,J13 J13_CMNPTS,EEEE:DYRP,CPU:1.7GHZ,DDR3:HYNIX_4GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-3645 PCBA,MLB,1.5GHZ,EL 8GB,J13 639-3644 PCBA,MLB,1.7GHZ,EL 8GB,J13 J13_CMNPTS,EEEE:F0TD,CPU:1.7GHZ,DDR3:ELPIDA_8GB 639-3760 PCBA,MLB,1.8GHZ,SA 4GB,J13 J13_CMNPTS,EEEE:F25Q,CPU:1.8GHZ,DDR3:SAMSUNG_4GB 639-3761 PCBA,MLB,1.8GHZ,HY 8GB,J13 J13_CMNPTS,EEEE:F25T,CPU:1.8GHZ,DDR3:HYNIX_8GB 639-3762 PCBA,MLB,1.8GHZ,HY 4GB,J13 J13_CMNPTS,EEEE:F25Y,CPU:1.8GHZ,DDR3:HYNIX_4GB J13_CMNPTS,EEEE:F0TC,CPU:1.5GHZ,DDR3:ELPIDA_8GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM PCBA,MLB,1.8GHZ,EL 8GB,J13 639-3763 J13_CMNPTS,EEEE:F25P,CPU:1.8GHZ,DDR3:ELPIDA_8GB TABLE_BOMGROUP_ITEM 639-3764 PCBA,MLB,2.0GHZ,SA 4GB,J13 J13_CMNPTS,EEEE:F25N,CPU:2.0GHZ,DDR3:SAMSUNG_4GB 639-3765 PCBA,MLB,2.0GHZ,HY 8GB,J13 J13_CMNPTS,EEEE:F25W,CPU:2.0GHZ,DDR3:HYNIX_8GB 639-3766 PCBA,MLB,2.0GHZ,HY 4GB,J13 J13_CMNPTS,EEEE:F25R,CPU:2.0GHZ,DDR3:HYNIX_4GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-3767 PCBA,MLB,2.0GHZ,EL 8GB,J13 J13_CMNPTS,EEEE:F25V,CPU:2.0GHZ,DDR3:ELPIDA_8GB 639-3790 PCBA,MLB,1.7GHZ,SA 8GB,J13 J13_CMNPTS,EEEE:F27V,CPU:1.7GHZ,DDR3:SAMSUNG_8GB 639-3791 PCBA,MLB,1.8GHZ,SA 8GB,J13 J13_CMNPTS,EEEE:F27Q,CPU:1.8GHZ,DDR3:SAMSUNG_8GB 639-3792 PCBA,MLB,2.0GHZ,SA 8GB,J13 J13_CMNPTS,EEEE:F27R,CPU:2.0GHZ,DDR3:SAMSUNG_8GB 639-3793 PCBA,MLB,1.7GHZ,EL 4GB,J13 J13_CMNPTS,EEEE:F27W,CPU:1.7GHZ,DDR3:ELPIDA_4GB 639-3794 PCBA,MLB,1.8GHZ,EL 4GB,J13 J13_CMNPTS,EEEE:F27Y,CPU:1.8GHZ,DDR3:ELPIDA_4GB Bar Code Labels / EEEE #’s TABLE_BOMGROUP_HEAD BOM NUMBER DESCRIPTION REFERENCE DES 825-7670 QTY LBL,P/N LABEL,PCB,28MM X MM [EEEE_DYRK] CRITICAL CRITICAL BOM OPTION EEEE:DYRK 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DYRL] CRITICAL EEEE:DYRL 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DYRM] CRITICAL EEEE:DYRM 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DYRN] CRITICAL EEEE:DYRN 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DYRP] CRITICAL EEEE:DYRP 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DYRQ] CRITICAL EEEE:DYRQ 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F0TC] CRITICAL EEEE:F0TC 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F0TD] CRITICAL EEEE:F0TD 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F25N] CRITICAL EEEE:F25N 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F25P] CRITICAL EEEE:F25P 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F25Q] CRITICAL EEEE:F25Q 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F25R] CRITICAL EEEE:F25R 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F25T] CRITICAL EEEE:F25T 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F25V] CRITICAL EEEE:F25V 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F25W] CRITICAL EEEE:F25W 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F25Y] CRITICAL EEEE:F25Y 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F27Q] CRITICAL EEEE:F27Q 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F27R] CRITICAL EEEE:F27R 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F27T] CRITICAL EEEE:F27T 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F27V] CRITICAL EEEE:F27V 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F27W] CRITICAL EEEE:F27W 825-7670 LBL,P/N LABEL,PCB,28MM X MM [EEEE_F27Y] CRITICAL EEEE:F27Y D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C 639-3795 PCBA,MLB,2.0GHZ,EL 4GB,J13 J13_CMNPTS,EEEE:F27T,CPU:2.0GHZ,DDR3:ELPIDA_4GB C B B A Sub BOM PART NUMBER SYNC_MASTER=J30_MLB SYNC_DATE=07/27/2011 PAGE TITLE QTY DESCRIPTION REFERENCE DES CRITICAL Revision History BOM OPTION 085-3939 J13 MLB DEVELOPMENT DEVEL CRITICAL DEVEL_BOM 607-9090 CMN PTS,PCBA,MLB,J13 CMNPTS CRITICAL J13_CMNPTS DRAWING NUMBER Apple Inc 051-9277 REVISION 2.8.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE OF 109 SHEET OF 73 SIZE D A J13 BOM GROUPS Module Parts TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS J13_COMMON ALTERNATE,COMMON,J13_MISC,J13_DEBUG:ENG,J13_PROGPARTS,USBHUB2514B,EDP:YES,PCH_C1 J13_MISC CPUMEM_SLG:NO,HUB_3NONREM,TBT,MPM5:YES,PP5V5_DCIN:NO,TPAD_PCH:NO,SKIP_5V3V3:INAUDIBLE,BTPWR:S4,TBTHV:P15V,LVDDR3_HW:YES,AXG_ACOUSTIC:NO PART NUMBER TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM J13_PROGPARTS BOOTROM_PROG,SMC_PROG,TBTROM:PROG DESCRIPTION REFERENCE DES 337S4197 IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB U1000 CRITICAL CPU:1.5GHZ 337S4299 QTY IVB,QC55,QS,L0,1.7,17W,2+2,1.0,3M,ULVBGA U1000 CRITICAL CRITICAL BOM OPTION CPU:1.7GHZ 337S4298 IVB,QC54,QS,L0,1.8,17W,2+2,1.1,3M,ULVBGA U1000 CRITICAL 337S4296 IVB,QC52,QS,L0,2.0,17W,2+2,1.1,4M,ULVBGA U1000 CRITICAL CPU:2.0GHZ 337S4198 IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB U1000 CRITICAL CPU:1.5GHZTDP 337S4236 IVB,QBQF,ES2,K0,1.7,17W,2+2,1.0,4M,ULV,TDP U1000 CRITICAL CPU:1.7GHZTDP 337S4165 IC,PCH,PPT-MB,SFF,ES1 U1800 CRITICAL PCH_ES1 TABLE_BOMGROUP_ITEM J13_DEVEL:ENG ALTERNATE,BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG J13_DEVEL:PVT LPCPLUS,XDP_CONN CPU:1.8GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D J13_DEBUG:ENG DEVEL_BOM,MOJO:YES,XDP J13_DEBUG:PVT DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD J13_DEBUG:PROD BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM DDR3:HYNIX_4GB RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB DDR3:HYNIX_8GB RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB 337S4180 IC,PCH,PPT-MB,SFF,ES2,B0 U1800 CRITICAL PCH_ES2 337S4235 IC,PCH,PPT-MB,SFF,P-QS,C0 U1800 CRITICAL PCH_C0 337S4275 IC,PCH,PPT-MB,QS77,C1,QS U1800 CRITICAL PCH_C1 338S1047 IC,TBT,CR-4C,ES1,288 FCBGA,12X12MM U3600 CRITICAL TBT 333S0622 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FPGA U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0622 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0622 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FGBA U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0622 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0625 IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:HYNIX_8GB DRAM_TYPE:HYNIX_8GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM DDR3:SAMSUNG_4GB RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB TABLE_BOMGROUP_ITEM DDR3:SAMSUNG_8GB RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB TABLE_BOMGROUP_ITEM DDR3:ELPIDA_8GB RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB TABLE_BOMGROUP_ITEM DDR3:ELPIDA_4GB RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB Programmable Parts PART NUMBER C QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 335S0865 IC,SERIAL SPI EEPROM,256KBIT,20MHZ,MLP8 U3690 CRITICAL TBTROM:BLANK 333S0625 IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FPGA U3000,U3010,U3020,U3030 CRITICAL 341S3475 IC,EEPROM,CR,V24.1,J11/J13 U3690 CRITICAL TBTROM:PROG 333S0625 IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FGBA U3100,U3110,U3120,U3130 CRITICAL 338S1098 IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA U4900 CRITICAL SMC_BLANK 333S0625 IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:HYNIX_8GB 338S1065 IC,SMC12,40MHZ/50DMIPS MCU, 9X9,157BGA U4900 CRITICAL SMC_BLANK 333S0623 IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:SAMSUNG_4GB 341S3433 IC,SMC,V2.1A43,Proto1B,J13 U4900 CRITICAL SMC_PROG 333S0623 IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:SAMSUNG_4GB 335S0809 64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix U6100 CRITICAL BOOTROM_BLANK 333S0623 IC,SDRAM,2GBIT,DDR3-1600,78P FGBA,D-DIE U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:SAMSUNG_4GB 335S0803 64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx U6100 CRITICAL BOOTROM_BLANK 333S0623 IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:SAMSUNG_4GB 341S3482 IC,EFI ROM,PROTO1B,J13 J11 U6100 CRITICAL BOOTROM_PROG 333S0642 IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:SAMSUNG_8GB 333S0642 IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:SAMSUNG_8GB 333S0642 IC,SDRAM,4GBIT,DDR3-1600,78P FGBA,C-DIE U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:SAMSUNG_8GB 333S0642 IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:SAMSUNG_8GB 333S0629 IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:ELPIDA_8GB 333S0629 IC,SDRAM,4GBIT,DDR3L-1600,REV B.78P FBGA U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:ELPIDA_8GB 333S0629 IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FGBA U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:ELPIDA_8GB 333S0629 IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:ELPIDA_8GB 333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:ELPIDA_4GB 333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D.78P FBGA U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:ELPIDA_4GB 333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FGBA U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:ELPIDA_4GB 333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:ELPIDA_4GB Alternate Parts TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES DRAM_TYPE:HYNIX_8GB C COMMENTS: TABLE_ALT_ITEM 376S0855 376S0613 ALL Diodes alt to Toshiba TABLE_ALT_ITEM 376S0977 376S0859 ALL Diodes alt to Toshiba 376S0972 376S0612 ALL Rohm alt to Toshiba 138S0676 138S0691 ALL Murata alt to Samsung 371S0709 371S0652 ALL NXP alt to NXP TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM 138S0671 138S0673 ALL Taiyo alt to Murata TABLE_ALT_ITEM 376S0790 376S0928 ALL TI alt to Fairchild 152S1462 152S1295 ALL Toko alt for NEC inductor 152S1085 152S1307 ALL Toko alt for Cyntec 138S0703 138S0648 ALL Murata alt to Taiyo Yuden 138S0684 138S0660 ALL Murata alt to Taiyo Yuden 152S1493 152S1300 ALL Coilcraft alt to Murata 353S3238 353S1428 ALL Intersil alt to OPA2333 372S0186 372S0185 ALL NXP alt to Diodes TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM B B TABLE_ALT_ITEM TABLE_ALT_ITEM 353S2929 IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28 U7000 CRITICAL 946-3115 MLB,DYMAX UV EB 0.22GRAM,K21 GLUE CRITICAL TABLE_ALT_ITEM TABLE_ALT_ITEM 376S1053 376S0604 ALL 376S0855 376S0613 ALL Diodes alt to Toshiba 376S0903 376S0796 ALL Fairchild alt to Siliconix 197S0431 197S0432 ALL Epson alt to NDK Diodes alt to Fairchild PD Module Parts TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM DRAM CFG CHART TABLE_ALT_ITEM 337S4198 337S4197 ALL TDP 1.5GHZ alt to Nominal TABLE_ALT_ITEM 337S4236 337S4196 ALL VENDOR CFG CFG TDP 1.7GHZ alt to Nominal TABLE_ALT_ITEM 371S0713 371S0558 ALL Diodes alt to ST Micro HYNIX 128S0333 998-4435 ALL Sanyo alt to Kemet 998-4435 ALL Sanyo alt to POS caps TABLE_ALT_ITEM SAMSUNG MICRON ELPIDA 1 TABLE_ALT_ITEM 998-4715 998-4435 ALL CAN,T29,J11/J13 TBTFENCE CRITICAL 806-3215 CAN,COVER,T29,J11/J13 TBTCOVER CRITICAL 806-3214 CAN,TOPSIDE,J11/J13 TBTTOPSIDE_1P CRITICAL 806-3706 CAN,TOPSIDE_2Piece_Cover,J11/J13 TBTTOPSIDE_2P_COVER CRITICAL 806-3705 CAN,TOPSIDE_2Piece_Fence,J11/J13 TBTTOPSIDE_2P_FENCE CRITICAL 806-3216 CAN,MDP,J11/J13 MDPCAN CRITICAL 806-3083 SHLD,USB,MLB,J11/J13 USBCAN CRITICAL 806-2377 K78, mDP Spring MDPSPRING CRITICAL TABLE_ALT_ITEM 128S0357 806-3142 Kemet_Rect alt to POS caps NOSTUFF TABLE_ALT_ITEM 998-4716 998-4435 ALL Kemet_.0045 Flute alt to POS caps A SIZE CFG DIE REV SYNC_MASTER=J30_MLB CFG SYNC_DATE=07/27/2011 PAGE TITLE BOM Configuration 4GB 8GB A B DRAWING NUMBER Apple Inc NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9277 REVISION 2.8.0 R BRANCH PAGE OF 109 SHEET OF 73 SIZE D A FUNC_TEST (Need TPs) PP3V3_S0_SSD_FLT SATA_SSD_D2R_P SATA_SSD_D2R_N SMC_OOB1_RX_L SMC_OOB1_TX_L PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N PCIE_SSD_R2D_P PCIE_SSD_R2D_N PCIE_SSD_D2R_P PCIE_SSD_D2R_N SATA_SSD_R2D_N SATA_SSD_R2D_P SSD_CLKREQ_L SATA_PCIE_SEL SSD_P3V3S0_EN SSD_RESET_L (Need to add GND TPs) TRUE J4001: AirPort / BT Connector TRUE TRUE PP3V3_S3RS4_BT_F TRUE TRUE TRUE TRUE TRUE D TRUE TRUE TRUE TRUE TRUE TRUE J5600: Fan Connector (Need TPs) 37 42 TRUE 37 41 42 TRUE 37 69 TRUE FUNC_TEST TRUE I624 TRUE 16 37 69 16 37 69 TRUE 17 37 TRUE 37 TRUE 37 TRUE 37 TRUE TRUE TRUE TRUE 48 48 48 J5700: IPD Flex Connector 16 37 69 37 68 37 68 TRUE J5715: KB BKLT CONNECTOR TRUE =PP5V_S0_FAN FAN_RT_TACH FAN_RT_PWM 16 37 69 TRUE I623 FUNC_TEST I626 TRUE (Need to add GND TP) 37 69 (Need to add GND TPs) I627 TRUE FUNC_TEST PP3V3_WLAN_F WIFI_EVENT_L PCIE_AP_R2D_N PCIE_AP_R2D_P PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P USB_BT_CONN_P USB_BT_CONN_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_WAKE_L AP_RESET_CONN_L AP_CLKREQ_Q_L TRUE PP3V3_TPAD_CONN PP5V_TPAD_FILT =PP3V42_G3H_TPAD USB_TPAD_CONN_P USB_TPAD_CONN_N =I2C_TPAD_SDA =I2C_TPAD_SCL SMC_ONOFF_L SMC_LID SMC_TPAD_RST_L SMC_PME_S4_WAKE_L 49 TRUE TRUE TRUE C TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I671 TRUE I672 TRUE I673 TRUE I674 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE =PP3V42_G3H_ONEWIRE =PP3V3_S0_AUDIO =PP3V3R1V5_S0_AUDIO SYS_ONEWIRE SMC_BC_ACOK =USB_PWR_EN SMC_LID =I2C_LIO_SDA =I2C_LIO_SCL =I2C_MIKEY_SCL =I2C_MIKEY_SDA AUD_IPHS_SWITCH_EN AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L AUD_GPIO_3 SPKRAMP_INR_N SPKRAMP_INR_P USB_EXTB_N USB_EXTB_P USB3_EXTB_TX_C_N USB3_EXTB_TX_C_P USB3_EXTB_RX_RC_N USB3_EXTB_RX_RC_P USB_CAMERA_N USB_CAMERA_P HDA_SDOUT HDA_BIT_CLK HDA_SDIN0 USB_EXTB_OC_L HDA_RST_L HDA_SYNC 40 TRUE TRUE TRUE TRUE 40 (Need TPs) TRUE 40 41 TRUE 40 41 42 TRUE 39 40 62 TRUE 40 41 42 49 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE A TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 49 68 68 44 49 44 49 I681 TRUE I683 TRUE I684 TRUE I682 TRUE 38 68 38 41 38 41 42 MAKE_BASE=TRUE 16 38 66 NC_CPU_THERMDA TRUE TP_EDP_TX_P TRUE TP_EDP_TX_N TRUE TP_EDP_AUX_P TRUE TP_EDP_AUX_N TRUE TP_CPU_THERMDA MAKE_BASE=TRUE 16 38 66 NC_CPU_THERMDC 38 66 MAKE_BASE=TRUE 38 66 NC_CPU_RSVD TRUE TP_CPU_THERMDC TRUE TP_CPU_RSVD TRUE TP_CPU_RSVD D MAKE_BASE=TRUE 38 66 NC_CPU_RSVD 38 66 MAKE_BASE=TRUE TRUE NC_PEG_R2D_CP 38 68 =PEG_R2D_C_P TRUE =PEG_R2D_C_N TRUE =PEG_D2R_P TRUE =PEG_D2R_N MAKE_BASE=TRUE 38 68 NC_PEG_R2D_CN 16 38 MAKE_BASE=TRUE 38 NC_PEG_D2RP MAKE_BASE=TRUE 38 NC_PEG_D2RN 25 38 MAKE_BASE=TRUE J6900: DC-In Connector 40 41 42 49 FUNC_TEST 42 49 =PP18V5_DCIN_CONN =PP5V_S3_LIO_CONN TRUE 41 42 49 TRUE 52 (Need TPs) 52 (Need to add GND TPs) SPKRAMP_ROUT_P SPKRAMP_ROUT_N (Need to add GND TPs) NO_TEST Nets 51 52 72 51 52 72 PPVBAT_G3H_CONN =SMBUS_BATT_SCL =SMBUS_BATT_SDA SYS_DETECT_L 52 53 I667 TRUE I668 TRUE I669 TRUE I670 TRUE 44 52 TP_CRT_IG_BLUE 17 TP_CRT_IG_GREEN 17 TP_CRT_IG_RED 44 52 52 17 TP_CRT_IG_HSYNC 17 TP_CRT_IG_VSYNC FUNC_TEST TRUE TRUE 40 51 72 TRUE 40 51 72 TRUE 24 40 68 TRUE 24 40 68 TRUE 40 68 TRUE 40 68 TRUE 40 68 TRUE 40 68 TRUE 18 40 68 TRUE 18 40 68 TRUE 16 40 69 TRUE 16 40 69 TRUE 16 40 69 TRUE TRUE 16 40 69 54 TP_PCIE_CLK100M_PE5P 54 TP_PCIE_CLK100M_PE6N 54 TP_PCIE_CLK100M_PE6P PPVOUT_SW_LCDBKLT PP3V3_SW_LCD I2C_TCON_SDA_R I2C_TCON_SCL_R LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1 DP_INT_HPD_CONN DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P DP_INT_ML_F_P DP_INT_ML_F_N DP_INT_ML_F_P DP_INT_ML_F_N TP_PSOC_P1_3 NC_CRT_IG_GREEN TP_SATA_B_D2RN NC_CRT_IG_RED TP_SATA_B_D2RP TP_SATA_B_R2D_CN J9000: Internal DP Connector TRUE TP_PCIE_CLK100M_PE5N NC_CRT_IG_BLUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_CRT_IG_DDC_DATA 40 51 TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE7P 17 17 18 40 TP_PCIE_CLK100M_PE4N 16 NO_TEST 40 44 18 40 16 54 (Need TPs) TP_CRT_IG_DDC_CLK 25 40 VCCSAS0_SREF VCCSAS0_SET1_R VCCSAS0_SET0 VCCSAS0_SET1 TP_PCIE_CLK100M_PE7N 17 40 44 63 65 63 (Need TPs) (Need TPs) 63 TP_SATA_B_R2D_CP NC_CRT_IG_DDC_DATA NC_CRT_IG_HSYNC TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_CRT_IG_VSYNC NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_DATA TRUE MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUE MAKE_BASE=TRUE TP_LVDS_IG_CTRL_DATA 63 NC_CRT_IG_DDC_CLK TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_LVDS_IG_CTRL_CLK TP_PCH_LVDS_VBG 63 65 63 65 63 65 16 TP_HDA_SDIN1 63 65 16 TP_HDA_SDIN2 63 65 16 TP_HDA_SDIN3 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 16 TP_SATA_D_D2RN 16 TP_SATA_D_D2RP 16 TP_SATA_D_R2D_CN 16 TP_SATA_D_R2D_CP 16 TP_SATA_E_D2RN 16 TP_SATA_E_D2RP 16 TP_SATA_E_R2D_CN 16 TP_SATA_E_R2D_CP 16 TP_SATA_F_D2RN NC_HDA_SDIN1 16 TP_SATA_F_D2RP NC_HDA_SDIN2 16 TP_SATA_F_R2D_CN NC_HDA_SDIN3 16 TP_SATA_F_R2D_CP 63 18 TP_PCI_PME_L 18 TP_PCI_CLK33M_OUT3 63 66 33 33 33 33 33 =PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS LPC_AD SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO TP_SMC_TRST_L TP_SMC_MD1 SMC_TX_L LPC_CLK33M_LPCPLUS SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT SMC_RX_L LPCPLUS_GPIO 43 43 16 41 43 69 43 43 16 41 43 69 17 41 43 41 42 43 25 43 69 41 42 43 43 43 41 42 43 25 43 69 19 43 50 43 43 16 41 43 17 25 41 43 41 42 43 41 42 43 41 42 43 53 42 43 41 42 43 19 43 TRUE I629 TRUE I630 TRUE I631 TRUE I632 TRUE I633 TRUE I634 TRUE I636 TRUE I635 TRUE I638 TRUE I637 TRUE I639 TRUE I641 TRUE I640 TRUE I643 TRUE I642 TRUE I644 TRUE I646 TRUE I645 TRUE I648 TRUE I647 TRUE I649 TRUE I650 TRUE I651 TRUE I653 TRUE I652 TRUE I654 TRUE I655 TRUE I657 TRUE I656 TRUE I685 I686 I687 I688 I689 I690 NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_B_D2RN NC_SATA_B_D2RP C NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP NC_SATA_F_D2RN TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP TRUE MAKE_BASE=TRUE NC_PCH_TP18 TP_PCH_TP17 TRUE MAKE_BASE=TRUE NC_PCH_TP17 TP_PCH_TP16 TRUE MAKE_BASE=TRUE NC_PCH_TP16 TP_PCH_TP15 TRUE MAKE_BASE=TRUE NC_PCH_TP15 TP_PCH_TP14 TRUE MAKE_BASE=TRUE NC_PCH_TP14 TP_PCH_TP13 TRUE MAKE_BASE=TRUE NC_PCH_TP13 TP_PCH_TP12 TRUE MAKE_BASE=TRUE TP_PCH_TP10 TRUE MAKE_BASE=TRUE NC_PCH_TP10 TP_PCH_TP9 TRUE MAKE_BASE=TRUE NC_PCH_TP9 52 TP_PCH_TP8 TRUE MAKE_BASE=TRUE NC_PCH_TP8 36 TP_PCH_TP7 TRUE MAKE_BASE=TRUE NC_PCH_TP7 XDP_PCH_AP_PWR_EN TP_PCH_TP6 TRUE MAKE_BASE=TRUE NC_PCH_TP6 XDP_PCH_USB_HUB_SOFT_RST_L 16 TP_CLINK_CLK 16 TP_CLINK_DATA 66 66 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_CLINK_RESET_L 16 16 TP_PCIE_CLK100M_PEBN 16 TP_PCIE_CLK100M_PEBP NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L NC_PCIE_CLK100M_PEBN TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE PPBUS_G3H PPVIN_SW_TBTBST PPBUS_S5_HS_COMPUTING_ISNS PPDCIN_G3H PP3V42_G3H PPVRTC_G3H PP5V_S5 PP5V_SUS PP3V3_S5 PP3V3_SUS PP3V3_S3 PP1V8_S0 PP3V3_S0 PP1V5_S3 PP1V5_S3RS0 PP1V5_S0 PP1V05_S0 PPVTTDDR_S3 PP0V75_S0_DDRVTT PPVCCSA_S0_CPU PP1V05_SUS PP15V_TBT PP3V3_TBTLC PP1V05_TBTLC PP1V05_S0_PCH_VCCADPLL PPVCORE_S0_CPU PPVCORE_S0_AXG PP1V5_S3_CPU_VCCDQ PP1V05_S0_CPU_VCCPQE PP1V8_S0_CPU_VCCPLL_R PP1V05_TBTCIO PPBUS_S5_HS_OTHER_ISNS PPDCIN_G3H_ISOL PP5V_S3 PP5V_S0 PP3V3_S4 I593 TRUE I592 TRUE I595 TRUE TP_PCH_TP5 TRUE MAKE_BASE=TRUE NC_PCH_TP5 XDP_PCH_SDCONN_STATE_RST_L TP_PCH_TP4 TRUE MAKE_BASE=TRUE NC_PCH_TP4 I594 TRUE XDP_PCH_ENET_PWR_EN TP_PCH_TP3 TRUE MAKE_BASE=TRUE NC_PCH_TP3 I596 TRUE XDP_PCH_SDCONN_DET_L TP_PCH_TP2 TRUE MAKE_BASE=TRUE I597 TRUE XDP_PCH_S5_PWRGD 23 TP_PCH_TP1 TRUE MAKE_BASE=TRUE 72 I598 TRUE XDP_PCH_PWRBTN_L 23 I599 TRUE XDP_PCH_ISOLATE_CPU_MEM_L I600 TRUE XDP_FW_CLKREQ_L I601 TRUE XDP_AP_CLKREQ_L TRUE XDP_PCH_AUD_IPHS_SWITCH_EN 7 72 I602 67 67 7 17 TP_SDVO_TVCLKINN 17 TP_SDVO_TVCLKINP 7 17 TP_SDVO_STALLN 17 TP_SDVO_STALLP 7 17 TP_SDVO_INTN 17 TP_SDVO_INTP 36 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_TVCLKINN TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_STALLN TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_INTN 23 TP_XDP_PCH_OBSFN_A 23 TP_XDP_PCH_OBSFN_B 23 TP_XDPPCH_HOOK2 23 TP_XDPPCH_HOOK3 23 TP_XDP_PCH_OBSFN_D 23 TP_XDP_PCH_HOOK4 23 TP_XDP_PCH_HOOK5 16 TP_PCH_GPIO64_CLKOUTFLEX0 16 TP_PCH_GPIO65_CLKOUTFLEX1 16 TP_PCH_GPIO66_CLKOUTFLEX2 16 TP_PCH_GPIO67_CLKOUTFLEX3 7 7 B NC_PCH_TP2 NC_PCH_TP1 PCH_VSS_NCTF TRUE I500 I566 PCH_VSS_NCTF TRUE PCH_VSS_NCTF PCH_VSS_NCTF TRUE TRUE I499 I567 I501 PCH_VSS_NCTF I568 PCH_VSS_NCTF TRUE TRUE I502 TRUE PCH_VSS_NCTF I503 TRUE PCH_VSS_NCTF I504 TRUE PCH_VSS_NCTF I505 TRUE PCH_VSS_NCTF I506 TRUE PCH_VSS_NCTF PCH_VSS_NCTF I570 TRUE I571 TRUE PCH_VSS_NCTF I569 TRUE PCH_VSS_NCTF NC_SDVO_TVCLKINP NC_SDVO_STALLP 8 TP_LVDS_IG_B_CLKN TRUE MAKE_BASE=TRUE TRUE TP_LVDS_IG_B_CLKP MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_LVDS_IG_BKL_PWM NC_SDVO_INTP SMC_BS_ALRT_L TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_OBSFN_A TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_PCH_GPIO64_CLKOUTFLEX0 NC_TP_XDP_PCH_OBSFN_B NC_LVDS_IG_B_CLKN NC_LVDS_IG_B_CLKP NC_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE NC_PCH_TP12 NC_PCIE_CLK100M_PEBP (Need to add 27 GND TPs) NC_SATA_D_D2RN NC_PCIE_CLK100M_PE5N TP_PCH_TP18 63 66 (Need to add GND TPs) I628 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4P NC_PCI_CLK33M_OUT3 63 66 Misc Voltages & Control Signals 33 NC_PCIE_CLK100M_PE4N NC_PCI_PME_L TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 63 66 FUNC_TEST PP3V3_SW_SD_PWR SD_CLK SD_CMD SD_D SD_CD_L SD_WP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 63 65 16 40 69 (Need to add GND TPs) 38 68 41 42 49 40 44 FUNC_TEST TRUE TRUE I676 TRUE (Need to add GND TPs near J6950 and for shield) 40 44 J5100: LPC+SPI Connector TRUE I675 FUNC_TEST 40 (Need to add GND TPs) TRUE I677 TRUE J6950: Battery Connector FUNC_TEST TRUE TRUE POWER SIGNALS J4800: SD Card Connector TRUE TRUE I678 TRUE (Need to add GND TPs) B TRUE I679 NC_EDP_TXP MAKE_BASE=TRUE NC_EDP_TXN MAKE_BASE=TRUE NC_EDP_AUXP MAKE_BASE=TRUE NC_EDP_AUXN 38 FUNC_TEST TRUE TRUE TRUE I680 49 FUNC_TEST TRUE I658 J6903: Speaker Connector 49 (Need to add GND TP) TRUE TRUE 49 J4700: LIO Connector TRUE I659 (Need to add GND TPs) KBDLED_FB KBDLED_ANODE J4501: SATA SSD Connector Functional Test Points FUNC_TEST NC_SMC_BS_ALRT_L SYNC_MASTER=K21_MLB NC_TP_XDPPCH_HOOK2 Functional Test / No Test NC_TP_XDPPCH_HOOK3 DRAWING NUMBER NC_TP_XDP_PCH_OBSFN_D Apple Inc NC_TP_XDP_PCH_HOOK4 NC_TP_XDP_PCH_HOOK5 NC_PCH_GPIO65_CLKOUTFLEX1 NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3 SYNC_DATE=07/29/2011 PAGE TITLE 051-9277 REVISION 2.8.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE OF 109 SHEET OF 73 SIZE D A "G3Hot" (Always-Present) Rails 53 =PPBUS_G3H PPBUS_G3H 52 55 =PP3V3_S5_REG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE 36 PPVIN_SW_TBTBST VOLTAGE=12.8V PP3V3_S5 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM =PPBUS_S0_LCDBKLT =PPBUS_S0_VSENSE =PPVIN_SW_TBTBST =PPVIN_S5_HS_COMPUTING_ISNS_R =PPVIN_S5_HS_OTHER_ISNS_R 46 PPBUS_S5_HS_OTHER_ISNS 45 36 =PPVIN_S5_HS_OTHER_ISNS D =PPVIN_S5_P5VP3V3 =PPVIN_S5_HS_COMPUTING_ISNS 55 PPBUS_S5_HS_COMPUTING_ISNS TBT Rails (off when no cable) 60 61 =PP1V8_S0_REG 61 26 52 =PP18V5_DCIN_CONN 56 61 PPDCIN_G3H 42 20 22 25 62 62 56 =PPDDR_S3_REG =PP18V5_DCIN_ISOL 61 =PPDCIN_S5_CHGR 53 PPDCIN_G3H_ISOL =PP3V3_SUS_FET 61 61 =PPDCIN_S5_CHGR_ISOL =PPDCIN_S5_VSENSE 45 C 52 =PP3V42_G3H_REG PP3V42_G3H =PPVRTC_G3_OUT 61 =PP3V3_S3_FET 39 49 42 25 16 17 20 61 =PP5V_SUS_FET PP5V_SUS 61 61 =PP3V3_S0_FET MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V MAKE_BASE=TRUE =PP5V_SUS_PCH 55 =PP5V_S3_REG PP5V_S3 22 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG =PP5V_S3_MEMRESET =PP5V_S3_P5VS0FET =PP5V_S3_RTUSB =PP5V_S3_LIO_CONN 61 =PP5V_S0_FET PP5V_S0 51 56 26 61 39 52 =PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN =PP5V_S0_LPCPLUS =PP5V_S0_VCCSA =PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_KBDLED 65 57 59 48 43 54 22 25 62 49 6 67 =PP1V5_S0_REG 36 27 28 32 34 35 36 16 19 PP1V05_TBTLC =PP1V05_TBTLC_FET 29 30 32 61 56 31 36 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_TBTCIO_FET =PP1V05_TBTLC_RTR 35 PP1V05_TBTCIO MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 67 =PP1V05_TBTCIO_RTR 10 12 15 26 35 1V05 S0 LDO 62 PP1V5_S0 25 26 PP1V05_S0_PCH_VCCADPLL =PP1V05_S0_LDO MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_S0_PCH_VCCADPLL 22 MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE 60 42 =PP3V3R1V5_S0_AUDIO =PP3V3R1V5_S0_PCH_VCCSUSHDA 20 22 16 17 18 19 40 Chipset "VCore" Rails 20 22 25 C 50 20 22 58 =PPVTT_S3_DDR_BUF PPVTTDDR_S3 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 56 =PPVTT_S0_DDR_LDO =PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE PP0V75_S0_DDRVTT 58 =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP 37 33 26 =PPVCORE_S0_AXG_REG 44 54 =PPVCCSA_S0_REG 26 PPVCCSA_S0_CPU 31 =PPVCORE_S0_CPU_VCCAXG =PPGFXVCORE_S0_VSENSE 12 15 45 15 12 =PPVCCSA_S0_CPU 12 15 =PPVCCSA_S0_VSENSE 45 =PP1V5_S3_CPU_VCCDQ PP1V5_S3_CPU_VCCDQ MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 37 46 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 32 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.9V MAKE_BASE=TRUE 24 45 PPVCORE_S0_AXG 32 44 24 12 14 MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE 6 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE 34 35 36 14 12 =PP1V05_S0_CPU_VCCPQE PP1V05_S0_CPU_VCCPQE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 18 25 46 52 24 60 =PP1V05_SUS_LDO 72 VOLTAGE=3.3V MAKE_BASE=TRUE PP1V05_SUS 14 12 =PP1V8_S0_CPU_VCCPLL_R PP1V8_S0_CPU_VCCPLL_R MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 63 PP3V3_S0 =PP3V3_S0_SSD =PP3V3_S0_HDDISNS =PP3V3_S0_VMON =PP3V3_S0_P1V5S0 =PP3V3_S0_TBTPWRCTL =PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS =PP3V3_S0_XDP =PP3V3_S0_BKLTISNS =PP3V3_S0_SYSCLKGEN =PP3V3_S0_SATAMUX =PP3V3_S0_SAISNS =PP3V3_S0_3V3S0ISNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_STRAPS MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE A 60 D =PPVDDIO_TBT_CLK =PP3V3_TBTLC_RTR =PP3V3_TBT_PCH_GPIO 22 62 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 60 60 VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S0_CPUVCCIOISNS =PP3V3_S0_AUDIO =PP3V3_S0_BKL_VDDIO =PP3V3_S0_HS_COMPUTING_ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_DP_DDC =PP3V3_S0_FAN =PP3V3_S0_P3V3TBTFET =PP3V3_S0_P1V8S0 =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_HS_OTHER_ISNS =PP3V3_S0_PCH_VCC3_3 =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC 49 PP3V3_TBTLC =PP3V3_TBTLC_FET 25 20 22 64 PP3V3_S3 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM 61 36 20 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S3_USB_HUB =PP3V3_S3_USB_RESET =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_WLANISNS =PP3V3_S3_BMON_ISNS =PP3V3_S3_PCH_GPIO =PP3V3_S3_1V5S3ISNS =PP3V3_S3_DBGLEDS =PP3V3_S3_USBMUX =PP3V3_S3_LCD 40 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE B PP3V3_SW_TBTAPWR PP1V5_S3RS0 =PP1V5_S3_CPU_VCCDDR =PP1V5_S3RS0_VMON VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S3_BT =PP3V3_S3_CARDREADER =PP3V3_S3_MEMRESET =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMBUS_SMC_MGMT 44 =PPVRTC_G3_PCH =PP5V_S5_P1V5DDRFET =PP5V_S5_P5VSUSFET =PP5V_S5_TPAD =PP1V5_S3RS0_FET 62 PPVRTC_G3H PP5V_S5 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM 53 5V Rails =PP5V_S5_LDO 37 =PP3V3_S4_TBT 41 42 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE 55 61 49 PP3V3_SUS MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM 43 60 36 42 64 19 20 22 33 56 31 =PP3V3_S4_TBTAPWR =PP3V3_S5_LPCPLUS =PP3V3_S5_SMC =PP3V42_G3H_CHGR =PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF =PPVBAT_G3H_SYSCLK =PP3V42_G3H_ONEWIRE 25 6 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.42V MAKE_BASE=TRUE =PPHV_SW_DPAPWRSW =PPHV_SW_TBTAPWRSW VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_GPIO =PP3V3_SUS_PCH =PP3V3_SUS_PWRCTL =PP3V3_SUS_P1V05SUSLDO =PP3V3_SUS_SMC =PP3V3_SUS_PCH_VCC_SPI =PP3V3_SUS_PCH_GPIO =PP3V3_SUS_ROM =PP3V3_SUS_PCH_VCCSUS_USB 53 =PP1V8_S0_PCH_VCC_DFTERM =PP1V8_S0_P1V05S0LDO =PP1V8R1V5_S0_PCH_VCCVRM =PPVDDIO_S0_SBCLK =PP1V8_S0_P1V5S0 PP1V5_S3 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=17.8V MAKE_BASE=TRUE 14 =PP1V5_S3_MEMRESET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_P1V5S3RS0_FET =PPVIN_S0_DDRREG_LDO =PPDDR_S3_MEMVREF 19 =PP3V3_S4_BT MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE PP15V_TBT =PP15V_TBT_REG MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.5V MAKE_BASE=TRUE 64 =PP3V3_S4_SD_HPD =PP3V3_S4_SMC =PP3V3_S4_TPAD 36 =PP1V8_S0_CPU_VCCPLL 25 PP3V3_S4 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 58 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE 52 =PP3V3_S4_FET 54 17 57 58 59 PP1V8_S0 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE 2A max supply MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE =PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG =PPVIN_S0_CPUVCCIOS0 =PPVIN_S0_VCCSAS0 =PPVIN_S0_CPUAXG 72 23 =PP3V3_S5_PCH_VCCDSW =PP3V3_S5_SYSCLK =PP3V3_S5_VMON =PP3V3_S5_PWRCTL =PP3V3_S4_TBTAPWRSW =PP3V3_S5_P3V3SUSFET =PP3V3_S4_P3V3S4FET =PP3V3_S5_PCH_GPIO MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S5_XDP =PP3V3_S0_P3V3S0FET =PP3V3_S3_P3V3S3FET =PP3V3_S5_CPU_VCCDDR =PP3V3_S5_PCH =PP3V3_S5_PCHPWRGD 65 1.8V/1.5V/1.2V/1.05V Rails =PP3V3_S5_SMCBATLOW 46 3.3V Rails MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE =PP1V05_SUS_PCH_JTAG 23 PP1V05_S0 B 45 40 65 59 =PPCPUVCCIO_S0_REG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE ? mA 46 =PP1V05_S0_CPU_VCCIO =PP1V05_S0_PCH =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCASW 47 48 36 60 16 22 10 12 14 16 22 20 22 17 16 22 20 22 16 17 18 19 25 36 =PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_VMON =PPVCCIO_S0_CPUIMVP =PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_PCH_VCC_DMI =PPVCCIO_S0_XDP =PPVCCIO_S0_SMC =PP1V05_S0_P1V05TBTFET 46 20 22 22 62 25 25 44 44 44 42 20 22 62 57 16 20 22 20 22 20 22 20 22 23 42 36 38 46 62 60 36 SYNC_MASTER=K21_MLB 60 SYNC_DATE=07/29/2011 PAGE TITLE Power Aliases 45 23 DRAWING NUMBER 46 Apple Inc 25 051-9277 REVISION 2.8.0 R 38 45 NOTICE OF PROPRIETARY PROPERTY: 45 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 12 22 BRANCH PAGE OF 109 SHEET OF 73 SIZE D A Unused PPT Plated Board Slot 16 IN PCIE_CLK100M_ENET_N 16 IN PCIE_CLK100M_ENET_P 16 IN PCIE_CLK100M_FW_N IN PCIE_CLK100M_FW_P IN PCIE_CLK100M_EXCARD_N 16 16 SL0900 TH-NSP SL-2.3X3.9-2.9X4.5 16 IN PCIE_CLK100M_EXCARD_P 69 16 IN PEG_CLK100M_N 69 16 IN PEG_CLK100M_P 16 IN PCIE_ENET_D2R_N IN PCIE_ENET_D2R_P 16 IN PCIE_ENET_R2D_C_N 16 IN PCIE_ENET_R2D_C_P 16 D CPU Heat Sink Mounting Bosses Z0913 Z0910 STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM 1 IN PCIE_FW_D2R_N 16 IN PCIE_FW_D2R_P 16 IN PCIE_FW_R2D_C_N 16 IN PCIE_FW_R2D_C_P 16 IN PCIE_EXCARD_D2R_N IN PCIE_EXCARD_D2R_P 16 IN PCIE_EXCARD_R2D_C_N 16 IN PCIE_EXCARD_R2D_C_P 16 Z0911 Z0912 STDOFF-4.5OD1.8H-SM NC_PCIE_CLK100M_ENET_N MAKE_BASE=TRUE NC_PCIE_CLK100M_ENET_P MAKE_BASE=TRUE NC_PCIE_CLK100M_FW_N MAKE_BASE=TRUE NC_PCIE_CLK100M_FW_P MAKE_BASE=TRUE NC_PCIE_CLK100M_EXCARD_N MAKE_BASE=TRUE NC_PCIE_CLK100M_EXCARD_P MAKE_BASE=TRUE NC_PEG_CLK100M_N MAKE_BASE=TRUE NC_PEG_CLK100M_P MAKE_BASE=TRUE NC_PCIE_ENET_D2R_N MAKE_BASE=TRUE NC_PCIE_ENET_D2R_P MAKE_BASE=TRUE NC_PCIE_ENET_R2D_C_N MAKE_BASE=TRUE NC_PCIE_ENET_R2D_C_P MAKE_BASE=TRUE NC_PCIE_FW_D2R_N MAKE_BASE=TRUE NC_PCIE_FW_D2R_P MAKE_BASE=TRUE NC_PCIE_FW_R2D_C_N MAKE_BASE=TRUE NC_PCIE_FW_R2D_C_P MAKE_BASE=TRUE NC_PCIE_EXCARD_D2R_N MAKE_BASE=TRUE NC_PCIE_EXCARD_D2R_P MAKE_BASE=TRUE NC_PCIE_EXCARD_R2D_C_N MAKE_BASE=TRUE NC_PCIE_EXCARD_R2D_C_P MAKE_BASE=TRUE 16 CPU signals NO_TEST=TRUE 16 NO_TEST=TRUE NO_TEST=TRUE MEMVTT_EN 26 MEM_A_CLK_P MEM_A_CLK_N 67 11 4x 860-1327 67 11 MAKE_BASE=TRUE NO_TEST=TRUE 16 NO_TEST=TRUE 16 NO_TEST=TRUE NO_TEST=TRUE MEM_B_CLK_P MEM_B_CLK_N 67 11 MAKE_BASE=TRUE Fan Boss X21 Boss Z0914 Z0915 STDOFF-4.5OD1.9H-SM STDOFF-4.5OD1.9H-SM 1 860-1327 860-1327 860-1327 5% 1/20W MF 201 NO_TEST=TRUE NO_TEST=TRUE CRITICAL NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE 17 NO_TEST=TRUE 17 ZS0906 POGO-2.0OD-3.6H-K86-K87 SM SM TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE TP_MEM_A_CLKP TP_MEM_A_CLKN 470K 1% 1/20W MF 201 TP_MEM_B_CLKP TP_MEM_B_CLKN DP_TBTSNK0_DDC_CLK 64 ENET_LOW_PWR_PCH 16 SATARDRVR_EN 16 TP_PCH_CLKOUT_DPP DPLL_REF_CLK_N MAKE_BASE=TRUE DPLL_REF_CLKN SL-1.1X0.4-1.4X0.7 470K DPLL_REF_CLK_P MAKE_BASE=TRUE DPLL_REF_CLKP 10 66 65 PPBUS_SW_LCDBKLT_PWR 10 66 72 46 OUT ISNS_LCDBKLT_P 72 46 OUT ISNS_LCDBKLT_N OUT 0.5% 1W MF 0612-1 1% 1/20W MF 201 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 17 DP_TBTSNK1_HPD 17 DPA_IG_HPD DP_TBTSNK0_HPD DP_TBTSNK0_AUXCH_C_P DPA_IG_AUX_CH_P 69 34 34 69 D 34 69 34 69 34 69 34 69 34 69 34 69 34 34 17 DPA_IG_AUX_CH_N DP_TBTSNK0_AUXCH_C_N DP_TBTSNK1_AUXCH_C_P 17 DPB_IG_AUX_CH_P 17 DPB_IG_AUX_CH_N 17 TP_DP_IG_C_MLP 17 TP_DP_IG_C_MLN 17 TP_DP_IG_B_MLP 17 TP_DP_IG_B_MLN 17 MAKE_BASE=TRUE 17 69 34 DP_TBTSNK1_AUXCH_C_N 69 34 DP_TBTSNK1_ML_C_P 69 34 DP_TBTSNK1_ML_C_N 69 34 DP_TBTSNK0_ML_C_P 69 34 DP_TBTSNK0_ML_C_N 70 34 DP_TBTPB_ML_C_P NC_DP_TBTPB_ML_C_P 70 34 DP_TBTPB_ML_C_N NC_DP_TBTPB_ML_C_N MAKE_BASE=TRUE 17 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE PPBUS_SW_BKL MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=12.6V MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 65 70 34 DP_TBTPB_ML_C_P NC_DP_TBTPB_ML_C_P R0954 70 34 DP_TBTPB_ML_C_N NC_DP_TBTPB_ML_C_N 1% 1W MF 70 34 DP_TBTPB_AUXCH_C_P NC_DP_TBTPB_AUXCH_C_P IN USB_EXTC_P OUT ISNS_HS_COMPUTING_N OUT ISNS_HS_COMPUTING_P MAKE_BASE=TRUE 0612 =PPVIN_S5_HS_COMPUTING_ISNS_R IN 70 34 IN USB_EXTC_N 18 IN USB3_EXTC_RX_P 18 IN USB3_EXTC_RX_N 18 IN USB3_EXTC_TX_P 18 IN USB3_EXTC_TX_N 18 IN USB3_EXTD_RX_P 18 IN USB3_EXTD_RX_N IN USB3_EXTD_TX_P MLB_RAMCFG2 IN TBT_B_R2D_C_N 70 34 IN TBT_B_R2D_C_P IN TBT_B_R2D_C_N IN TBT_B_R2D_C_P TBT_B_D2R_P 19 MLB_RAMCFG0 70 34 IN TBT_B_D2R_N 70 34 IN TBT_B_D2R_P IN TBT_B_D2R_N 5% 1/20W MF 201 NO_TEST=TRUE NC_USB3_EXTC_RX_N NO_TEST=TRUE 2 RAMCFG1:L 1RAMCFG0:L R0952 R0953 10K 10K 10K 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 2 70 34 NC_USB3_EXTC_TX_P MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE 34 NC_USB3_EXTD_RX_P MAKE_BASE=TRUE NC_USB3_EXTD_TX_P 18 IN USB_EXTD_EHCI_N 18 IN USB_EXTD_EHCI_P NO_TEST=TRUE NO_TEST=TRUE TP_LVDS_IG_B_CLKP NO_TEST=TRUE NC_TBT_B_D2R_N NO_TEST=TRUE MAKE_BASE=TRUE TBT_B_CIO_SEL 34 DP_TBTPB_HPD 34 TBT_B_CONFIG2_RC TBT_B_CONFIG1_BUF TBT_B_LSRX R0916 LVDS_IG_B_CLK_P TP_LVDS_IG_B_CLKN LVDS_IG_B_CLK_N NC_LVDS_IG_B_DATAP NO_TEST=TRUE MAKE_BASE=TRUE NC_USB_EXTD_EHCI_P MAKE_BASE=TRUE NO_TEST=TRUE NC_TBT_B_D2R_P MAKE_BASE=TRUE R0917 R0918 R0919 10K 10K 10K 10K 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 2 B R0914 10K 5% 1/20W MF 201 MAKE_BASE=TRUE NC_USB_EXTD_EHCI_N MAKE_BASE=TRUE NO_TEST=TRUE NC_TBT_B_D2R_N MAKE_BASE=TRUE MAKE_BASE=TRUE NC_USB3_EXTD_TX_N MAKE_BASE=TRUE LVDS_IG_A_DATA_P MAKE_BASE=TRUE DDRREG_PGOOD IN 61 IN 56 65 LCD_BKLT_PWM 34 NO_TEST=TRUE NC_LVDS_IG_A_DATAN P1V5S3RS0_RAMP_DONE LVDS_IG_B_DATA_N NO_TEST=TRUE NC_LVDS_IG_A_DATAP MAKE_BASE=TRUE LVDS_IG_B_DATA_P NO_TEST=TRUE NC_LVDS_IG_B_DATAN NO_TEST=TRUE MAKE_BASE=TRUE TP_P1V5S3RS0_RAMP_DONE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE USB3_EXTD_TX_N 34 LVDS Aliases NO_TEST=TRUE NC_USB3_EXTD_RX_N MAKE_BASE=TRUE NO_TEST=TRUE NC_TBT_B_D2R_P 34 NC_USB3_EXTC_TX_N MAKE_BASE=TRUE IN 2x TBT pin diodes R0951 10K NC_USB3_EXTC_RX_P MAKE_BASE=TRUE 1RAMCFG2:L NO_TEST=TRUE NC_TBT_B_R2D_C_P MAKE_BASE=TRUE IN R0950 NO_TEST=TRUE NC_TBT_B_R2D_C_N MAKE_BASE=TRUE 70 34 RAMCFG3:L NO_TEST=TRUE NC_TBT_B_R2D_C_P MAKE_BASE=TRUE MLB_RAMCFG1 NO_TEST=TRUE NC_TBT_B_R2D_C_N MAKE_BASE=TRUE 19 NC_USB_EXTC_N MAKE_BASE=TRUE NC_DP_TBTPB_AUXCH_C_N 70 34 70 34 NO_TEST=TRUE MAKE_BASE=TRUE DP_TBTPB_AUXCH_C_N MAKE_BASE=TRUE NC_USB_EXTC_P MAKE_BASE=TRUE C MAKE_BASE=TRUE 70 34 IN TBT_B_LSTX NC_TBT_B_LSTX MAKE_BASE=TRUE LVDS_IG_A_DATA_N NO_TEST=TRUE NO_TEST=TRUE LVDS_IG_BKL_PWM 17 LVDS_IG_PANEL_PWR 17 LVDS_IG_BKL_ON 17 MAKE_BASE=TRUE 63 LCD_IG_PWR_EN MAKE_BASE=TRUE 65 LCD_BKLT_EN MAKE_BASE=TRUE SATA Aliases 2x MDP Connector 2x TBT chip SMC Aliases Unused SATA ODD Signals IN SATA_ODD_R2D_C_P 16 IN SATA_ODD_R2D_C_N 16 OUT SATA_ODD_D2R_P 16 OUT SATA_ODD_D2R_N Unused SMC Signals NC_SATA_ODD_R2DCP MAKE_BASE=TRUE NO_TEST=TRUE NC_SATA_ODD_R2DCN MAKE_BASE=TRUE NO_TEST=TRUE 41 IN SMC_SYS_LED NO_TEST=TRUE 41 IN IR_RX_OUT_RC NC_SATA_ODD_D2RP MAKE_BASE=TRUE MAKE_BASE=TRUE NC_SMC_SYS_LED MAKE_BASE=TRUE NO_TEST=TRUE NC_IR_RX_OUT_RC MAKE_BASE=TRUE NC_SATA_ODD_D2RN NO_TEST=TRUE NO_TEST=TRUE SYNC_MASTER=J13_MLB_NON_POR SYNC_DATE=11/10/2011 PAGE TITLE 2x USB Connector =PEG_D2R_P IN IN =PEG_D2R_N IN =PEG_R2D_C_P IN =PEG_R2D_C_N 34 69 34 69 MAKE_BASE=TRUE SL0908 TH-NSP SL-1.1X0.4-1.4X0.7 34 69 PCIE_TBT_D2R_P PCIE_TBT_D2R_P PCIE_TBT_D2R_P PCIE_TBT_D2R_P PCIE_TBT_D2R_N PCIE_TBT_D2R_N PCIE_TBT_D2R_N PCIE_TBT_D2R_N DPB_IG_HPD 69 34 SSD PCIE Signals SL-1.1X0.4-1.4X0.7 MAKE_BASE=TRUE MLB_RAMCFG3 Unused PGOOD signal SL0907 TH-NSP 34 69 MAKE_BASE=TRUE MAKE_BASE=TRUE 1 34 69 MAKE_BASE=TRUE =PPBUS_SW_BKL =PPVIN_S5_HS_COMPUTING_ISNS 72 46 16 SL0904 TH-NSP 34 69 34 69 MAKE_BASE=TRUE 0.01 TP_DDRREG_PGOOD A MAKE_BASE=TRUE 34 69 TBT DP Ports 0.002 SL-1.1X0.45-1.4X0.75 MAKE_BASE=TRUE 34 69 MAKE_BASE=TRUE R0910 19 23 16 23 SL0906 TH-NSP SL-1.1X0.4-1.4X0.7 MAKE_BASE=TRUE PCIE_TBT_R2D_C_P PCIE_TBT_R2D_C_P PCIE_TBT_R2D_C_P PCIE_TBT_R2D_C_P PCIE_TBT_R2D_C_N PCIE_TBT_R2D_C_N PCIE_TBT_R2D_C_N PCIE_TBT_R2D_C_N MAKE_BASE=TRUE DPA_IG_DDC_DATA MAKE_BASE=TRUE MAKE_BASE=TRUE 16 CRITICAL XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH XDP_DC3_PCH_GPIO19_SATARDRVR_EN TP_PCH_CLKOUT_DPN SL0902 TH-NSP SL0905 TH-NSP 17 16 CRITICAL 18 Can Slots SL-1.1X0.45-1.4X0.75 DP_TBTSNK0_DDC_DATA MAKE_BASE=TRUE 18 17 16 870-1938 VOLTAGE=0V MIN_NECK_WIDTH=0.075MM MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE NC_PCIE_5_D2RP NC_PCIE_6_D2RP NC_PCIE_7_D2RP NC_PCIE_8_D2RP NC_PCIE_5_D2RN NC_PCIE_6_D2RN NC_PCIE_7_D2RN NC_PCIE_8_D2RN 69 34 DPA_IG_DDC_CLK MAKE_BASE=TRUE GND SL-1.1X0.4-1.4X0.7 MAKE_BASE=TRUE 72 46 Digital Ground SL0903 TH-NSP 16 DPB_IG_DDC_CLK DPB_IG_DDC_DATA DP_IG_D_CTRL_CLK DP_IG_D_CTRL_DATA MAKE_BASE=TRUE MAKE_BASE=TRUE 19 18 SL-1.1X0.4-1.4X0.7 16 MAKE_BASE=TRUE 18 5% 1/20W MF 201 16 R09241 R09251 Unused USB SL0901 TH-NSP 2.2K =PP3V3_S0_DP_DDC 19 B 16 NO_TEST=TRUE 19 870-1938 5% 1/20W MF 201 MAKE_BASE=TRUE MAKE_BASE=TRUE 1 5% 1/20W MF 201 2.2K MAKE_BASE=TRUE NO_TEST=TRUE CRITICAL ZS0905 2.2K R0923 16 USB/SD Card Pogo POGO-2.0OD-3.6H-K86-K87 R0922 NC_PCIE_5_R2D_CP NC_PCIE_6_R2D_CP NC_PCIE_7_R2D_CP NC_PCIE_8_R2D_CP NC_PCIE_5_R2D_CN NC_PCIE_6_R2D_CN NC_PCIE_7_R2D_CN NC_PCIE_8_R2D_CN MAKE_BASE=TRUE NO_TEST=TRUE EMI I/O Pogo Pins DisplayPort Pogo R0921 2.2K NO_TEST=TRUE 64 16 C R0920 NO_TEST=TRUE SSD Boss Z0905 16 NO STUFF NO STUFF MAKE_BASE=TRUE STDOFF-4.5OD1.8H-SM 16 =PP3V3_S0_DP_DDC NO_TEST=TRUE MAKE_BASE=TRUE 67 11 26 56 16 STDOFF-4.5OD1.8H-SM 16 =DDRVTT_EN MAKE_BASE=TRUE PCIE_SSD_D2R_P MAKE_BASE=TRUE PCIE_SSD_D2R_N MAKE_BASE=TRUE PCIE_SSD_R2D_C_P MAKE_BASE=TRUE PCIE_SSD_R2D_C_N MAKE_BASE=TRUE 17 OUT TP_DP_IG_D_HPD 38 66 OUT 38 66 OUT 38 66 DRAWING NUMBER MAKE_BASE=TRUE 38 66 OUT Signal Aliases DP_IG_D_HPD Apple Inc R09091 100K 5% 1/20W MF 201 051-9277 REVISION 2.8.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE OF 109 SHEET OF 73 SIZE D A NOTE: OMIT_TABLE 66 D 66 17 IN 66 17 IN 66 17 IN 66 17 IN 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 C 14 12 10 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 24.9 1% 1/20W MF 201 DMI_S2N_P DMI_S2N_P DMI_S2N_P DMI_S2N_P N3 P7 P3 P11 DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_N K1 M8 N4 R2 DMI_N2S_P DMI_N2S_P DMI_N2S_P DMI_N2S_P OUT 66 17 FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N W6 V4 Y2 AC9 FDI1_TX_0* FDI1_TX_1* FDI1_TX_2* FDI1_TX_3* FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P U6 W10 W3 AA7 FDI0_TX_0 FDI0_TX_1 FDI0_TX_2 FDI0_TX_3 FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P W7 T4 AA3 AC8 OUT OUT OUT 66 17 OUT 66 17 IN 66 17 IN FDI_FSYNC FDI_FSYNC 66 17 IN FDI_INT 66 17 IN 66 AA11 AC12 U11 FDI_LSYNC FDI_LSYNC EDP_COMP AA10 AG8 PLACE_NEAR=U1000.AF3:12.7MM 66 63 66 63 66 63 6 66 63 B 6 DMI_TX_0 DMI_TX_1 DMI_TX_2 DMI_TX_3 FDI0_TX_0* FDI0_TX_1* FDI0_TX_2* FDI0_TX_3* 66 17 IN DMI_TX_0* DMI_TX_1* DMI_TX_2* DMI_TX_3* U7 W11 W1 AA6 66 17 66 17 K3 M7 P4 T3 AD2 AF3 EDP_HPD_L AG11 DP_INT_AUX_CH_N DP_INT_AUX_CH_P AG4 AF4 BGA (1 OF 9) DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3 FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N 66 17 =PP1V05_S0_CPU_VCCIO R1030 IN IVY-BRIDGE 2C-35W FDI1_TX_0 FDI1_TX_1 FDI1_TX_2 FDI1_TX_3 FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC EDP_ICOMPO EDP_COMPIO EDP_HPD EDP_AUX* EDP_AUX DP_INT_ML_N TP_EDP_TX_N TP_EDP_TX_N TP_EDP_TX_N AC3 AC4 AE11 AE7 EDP_TX_0* EDP_TX_1* EDP_TX_2* EDP_TX_3* DP_INT_ML_P TP_EDP_TX_P TP_EDP_TX_P TP_EDP_TX_P AC1 AA4 AE10 AE6 EDP_TX_0 EDP_TX_1 EDP_TX_2 EDP_TX_3 Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating even if internal Graphics is disabled since they are shared with other interfaces NOTE: The EDP_HPD processor input is a low voltage active low signal Therefore, an inverting level shifter is required on the motherboard to convert the active high signal from Embedded DisplayPort sink device to low voltage signals for the processor (refer to latest Processor EDS for DC specifications) If HPD is disabled while eDP interface is still enabled, connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard This signal can be left as no-connect if entire eDP interface is disabled 66 23 66 23 66 23 66 23 66 23 23 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG NOSTUFF R1042 1K 66 23 CPU_CFG CPU_CFG CPU_CFG OMIT_TABLE =PP1V05_S0_CPU_VCCIO CRITICAL H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7 =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6 =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P PEG_TX_0* PEG_TX_1* PEG_TX_2* PEG_TX_3* PEG_TX_4* PEG_TX_5* PEG_TX_6* PEG_TX_7* PEG_TX_8* PEG_TX_9* PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15* G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P IN IN IN IN IN IN IN IN IN IN PLACE_NEAR=U1000.H43:50.8MM PLACE_SIDE=BOTTOM =PPVCORE_S0_CPU R1064 NOSTUFF R1070 IN IN IN IN IN IN IN IN IN Note VOLTAGE=1.05V IN Note VOLTAGE=0V IN IN IN IN IN IN IN IN IN IN IN 49.9 1% 1/16W MF-LF 402 49.9 1% 1/16W MF-LF 2 402 PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=BOTTOM Note VOLTAGE=1.25V IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Note VOLTAGE=0V NOSTUFF R1065 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 12 14 =PPVCORE_S0_CPU_VCCAXG NOSTUFF 12 15 23 66 IN 66 23 IN 66 23 IN 66 23 IN 23 IN 23 IN R1071 49.9 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 U1000 BGA (5 OF 9) RESERVED H43 VCC_VAL_SENSE K43 VSS_VAL_SENSE CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N H45 VAXG_VAL_SENSE K45 VSSAXG_VAL_SENSE TP_CPU_VCC_DIE_SENSE F48 VCC_DIE_SENSE 72 47 OUT 72 47 OUT CPU_THERMD_P CPU_THERMD_N H48 RSVD_6 K48 RSVD_7 NOTE: Intel does not recommend to use BA19 this alnalog sense due to accuracy concern.NC 2 AV19 PLACE_NEAR=U1000.K45:50.8MM NC AT21 PLACE_SIDE=BOTTOM NC BB21 NC BB19 PLACE_NEAR=U1000.K43:50.8MM NC AY21 PLACE_SIDE=BOTTOM NC BA22 NOTE: Intel validation sense lines per NC AY22 doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1 NC AU19 NC AU21 NC BD21 NC BD22 NC BD25 NC BD26 NC BG22 NC BE22 NC BG26 NC BE26 NC BF23 NC BE24 NC RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22 RSVD_23 RSVD_24 RSVD_25 RSVD_26 RSVD_27 PPCPU_MEM_VREFDQ_A PPCPU_MEM_VREFDQ_B SA_DIMM_VREFDQ BE7 SB_DIMM_VREFDQ BG7 CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N NOSTUFF 49.9 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V 10 12 14 1% 1/20W MF 201 PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8* PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15* 14 12 10 RSVD_30 RSVD_31 RSVD_32 RSVD_33 N42 NC L42 NC L45 NC L47 RSVD_34 RSVD_35 RSVD_36 RSVD_37 RSVD_38 M13 NC M14 NC U14 NC W14 NC P13 31 OUT 31 D NC NC RSVD_39 AT49NC RSVD_40 K24 NC RSVD_41 RSVD_42 RSVD_43 RSVD_44 AH2 NC AG13 NC AM14 NC AM15 NC RSVD_45 N50 NC DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 A4 TP_CPU_DC_TEST_A4 C4 CPU_DC_TEST_C4_D3 D3 D1 TP_CPU_DC_TEST_D1 A58 TP_CPU_DC_TEST_A58 A59 CPU_DC_TEST_C59_A59 C59 A61 CPU_DC_TEST_C61_A61 C61 D61 TP_CPU_DC_TEST_D61 BD61 TP_CPU_DC_TEST_BD61 BE61 CPU_DC_TEST_BE59_BE61 BE59 BG61 CPU_DC_TEST_BG59_BG61 BG59 BG58 TP_CPU_DC_TEST_BG58 BG4 TP_CPU_DC_TEST_BG4 BG3 CPU_DC_TEST_C4_BE3_BG3 BE3 BG1 CPU_DC_TEST_C4_BE1_BG1 BE1 BD1 TP_CPU_DC_TEST_BD1 C B =PP1V05_S0_CPU_VCCIO PLACE_NEAR=U1000.AG11:12.7MM R1031 1K NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF R1044 R1045 R1046 R1047 R1040 R1041 R1043 R1049 5% 402 1K 1K 5% 402 402 402 402 1K 5% 402 1K 5% 402 1/16W MF-LF EDP_HPD_L 5% 1/16W MF-LF 5% 1/20W MF 201 1K 5% 1/16W MF-LF MF-LF 1K 1/16W 1/16W MF-LF 5% 1/16W MF-LF 1K 5% 1/16W MF-LF 402 D 63 DP_INT_HPD SYNC_MASTER=J13_MLB_NON_POR Q1031 G CPU DMI/PEG/FDI/RSVD SOT-523-3 S CFG [7] :PEG DEFER TRAINING SYNC_DATE=10/17/2011 PAGE TITLE 2N7002TXG EDP:YES DRAWING NUMBER These can be Placed close to J2500 and Only for debug access Apple Inc CR SFF Intel doc #460452 Rise/Fall time 10 ms S5PGOOD_DLY 343S0497 U7941 SMC_PM_G2_EN MAKE_BASE=TRUE 62 CRITICAL VDD P3V3S5_EN MAKE_BASE=TRUE C7942 0.033UF SMC_ADAPTER_EN SMC_PM_G2_ENABLE SMC_S4_WAKESRC_EN PM_SUS_EN PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L X 1 1 1 Sleep (S3AC) 1 1 1 Sleep (S3) 1 1 Deep Sleep (S4AC) 1 0 0 Deep Sleep (S4) 1 0 0 1 0 0 Deep Sleep (S5) 0 0 Battery Off (G3HotAC) toggle 3Hz 0 0 0 Battery Off (G3Hot) 0 0 0 Deep Sleep (S5AC) NO STUFF P5V3V3_REG_EN MAKE_BASE=TRUE =P5V3V3_REG_EN OUT 55 62 OUT MAKE_BASE=TRUE THRM PAD GND 220PF 10% 25V X7R-CERM 201 MAKE_BASE=TRUE 20% 10V 41 17 IN PLACE_NEAR=U7300.16:6mm R7911 5% 1/20W MF 201 =P5VS3_EN MAKE_BASE=TRUE 55 OUT NO STUFF C7913 0.068UF R7912 5.1K 9.1K 5% 1/20W MF 201 10% 10V CERM 402 D P3V3S3_EN P5V3V3_S4_EN MAKE_BASE=TRUE =TBTAPWRSW_EN MAKE_BASE=TRUE OUT 64 =P3V3S4_EN OUT 61 NC NOSTUFF SMC_S4_WAKESRC_EN C7910 0.47UF PLACE_NEAR=Q7812.2:6mm PLACE_NEAR=U7300.16:6mm NC =P3V3S3_EN OUT 61 =DDRREG_EN OUT 56 =USB_PWR_EN OUT 39 40 MAKE_BASE=TRUE DDRREG_EN SOT891 S5_PWRGD (old name RSMRST_PWRGD) >SMC SMC >PM_DSW_PWRGD IN P5VS3_EN 74LVC1G32 PM_SLP_S5_L 402 42 41 5% 1/20W MF 201 DP S4 Power Enable U7970 PM_SLP_S5_L:100K pull down on PCH page 0.1uF 41 CERM C7941 PM_SLP_S4_L IN PLACE_NEAR=Q7812.2:6mm C7970 S5_PWRGD (OD,IPU) R7913 49 26 17 41 37 =PP3V3_S5_PWRCTL PLACE_NEAR=U7940.1:2.3mm OUT_B DLY 3.3V,5V S3 ENABLE State Run (S0) =P3V3S5_ENOUT 10% 16V X5R 402 NC D 41 C7940 Mobile System Power State Table =PP3V42_G3H_PWRCTL Internal pull-ups 100K +/- 20% 62 C7912 0.47UF 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 R7915 MAKE_BASE=TRUE 5% 1/16W MF-LF R7974 ALL_SYS_PWRGD 62 52 41 25 23 CPUVCORE ENABLE 402 CPUIMVP_VR_ON 5% 1/20W MF 201 57 OUT S0 ENABLE PLACE_NEAR=U7400.1:5mm 62 41 26 17 R7978 PM_SLP_S3_L IN 100 PM_SLP_S3_R_L 5% 1/20W MF 201 3.3V/5.0V Sus ENABLE C 2 =PP3V3_S5_PWRCTL 62 7 62 PLACE_NEAR=U7940.5:2.3mm =PP3V3_S0_VMON R7956 SMC_BATLOW_L:100K pull up on SMC page SMC_BATLOW_L 42 41 IN 150K 1% 1/20W MF 201 R7951 15K 1K 17 VMON_Q2_BASE R7954 =PP1V5_S3RS0_VMON 1K NC 5% 1/20W MF 201 PP1V5_S3RS0 Q1 Q2 =PP1V05_S0_VMON 1K 5% 1/20W MF 201 VMON_Q4_BASE B 62 Could stuff R7930 to satisfy PCH power down timing t235 353S2809 S0PGD_BJT_GND_R Worst-Case Thresholds: R7957 Q2: 0.XXXV Q3: 0.640V 3.3V w/Divider: 2.345V Q4: 0.660V MAKE_BASE=TRUE CHGR VFRQ Generation =PP3V3_SUS_PWRCTL S0PGOOD_ISL R79721 10K 1/20W MF 2012 1% 1/20W MF 201 R79611S0PGOOD_ISL 15K R79711 1% 1/20W MF 2012 12.4K 1% 1/20W MF 2012 55 10% 6.3V X5R 201 1% 1/20W MF 201 P1V5_DIV_VMON P1V05_DIV_VMON S0PGOOD_ISL R7973 15K 5% 1/20W MF 201 IN 100 SENSE P5VS3_PGOOD 5% 1/20W MF 201 U7960 59 NC V3MON S0PGOOD_ISL V4MON RST* 1% 1/20W MF 2012 54 IN C7930 0.1UF 100 5% 1/20W MF 201 100 1 C7981 PLACE_NEAR=U7770.3:6mm 0.47UF 10% 6.3V CERM-X5R 402 C7988 C7986 0.47UF 0.47UF 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 B 5% 1/20W MF 201 U7930 RESET* SOT23-6 MR* PM_RSMRST_L OUT 17 PM_RSMRST_L goes to U1800.C21 (90K IPU) WLAN Enable Generation "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal NO STUFF R7966 100 PM_WLAN_EN_L SUS_PGOOD_MR_L Q7925 AP_PWR_EN G NC SOT-363 R7929 G S 5% 1/20W MF 201 S0PGOOD_ISL ALL_SYS_PWRGD OUT 62 41 26 17 IN DRAWING NUMBER 2N7002DW-X-G SOT-363 S G Apple Inc PM_SLP_S3_L 051-9277 (PM_SLP_S3_L) NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION 2.8.0 R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 23 25 41 52 62 5% 1/20W MF 201 SYNC_DATE=11/10/2011 Power Control 1/ENABLE Q7920 D SMC_ADAPTER_EN R7962 NC PAGE TITLE NO STUFF D IN S SYNC_MASTER=J13_MLB_NON_POR 2N7002DW-X-G 42 41 17 G (AC_EN_L) AC_EN_L Q7920 5% 1/20W MF 201 R7964 Unused fet SOT-363 S 100 D 2N7002DW-X-G D SOT-363 IN Q7925 2N7002DW-X-G 37 23 18 NC 37 OUT 330 60 100K THRM_PAD 353S2310 54 OUT R7933 10% 16V X7R-CERM 0201 5% 1/20W MF 201 ALL_SYS_PWRGD_R 10% 6.3V X5R 201 1000PF R7901 CPUVCCIOS0_PGOOD PVCCSA_PGOOD C7931 5% 1/20W MF 201 R7963 ISL88042IRTEZ TDFN (IPU) V2MON CRITICAL MR* GND IN 5% 1/20W MF 201 2 VDD 6.04K P5V_DIV_VMON S0PGOOD_ISL P1V8S0_PGOOD R79601S0PGOOD_ISL 6.04K R79701 1% A IN S0PGOOD_ISL =PP1V5_S3RS0_VMON C7960 =PP1V05_S0_VMON 0.1UF 62 62 IN 60 100 R7965 S0PGOOD_ISL 57 P3V3S5_PGOOD =PVCCSA_EN 62 10K R7968 IN 60 59 GND R79671 CPUIMVP_AXG_PGOOD 55 OUT =1V05_S0_LDO_ENOUT =CPUVCCIOS0_EN OUT PLACE_NEAR=U7930.6:2.3mm S4_PGOOD_CT CT NO STUFF P1V5S0_PGOOD from U7710 =PP3V3_S0_VMON =P1V5S0_EN 60 VFRQ Low: Fix Frequency VFRQ High: Variable Frequency =PP3V3_S5_PWRCTL No stuff C7931, 12ms Min delay time U7930 Sense input threhold is 3.07V =PP3V3_SUS_PWRCTL =PP3V3_S0_PWRCTL S0 Rail PGOOD Circuitry 62 OUT VDD (ISL Version in development) =PP5V_S0_VMON C PLACE_NEAR=U7720.5:6mm C7987 0.47UF TPS3808G33DBVRG4 Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V S CRITICAL 62 7 =P1V8S0_EN MAKE_BASE=TRUE CPUVCCIOS0_EN 3.3V SUS Detect 100 5% 1/20W MF 201 64 P1V5S0_EN 53 R7930 62 OUT D 5% 1/20W MF 201 45 =TBT_S0_EN PLACE_NEAR=U7720.5:6mm MAKE_BASE=TRUE 38 61 OUT P1V8S0_EN SOD-VESM-HF G NO STUFF R7955 61 OUT =PBUSVSENS_EN PVCCSA_EN 5% 1/20W MF 201 CRITICAL Q4 PLACE_NEAR=U7770.3:6mm OUT =P3V3S0_EN MAKE_BASE=TRUE R7917 Q3 5% 1/20W MF 201 =P5VS0_EN PLACE_NEAR=U7100.15:6mm NO STUFF R7986 5.1K 5% 1/20W MF 201 PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm ASMCC0179 39K 5% 1/20W MF 201 61 2 NC =P5V_3V3_SUS_EN OUT 20K 5% 1/20W MF 201 C DFN2015H4-8 VMON_Q3_BASE PM_SUS_EN MAKE_BASE=TRUE PM_SLP_SUS_L Q7950 1% 1/20W MF 201 45 GND 5% 1/20W MF 201 7.15K IN 33K R7988 5% 1/20W MF 201 CHGR_VFRQOUT Q7931 SSM3K15FV Y R7981 PLACE_NEAR=U7600.3:6mm 10K B VMON_3V3_DIV R7952 23 25 41 52 62 S0PGD_C R7953 62 ALL_SYS_PWRGD 1% 1/20W MF 201 R7931 VCC U7940 74AUP1G3208 SOT891 A 62 10% 6.3V X5R 201 =PP3V3_S5_VMON R7987 S0 Rail PGOOD (BJT Version) =PP3V42_G3H_PWRCTL C7943 0.1UF MAKE_BASE=TRUE (PM_SLP_S3_R_L) BRANCH PAGE 79 OF 109 SHEET 62 OF 73 A D PART NUMBER 518S0829 QTY DESCRIPTION REFERENCE DES CONNTWIN-AX,P=0.4,30P,W-BOSS,HF J9000 CRITICAL D BOM OPTION LCD Connector Internal DP Connector: 518S0787 OMIT_TABLE CRITICAL J9000 CABLINE-CA F-RT-SM Pull-ups on panel side, 4.7 kOhm to 3.3V R9061 44 BI =I2C_TCON_SDA 65 31 PPVOUT_SW_LCDBKLT I2C_TCON_SDA_R 5% 1/20W MF 201 NC 44 C IN =I2C_TCON_SCL U9000 =PP3V3_S3_LCD I2C_TCON_SCL_R OUT DP_INT_HPD IN LCD_IG_PWR_EN ON VIN_1 FERR-120-OHM-1.5A VIN_2 GND R9014 1 1K 5% 1/20W MF 201 C9009 0.1UF 2 10% 6.3V X5R 201 VOUT_1 VOUT_2 PP3V3_SW_LCD_UF MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 65 OUT 65 OUT 65 OUT 65 OUT 65 OUT LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1 0.1UF 10% 6.3V X5R 201 C9012 66 10UF 2 BI DP_INT_AUX_CH_N 10% 16V X5R-CERM 0201 20% 6.3V X5R 603 66 BI DP_INT_AUX_CH_P 0.1UF IN DP_INT_ML_P B IN DP_INT_ML_N R9070 100K 2 5% 1/20W MF 201 DP_INT_HPD_CONN 12 13 14 DisplayPort I/F 17 PP3V3_SW_LCD 18 MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 66 66 19 20 DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P 21 22 23 DP_INT_ML_F_P DP_INT_ML_F_N 24 25 26 (DP_INT_AUX_CH_C_P) NC NC 10% 16V X5R-CERM 0201 PLACE_NEAR=J9000.25:1mm R90171 1M 5% 1/20W MF 201 C9021 0.1UF C LED Backlight I/F 11 16 66 0.1UF 15 66 10% 16V X5R-CERM 0201 66 C9025 C9020 66 (DP_INT_AUX_CH_C_N) 10% 16V X7R-CERM 0201 10 NC 1000PF 0.1UF C9015 C9024 C9011 0402-LF THRM PAD OUT 5% 1/20W MF 201 L9004 MFET-2X2-8IN 1 FPF1009 65 NC R9060 CRITICAL 5% 1/20W MF 201 CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP R9062 2 R9018 27 28 29 30 1M 5% 1/20W MF 201 33 34 PLACE_NEAR=J9000.24:1mm 35 B 36 10% 16V X5R-CERM 0201 37 38 39 40 41 PLACE_NEAR=J9000.14:2mm R9050 32 R9080 100K 100K 5% 1/20W MF 201 5% 1/20W MF 201 A 2 PLACE_NEAR=J9000.3:2mm C9017 1000PF 5% 50V C0G-CERM 603 SYNC_MASTER=K21_MLB SYNC_DATE=07/28/2011 PAGE TITLE Internal DisplayPort Connector DRAWING NUMBER Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R BRANCH PAGE 90 OF 109 SHEET 63 OF 73 A 64 V3P3 must be S4 to support wake from Thunderbolt devices CRITICAL C9487 C9480 D 1 C9481 22UF 100UF 20% 6.3V POLY-TANT CASE-B2-SM Nominal IV3P3 1100mA IHVS0 890mA IHVS3 890mA 20% 6.3V X5R-CERM-1 603 0.1UF 10% 16V X5R-CERM 0201 19 20 =PPHV_SW_TBTAPWRSW C9410 4.7UF 12 14 OUT VHV 10% 16V X5R-CERM 0201 CD3210A0RGP QFN 16 RSVD 2 C9486 0.1UF U9410 10% 25V X5R 402 70 34 70 34 C9430 DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_C_P BI BI C9431 =TBTAPWRSW_EN IN TBT_A_HV_EN 11 HV_EN ISET_S0 10 TBTAPWRSW_ISET_S0 =TBT_S0_EN 17 S0 ISET_S3 TBTAPWRSW_ISET_S3 TBTAPWRSW_ISET_V3P3 21 TBTHV:P15V R94101 12V: See below 70 34 IN 70 34 IN DP_TBTPA_ML_C_P DP_TBTPA_ML_C_N 0.22UF C9433 0.22UF TBTHV:P15V THRM PAD 13 GND C9432 ISET_V3P3 IN R9411 22.6K 22.6K 1% 1/20W MF 201 64 R9412 34 IN 25 IN 70 16V 0201 70 10% X5R-CERM 16V 0201 TBT_A_CIO_SEL BIASIN DP_AUXIO_EN AUXIO_EN DP_TBTPA_AUXCH_N DP_TBTPA_AUXCH_P AUXAUX+ 20% X5R BI IN DP_TBTSNK0_DDC_DATA DP_TBTSNK0_DDC_CLK 34 OUT TBT_A_CONFIG1_BUF 16 CA_DETOUT DP_TBTPA_ML_P DP_TBTPA_ML_N 11 DP+ DP- 34 IN TBT_A_LSTX TBT_A_LSRX_UNBUF 14 6.3V 0201 70 70 20% X5R 6.3V 0201 34 IN TBT_A_DP_PWRDN 34 OUT DP_TBTPA_HPD 10 13 12 SOT891 R9426 34 OUT 22.6K 1% 1/20W MF 201 1% 1/20W MF 201 TBT_A_BIAS Y Y = B C9460 0.1UF Single-fault protection requires two R’s per HV ISET_Sx with CD3210 Single R on ISET_V3P3 OK 20% 10V CERM 402 A B C 64 VOLTAGE=3.3V BIASOUT 24 AUXIOAUXIO+ 23 C9425 0.1UF 10% 16V X5R-CERM 0201 D 5% 1/20W MF 201 DP_A_AUXCH_DDC_N DP_A_AUXCH_DDC_P 22 64 70 LSTX LSRX CA_DET 18 TBT_A_CONFIG1_RC 64 70 DPMLO+ DPMLO- 19 DP_A_LSX_ML_P DP_A_LSX_ML_N 20 64 64 70 64 70 TBT: LSX_A_R2P/P2R (P/N) DP_PD HPDOUT TBT_A_HPD 17 HPD GND THMPAD 1 64 R9428 100K 2 5% 1/20W MF 201 GND R9414 TBT_A_LSRX 22.6K TBT: RX_1 Bias Sink 1M VCC R9413 DDC_DAT DDC_CLK U9460 74AUP1T97 TBTHV:P15V 5% 1/20W MF 201 CBTL05023 CRITICAL 1% 1/20W MF 201 TBTAPWRSW_ISET_S0_R TBTHV:P15V 5% 1/20W MF 201 PP3V3_SW_TBTAPWR 36.5K 1% 1/20W MF 201 TBTAPWRSW_ISET_S3_R 100K 10K 10% X5R-CERM 0.1UF RSVD 15 EN 0.1UF 10% 25V X5R 402 R9429 R9427 HVQFN 0.1UF 20% 6.3V CERM-X5R 0402 0.1UF SIGNAL_MODEL=TBT_MUX C9411 10UF 62 IN 10% 16V X5R-CERM 0201 64 PPHV_SW_TBTAPWR 36 34 62 C9421 U9420 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V C9485 CRITICAL 0.1UF 10% 16V X5R-CERM 0201 VDD CRITICAL MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V V3P3OUT 18 V3P3 10% 25V X5R-CERM 0603 Max 1200mA 930mA (assumes 15V, 12W minimum) 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) PP3V3_SW_TBTAPWR 18.9V Max C9415 Min 1030mA 830mA 830mA CRITICAL C9420 0.1UF =PP3V3_S4_TBTAPWRSW PP3V3_SW_TBTAPWR 15 25 3.3V/HV Power MUX 21 C C ILIM = 40000 / RISET PART NUMBER QTY 118S0145 Nominal 1120mA DESCRIPTION 118S0145 IHVS0/S3 REFERENCE DES CRITICAL 0.01UF PP3V3RHV_SW_TBTAPWR C9400 TBTHV:P12V 10% 50V X7R-CERM 0402 12 OUT 70 34 OUT TBT_A_D2R_P TBT_A_D2R_N 20% 4V 201 CERM-X5R-1 0.47UF C9475 70 70 TBT_A_D2R_C_P TBT_A_D2R_C_N 20% 4V 201 CERM-X5R-1 0.47UF C9401 R9494 GND_VOID=TRUE 1K 5% 1/20W MF 201 70 34 IN 70 34 IN C9478 DP_TBTPA_ML_C_P DP_TBTPA_ML_C_N 2 20% X5R 6.3V 0201 20% X5R 6.3V 0201 70 70 0.22UF 64 70 34 OUT OUT TBT_A_D2R_P TBT_A_D2R_N C9476 (Both C’s) C9477 0.47UF 5% MF R9479 470K 1 2.2K 5% 1/20W MF 201 5% 1/20W MF 201 2 1/20W 201 70 0.01UF TBTACONN_7_C 11 15 17 19 GND_VOID=TRUE MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V 10% 25V X5R-CERM 0201 6.3V 0201 TBT_A_R2D_C_P TBT_A_R2D_C_N IN 34 70 IN 34 70 R9471 470K 5% 1/20W MF 201 5% 1/20W MF 201 (0-18.9V) DP_A_LSX_ML_P DP_A_LSX_ML_N 64 70 B 64 70 TBT: LSX_R2P/P2R (P/N) GND_VOID=TRUE CRITICAL (Both D’s) D9498 TBT_A_D2R_C_P TBT_A_D2R_C_N A D9499 20% 4V 201 CERM-X5R-1 TSLP-2-7 A 70 70 K BAR90-02LRH C9472 TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N 70 TBT: TX_1 TSLP-2-7 TBT_A_R2D_P TBT_A_R2D_N C9473 GND_VOID=TRUE 514-0818 GND_VOID=TRUE 6.3V 0201 20% X5R 6.3V 0201 TBT_A_R2D_C_P TBT_A_R2D_C_N IN 34 70 IN 34 70 GND_VOID=TRUE R9472 470K 650NH-5%-0.430MA-0.52OHM 20% X5R 0.22UF DP_A_AUXCH_DDC_P DP_A_AUXCH_DDC_N 0.22UF 70 K BAR90-02LRH (Both C’s) SHIELD PINS L9498 70 64 6.3V 0201 20% X5R GND_VOID=TRUE R9470 470K CRITICAL 70 64 20% X5R 0.22UF C9406 F-RT-TH SIGNAL_MODEL=TBTPIN GND_VOID=TRUE GND_VOID=TRUE 70 MDP-J11 HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND GND AUX_CHP ML_LANE2P AUX_CHN ML_LANE2N DP_PWR RETURN C9471 R9499 2.2K GND_VOID=TRUE 1/20W 201 5% MF 20% 4V 201 CERM-X5R-1 0.47UF 470K DP_TBTPA_ML_P DP_TBTPA_ML_N TBT: Unused R9498 10% 50V X7R-CERM 0402 13 10 12 14 16 18 20 SIGNAL_MODEL=EMPTY TBT_A_BIAS GND_VOID=TRUE 70 34 5% 1/20W MF 201 R9478 0.22UF C9479 R9495 DP Dir TBT_A_R2D_P TBT_A_R2D_N TBT: TX_0 1K SIGNAL_MODEL=EMPTY B TBT Dir 0.22UF 70 J9400 0.01UF GND_VOID=TRUE C9470 70 GND_VOID=TRUE CRITICAL GND_VOID=TRUE (Both C’s) (0-18.9V) TBT Dir 28 27 26 25 24 23 22 21 70 34 For J9400 TBT SMT pads (3, 5, 17 & 19): TBTACONN_20_RC MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V (Both C’s) DP Dir 10% 25V X5R-CERM 0201 R9401 5% 1/20W MF 201 GND_VOID=TRUE C9474 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V 0.01UF Max 1170mA (12W minimum) TBTACONN_1_C MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V 0603 TBTHV:P12V R9411,R9414 RES,MF,1/20W,17.8K,1,0201 C9405 FERR-120-OHM-3A BOM OPTION R9410,R9413 RES,MF,1/20W,17.8K,1,0201 Min 1090mA Thunderbolt Connector A L9400 For 12V systems: R9473 470K 5% 1/20W MF 201 5% 1/20W MF 201 0603 SIGNAL_MODEL=EMPTY C9498 1 30PF 5% 50V C0G-NP0 0402 CRITICAL C9499 2 470k R’s for ESD protection on AC-coupled signals L9499 30PF 650NH-5%-0.430MA-0.52OHM 5% 50V C0G-NP0 0402 0603 GND_VOID=TRUE SIGNAL_MODEL=EMPTY A 34 64 TBT_A_HPD 64 TBT_A_CONFIG1_RC OUT SYNC_MASTER=J11_MLB C9402 R9452 1M 5% 1/20W MF 201 R9451 1M 5% 1/20W MF 201 C9494 1 330PF 10% 16V X7R-CERM 0201 C9495 2 10% 16V X7R-CERM 0201 R9441 10% 25V X5R-CERM 0201 100K 330PF Thunderbolt Connector A DRAWING NUMBER Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R Sink HPD range: High: 2.0 - 5.0V Low: - 0.8V 5% 1/20W MF 201 SYNC_DATE=10/03/2011 PAGE TITLE DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a) 0.01UF TBT_A_CONFIG2_RC BRANCH PAGE 94 OF 109 SHEET 64 OF 73 A PPBUS S0 LCDBkLT FET MOSFET FDC638APZ CHANNEL P-TYPE RDS(ON) 43 mOhm @4.5V LOADING 0.65 A (EDP) CRITICAL Q9706 FDC638APZ_SBMS001 SSOT6-HF F9700 PPBUS_S0_LCDBKLT_FUSED 603-HF BOTTOM C9782 R9788 AND PPBUS_SW_BKL ON THE SENSOR PAGE X7R-CERM MF =PP5V_S0_BKL PLACE_NEAR=L9701.2:3mm CRITICAL =PPBUS_SW_BKL D9701 C9712 R9789 1 10UF 10% 25V X5R 805 1% 1/20W MF 201 SOD-123 CRITICAL 147K CRITICAL L9701 15UH-2.8A LCDBKLT_EN_DIV *LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT 0402 201 D *C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS *PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE 10% 16V 1% PPBUS_SW_LCDBKLT_PWR 0.1UF 301K 1/20W 65 THERE IS A SENSE RESISTOR BETWEEN MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V =PPBUS_S0_LCDBKLT 3AMP-32V-467 D PPBUS_SW_LCDBKLT_PWR MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V PIMB053T-SM C9713 0.1UF 2 PLACE_NEAR=L9701.1:3mm 10% 25V X5R 402 PPBUS_SW_LCDBKLT_PWR_SW A MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.150 MM VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE K PLACE_NEAR=U9701.A5:3mm PPVOUT_SW_LCDBKLT CRITICAL RB160M-60G C9796 220PF PLACE_NEAR=L9701.1:3mm CRITICAL C9797 10UF 10% 50V X7R-CERM 0402 C9799 63 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V 10UF 10% 50V X5R 1210-1 10% 50V X5R 1210-1 PLACE_NEAR=D9701.2:5mm LCDBKLT_EN_L PLACE_NEAR=D9701.2:3mm PLACE_NEAR=U9701.D1:5mm Q9707 D 10% 25V X5R 603-1 SOT563 S LCD_BKLT_EN C9714 G 10% XW9720 SM 201 PPVOUT_SW_LCDBKLT_FB VOLTAGE=50V MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM D C9711 10% 6.3V X5R 201 S PLACE_NEAR=C9797.1:5mm 0.1UF SOT563 C 0.01UF PLACE_NEAR=U9701.C4:4mm LCDBKLT_DISABLE Q9707 C BKLT_PLT_RST_L C4 IN 10V X5R =PP3V3_S0_BKL_VDDIO SSM6N15FEAPE 25 C1 IN D1 G 1UF SSM6N15FEAPE PLACE_NEAR=U9701.D1:3mm C9710 VIN VDDIO VLDO U9701 25-BUMP-MICRO R9731 200K B 1% 1/20W MF 201 R9704 IN LCD_BKLT_PWM 33 BKL_SCL BKL_SDA D3 BKL_PWM BKL_EN A4 PWM A3 EN TP_BKL_FAULT R9715 D4 C3 PLACE_SIDE=BOTTOM FAULT 100K 1% 1/20W MF 5% 1/20W MF 201 Fpwm=9.62kHz see spec for others C9704 33PF 5% R9717 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT1 E5 OUT2 OUT3 D5 C5 BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 OUT4 OUT5 E3 BKL_ISEN4 E2 OUT6 E1 BKL_ISEN5 BKL_ISEN6 R9755 10K 5% 1/20W MF 201 R97161 1% 1/20W MF 201 OUT 63 LED_RETURN_2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 63 OUT 63 OUT 63 OUT 63 OUT 63 BKLT:PROD B R9719 PLACE_NEAR=U9701.C5:10mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BOTTOM BKLT:PROD R9714 5% 1/16W MF-LF 402 BOTTOM R9720 18.2K MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9718 1 90.9K LED_RETURN_1 BKLT:PROD PLACE_NEAR=U9701.D5:10mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm I_LED=20.3mA 25V NPO-C0G 0201 5% 1/16W MF-LF 402 BOTTOM SCLK SDA 201 LP8550 FSET PLACE_NEAR=U9701.E5:10mm GND_SW GND_SW 5% 1/20W MF 201 PPBUS_SW_LCDBKLT_PWR 65 B4 BKLT:PROD B2 A2 BKL_FSET 5% 1/20W MF 201 FB A1 A5 GND_L =I2C_BKL_1_SDA ISET GND_S BI Addr: 0x58(Wr)/0x59(Rd) B3 5% 1/20W MF 201 R9757 44 BKL_ISET E4 =I2C_BKL_1_SCL C2 10K B5 IN BKL_FLTR VSYNC CRITICAL SW_0 SW_1 FILTER B1 R9741 R9753 44 BKL_VSYNC_R D2 PLACE_NEAR=U9701.E3:10mm 1% 1/20W MF 201 PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins) XW9710 SM GND_BKL_SGND 1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BOTTOM BKLT:PROD MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V R9721 PLACE_NEAR=U9701.E2:10mm I_LED=369/Riset (EEPROM should set EN_I_RES=1) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BOTTOM BKLT:PROD R9722 PLACE_NEAR=U9701.E1:10mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BOTTOM A PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 SYNC_MASTER=K21_MLB 103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719 BKLT:ENG 10.2 ohm resistors for current 103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9720,R9721,R9722 BKLT:ENG measurement on LED strings SYNC_DATE=07/28/2011 PAGE TITLE LCD Backlight Driver DRAWING NUMBER Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R BRANCH PAGE 97 OF 109 SHEET 65 OF 73 A CPU Signal Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 0.100 MM 0.100 MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ? D =STANDARD * CPU_45S CPU_45S CPU_45S CPU_COMP CPU_AGTL CPU_AGTL CPU_PECI PM_SYNC PM_MEM_PWRGD CPU_45S CPU_45S CPU_45S CPU_ITP CPU_ITP CPU_ITP XDP_DBRESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L DMI_CLK100M DMI_CLK100M DPLL_REF_CLK120M DPLL_REF_CLK120M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L_R_CFG (XDP_BPM_L_R_CFG) (XDP_BPM_L_R_CFG) (FSB_CPURST_L) CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_ITP CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP EDP_COMP CPU_PEG_COMP CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP CPU_CFG CPU_CATERR_L CPU_VCCIO_SEL CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N DPLL_REF_CLKP DPLL_REF_CLKN ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L XDP_BPM_L XDP_OBSDATA_B CPU_CFG XDP_CPURST_L CPU_VCCSENSE CPU_VCCSENSE CPU_VCCIOSENSE CPU_VCCIOSENSE CPU_AXG_SENSE CPU_AXG_SENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_P2MM CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N CPU_AXG_SENSE_P CPU_AXG_SENSE_N CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N CPU_SVIDALERT_L CPU_SVIDSCLK CPU_SVIDSOUT CPU_45S CPU_45S CPU_45S CPU_COMP CPU_COMP CPU_COMP CPU_VIDALERT_L CPU_VIDSCLK CPU_VIDSOUT PCIE_CPU_MUX_R2D PCIE_CPU_MUX_R2D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_CPU_TX PCIE_CPU_TX PCIE_CPU_TX PCIE_CPU_TX PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_RX PCIE_SSD_R2D_C_P PCIE_SSD_R2D_C_N PCIE_SSD_R2D_MUX_IN_P PCIE_SSD_R2D_MUX_IN_N PCIE_SSD_D2R_P PCIE_SSD_D2R_N PCIE_SSD_D2R_MUX_OUT_P PCIE_SSD_D2R_MUX_OUT_N PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_TX PCIE_CPU_TX PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_RX PCIE_SSD_R2D_C_P PCIE_SSD_R2D_C_N PCIE_SSD_R2D_P PCIE_SSD_R2D_N PCIE_SSD_D2R_P PCIE_SSD_D2R_N PCIE_SSD_D2R_C_P PCIE_SSD_D2R_C_N PCIE_CLK100M_SSD PCIE_CLK100M_SSD CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE CLK_PCIE PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N DP_INT_ML DP_INT_ML DP_80D DP_80D DP_80D DP_80D DP_TX DP_TX DP_TX DP_TX DP_INT_ML_P DP_INT_ML_N DP_INT_ML_F_P DP_INT_ML_F_N DP_AUX DP_AUX DP_AUX DP_AUX DP_INT_AUX_CH_C_P DP_INT_AUX_CH_C_N DP_INT_AUX_CH_P DP_INT_AUX_CH_N ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_HEAD SPACING_RULE_SET SPACING_RULE_SET LAYER LINE-TO-LINE SPACING CPU_8MIL * * CPU_8MIL_2ANY NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_RULE_ITEM CPU_8MIL_2ANY * MIL ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_ASSIGNMENT_ITEM CPU_ITP * * CPU_ITP_2ANY NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CPU_COMP CPU_COMP * CPU_COMP_2SELF * =4x_DIELECTRIC ? LINE-TO-LINE SPACING WEIGHT =6x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_HEAD LAYER TABLE_SPACING_RULE_ITEM CPU_COMP_2SELF TOP,BOTTOM TABLE_SPACING_ASSIGNMENT_ITEM * CPU_PECI PM_SYNC PM_MEM_PWRGD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM * Note: CPU_8MIL and CPU_ITP can be converted back to TABLE_SPACING_RULE once rdar://10308147 is resolved TABLE_SPACING_RULE_ITEM CPU_ITP_2ANY TABLE_SPACING_RULE_ITEM CPU_COMP_2OTHER CPU_COMP_2OTHER TOP,BOTTOM =10x_DIELECTRIC ? LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_RULE_ITEM CPU_COMP_2SELF * CPU_CATERR_L TABLE_SPACING_RULE_ITEM CPU_COMP_2OTHER * =6x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CPU_VCCSENSE CPU_VCCSENSE * CPU_VCCSENSE_2SELF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =6x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM CPU_VCCSENSE_2SELF TOP,BOTTOM TABLE_SPACING_ASSIGNMENT_ITEM CPU_VCCSENSE * * TABLE_SPACING_RULE_ITEM CPU_VCCSENSE_2OTHER CPU_VCCSENSE_2OTHER TOP,BOTTOM =10x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET C LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CPU_VCCSENSE_2SELF * TABLE_SPACING_RULE_ITEM CPU_VCCSENSE_2OTHER * =6x_DIELECTRIC ? PCI-Express Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM PCIE_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF CLK_PCIE_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM PCIE Clock Spacing TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE CLK_PCIE * CLK_PCIE_2SELF TABLE_SPACING_RULE_ITEM CLK_PCIE_2SELF TOP,BOTTOM =6x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE * * CLK_PCIE_2OTHER CLK_PCIE_2OTHER TOP,BOTTOM =10x_DIELECTRIC ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD LAYER TABLE_SPACING_RULE_ITEM CLK_PCIE_2SELF * =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CLK_PCIE_2OTHER * =6x_DIELECTRIC ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_ASSIGNMENT_ITEM PCIE_CPU_TX PCIE_CPU_TX B * PCIE_TX2TX TABLE_SPACING_RULE_ITEM PCIE_TX2TX TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM PCIE_CPU_RX PCIE_CPU_RX * PCIE_RX2RX PCIE_CPU_TX *_CPU_TX * PCIE_TX2OTHERTX TABLE_SPACING_RULE_ITEM PCIE_RX2RX TOP,BOTTOM =5x_DIELECTRIC ? PCIE_TX2OTHERTX TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM *_CPU_RX * PCIE_RX2OTHERRX TABLE_SPACING_RULE_ITEM PCIE_RX2OTHERRX TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM PCIE_CPU_TX *_CPU_RX * PCIE_TX2RX PCIE_CPU_RX *_CPU_TX * PCIE_RX2TX TABLE_SPACING_RULE_ITEM PCIE_TX2RX TOP,BOTTOM =7x_DIELECTRIC ? PCIE_RX2TX TOP,BOTTOM =7x_DIELECTRIC ? PCIE_2OTHERHS TOP,BOTTOM =6x_DIELECTRIC ? PCIE_2OTHER TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM *_TX * PCIE_2OTHERHS PCIE_CPU_RX *_TX * PCIE_2OTHERHS TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_CPU_TX *_RX * PCIE_2OTHERHS PCIE_CPU_RX *_RX * PCIE_2OTHERHS PCIE_CPU_TX * * PCIE_2OTHER PCIE_CPU_RX * * PCIE_2OTHER LINE-TO-LINE SPACING WEIGHT PCIE_TX2TX * =2.5x_DIELECTRIC ? PCIE_RX2RX * =2.5x_DIELECTRIC ? PCIE_CPU_SSD_R2D PCIE_CPU_SSD_R2D TABLE_SPACING_RULE_ITEM PCH PCIE Spacing PCIE_TX2OTHERTX * =4x_DIELECTRIC ? PCIE_RX2OTHERRX * =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCIE_PCH_TX PCIE_PCH_TX * PCIE_TX2TX PCIE_PCH_RX PCIE_PCH_RX * PCIE_RX2RX TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM * =6x_DIELECTRIC ? PCIE_RX2TX * =6x_DIELECTRIC ? PCIE_2OTHERHS PCIE_TX2RX * =4x_DIELECTRIC ? PCIE_CPU_SSD_D2R PCIE_CPU_SSD_D2R TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM *_PCH_TX * PCIE_TX2OTHERTX PCIE_PCH_RX *_PCH_RX * PCIE_RX2OTHERRX PCIE_PCH_TX *_PCH_RX * PCIE_TX2RX TABLE_SPACING_ASSIGNMENT_ITEM A LAYER TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_PCH_TX SPACING_RULE_SET TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE1 PCIE_CPU_MUX_D2R PCIE_CPU_MUX_D2R TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM PCIE_2OTHER * =3x_DIELECTRIC * PCIE_RX2TX PCIE_PCH_TX *_TX * PCIE_2OTHERHS PCIE_PCH_RX *_TX * PCIE_2OTHERHS PCIE_PCH_TX *_RX * PCIE_2OTHERHS TABLE_SPACING_ASSIGNMENT_ITEM Note: DisplayPort tables are on Page 103 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM *_RX * PCIE_2OTHERHS PCIE_PCH_TX * * PCIE_2OTHER PCIE_PCH_RX * * PCIE_2OTHER D 17 17 10 19 42 10 17 10 17 26 10 23 25 10 23 10 23 9 10 10 10 23 10 41 12 10 41 42 57 10 19 23 10 19 42 10 16 10 16 10 10 10 16 C 10 16 16 23 16 23 23 23 10 23 10 23 10 23 10 23 10 23 10 23 10 23 23 23 23 12 57 12 57 12 59 12 59 12 57 12 57 12 12 9 B 9 12 57 12 57 12 57 38 38 38 38 38 38 38 38 38 PCIe SSD 38 38 38 38 38 16 38 16 38 DP_INT_AUXCH DP_INT_AUXCH DP_80D DP_80D DP_80D DP_80D TABLE_SPACING_ASSIGNMENT_ITEM SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback SYNC_DATE=01/11/2012 PAGE TITLE 63 CPU Constraints 63 DRAWING NUMBER 63 Apple Inc 63 DP TABLE_SPACING_ASSIGNMENT_ITEM 17 SYNC_MASTER=J13_CONSTRAINTS TABLE_SPACING_ASSIGNMENT_ITEM PCIE_PCH_RX DMI/FDI 17 ? TABLE_SPACING_ASSIGNMENT_ITEM *_PCH_TX 17 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_PCH_RX 17 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_CPU_TX 17 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_CPU_RX 17 TABLE_SPACING_RULE_ITEM SPACING_RULE_SET CPU PCIE Spacing 17 WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM CPU_COMP SPACING DMI_S2N_P DMI_S2N_N DMI_N2S_P DMI_N2S_N FDI_DATA_P FDI_DATA_N FDI_FSYNC FDI_LSYNC FDI_INT PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D CPU_45S CPU_45S CPU_45S TABLE_SPACING_RULE_ITEM CPU_AGTL NET_TYPE PHYSICAL PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_RX PCIE_PCH_RX PCIE_PCH_RX PCIE_PCH_RX CPU_AGTL CPU_AGTL CPU_AGTL DMI_S2N DMI_S2N DMI_N2S DMI_N2S FDI_DATA FDI_DATA TABLE_PHYSICAL_RULE_ITEM * CPU Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET CPU_27P4S 051-9277 63 63 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 2.8.0 63 63 SIZE REVISION R BRANCH PAGE 100 OF 109 SHEET 66 OF 73 A Memory Bus Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MEM_72D * =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF MEM_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM Spacing Rule Sets TABLE_SPACING_RULE_HEAD D LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? PalPilot Spacing "Real" Spacing =2x_DIELECTRIC =2x_DIELECTRIC =5.7x_DIELECTRIC =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM MEM_DATA2SELF * TABLE_SPACING_RULE_ITEM MEM_DQS2OWNDATA * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * =3x_DIELECTRIC ? MEM_CMD2CTRL * =3x_DIELECTRIC ? MEM_CTRL2CTRL * =3x_DIELECTRIC ? =4x_DIELECTRIC =3x_DIELECTRIC =4x_DIELECTRIC =3x_DIELECTRIC =4x_DIELECTRIC =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_CLK2CLK * =6x_DIELECTRIC ? MEM_2OTHERMEM * =4x_DIELECTRIC ? MEM_2PWR * =PWR_P2MM ? =8.6x_DIELECTRIC =6x_DIELECTRIC =5.7x_DIELECTRIC =4x_DIELECTRIC =PWR_P2MM =PWR_P2MM =GND_P2MM =GND_P2MM =8.6x_DIELECTRIC =6x_DIELECTRIC TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_2GND * =GND_P2MM ? TABLE_SPACING_RULE_ITEM MEM_2OTHER =6x_DIELECTRIC * ? Memory to Power Spacing TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_PWR MEM_* * MEM_2PWR TABLE_SPACING_ASSIGNMENT_ITEM MEM_PWR * * DEFAULT Memory to GND Spacing TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET GND MEM_* * MEM_2GND TABLE_SPACING_ASSIGNMENT_ITEM C Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQS_0 MEM_A_DATA_0 * MEM_DQS2OWNDATA MEM_A_DQS_1 MEM_A_DATA_1 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQS_0 * * MEM_2OTHER MEM_A_DQS_1 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_2 MEM_A_DATA_2 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_2 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_3 MEM_A_DATA_3 * MEM_DQS2OWNDATA MEM_A_DQS_4 MEM_A_DATA_4 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_3 * * MEM_2OTHER MEM_A_DQS_4 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_5 MEM_A_DATA_5 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_5 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_6 MEM_A_DATA_6 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_6 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_7 MEM_A_DATA_7 * MEM_DQS2OWNDATA MEM_B_DQS_0 MEM_B_DATA_0 * MEM_DQS2OWNDATA MEM_B_DQS_1 MEM_B_DATA_1 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS_7 * * MEM_2OTHER MEM_B_DQS_0 * * MEM_2OTHER MEM_B_DQS_1 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_2 MEM_B_DATA_2 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_2 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_3 MEM_B_DATA_3 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_3 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_4 MEM_B_DATA_4 * MEM_DQS2OWNDATA MEM_B_DQS_5 MEM_B_DATA_5 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_4 * * MEM_2OTHER MEM_B_DQS_5 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM B TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_6 MEM_B_DATA_6 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_6 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_7 MEM_B_DATA_7 * MEM_DQS2OWNDATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS_7 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_*_DATA_* =SAME * MEM_DATA2SELF TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DATA_0 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DATA_1 * * MEM_2OTHER MEM_A_DATA_2 * * MEM_2OTHER MEM_A_DATA_3 * * MEM_2OTHER MEM_A_DATA_4 * * MEM_2OTHER MEM_A_DATA_5 * * MEM_2OTHER MEM_A_DATA_6 * * MEM_2OTHER MEM_A_DATA_7 * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET SPACING_RULE_SET NET_SPACING_TYPE2 AREA_TYPE MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_CTRL * SPACING_RULE_SET MEM_CMD2CTRL NET_TYPE PHYSICAL SPACING MEM_A_CLK MEM_A_CLK MEM_A_CTRL MEM_A_CTRL MEM_A_CTRL MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_72D MEM_72D MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_CLK MEM_CLK MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_DATA_0 MEM_A_DATA_1 MEM_A_DATA_2 MEM_A_DATA_3 MEM_A_DATA_4 MEM_A_DATA_5 MEM_A_DATA_6 MEM_A_DATA_7 MEM_A_DQS_0 MEM_A_DQS_0 MEM_A_DQS_1 MEM_A_DQS_1 MEM_A_DQS_2 MEM_A_DQS_2 MEM_A_DQS_3 MEM_A_DQS_3 MEM_A_DQS_4 MEM_A_DQS_4 MEM_A_DQS_5 MEM_A_DQS_5 MEM_A_DQS_6 MEM_A_DQS_6 MEM_A_DQS_7 MEM_A_DQS_7 MEM_A_CLK_P MEM_A_CLK_N MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_B_CLK MEM_B_CTRL MEM_B_CTRL MEM_B_CTRL MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MEM_72D MEM_72D MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_CLK MEM_CLK MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_DATA_0 MEM_B_DATA_1 MEM_B_DATA_2 MEM_B_DATA_3 MEM_B_DATA_4 MEM_B_DATA_5 MEM_B_DATA_6 MEM_B_DATA_7 MEM_B_DQS_0 MEM_B_DQS_0 MEM_B_DQS_1 MEM_B_DQS_1 MEM_B_DQS_2 MEM_B_DQS_2 MEM_B_DQS_3 MEM_B_DQS_3 MEM_B_DQS_4 MEM_B_DQS_4 MEM_B_DQS_5 MEM_B_DQS_5 MEM_B_DQS_6 MEM_B_DQS_6 MEM_B_DQS_7 MEM_B_DQS_7 MEM_B_CLK_P MEM_B_CLK_N MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_PWR MEM_PWR MEM_PWR MEM_PWR PP1V5_S3RS0 PP1V5_S3 PP0V75_S3_MEM_VREFCA_A PP0V75_S3_MEM_VREFDQ_A 11 27 28 32 11 27 28 32 11 27 28 32 11 27 28 32 11 27 28 32 11 27 28 32 11 27 28 32 D 11 27 28 32 11 27 28 32 11 27 28 32 11 27 11 27 11 27 11 27 11 28 11 28 11 28 11 28 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 C 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 11 29 11 29 11 29 11 29 11 30 11 30 11 30 11 30 11 29 11 29 11 29 11 29 11 29 11 29 11 29 B 11 29 11 30 11 30 11 30 11 30 11 30 11 30 11 30 11 30 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK MEM_CLK * MEM_CLK2CLK 7 27 28 31 27 28 31 TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DATA_0 * * MEM_2OTHER MEM_B_DATA_1 * * MEM_2OTHER MEM_B_DATA_2 * * MEM_2OTHER MEM_B_DATA_3 * * MEM_2OTHER MEM_B_DATA_4 * * MEM_2OTHER MEM_B_DATA_5 * * MEM_2OTHER MEM_B_DATA_6 * * MEM_2OTHER MEM_B_DATA_7 * * MEM_2OTHER MEM_CMD * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER MEM_CLK * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_* MEM_* * MEM_2OTHERMEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM A SYNC_MASTER=J13_CONSTRAINTS TABLE_SPACING_ASSIGNMENT_ITEM SYNC_DATE=01/11/2012 PAGE TITLE Memory Constraints TABLE_SPACING_ASSIGNMENT_ITEM DRAWING NUMBER TABLE_SPACING_ASSIGNMENT_ITEM Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R BRANCH PAGE 101 OF 109 SHEET 67 OF 73 A SATA Interface Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF SPACING_RULE_SET LAYER ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM SATA3_PCH_TX SATA3_PCH_TX SATA3_PCH_TX SATA3_PCH_TX SATA3_PCH_TX SATA3_PCH_TX SATA3_PCH_RX SATA3_PCH_RX SATA3_PCH_RX SATA3_PCH_RX SATA3_PCH_RX SATA3_PCH_RX SATA_ICOMP SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_SSD_R2D_MUX_IN_P SATA_SSD_R2D_MUX_IN_N SATA_SSD_R2D_P SATA_SSD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_SSD_D2R_MUX_OUT_P SATA_SSD_D2R_MUX_OUT_N SATA_SSD_D2R_P SATA_SSD_D2R_N PCH_SATAICOMP USB_TPAD_M USB_TPAD_M USB_SDCARD USB_SDCARD USB_SMC USB_SMC USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_HUB_UP_P USB_HUB_UP_N USB_BT_P USB_BT_N USB_BT_CONN_P USB_BT_CONN_N USB_BT_WAKE_P USB_BT_WAKE_N USB_TPAD_P USB_TPAD_N USB_TPAD_CONN_P USB_TPAD_CONN_N USB_TPAD_HUB_P USB_TPAD_HUB_N USB_TPAD_R_P USB_TPAD_R_N USB_TPAD_M_P USB_TPAD_M_N USB_SDCARD_P USB_SDCARD_N USB_SMC_P USB_SMC_N USB_CAMERA USB_CAMERA USB_80D USB_80D USB USB USB_CAMERA_P USB_CAMERA_N USB_EXTA USB_EXTA USB_80D USB_80D UART_45S UART_45S USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB USB UART UART USB USB USB USB USB3_PCH_RX USB3_PCH_RX USB3_PCH_TX USB3_PCH_TX USB3_PCH_RX USB3_PCH_RX USB3_PCH_TX USB3_PCH_TX USB3_PCH_TX USB3_PCH_TX USB_EXTA_P USB_EXTA_N SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_EXTA_MUXED_F_P USB2_EXTA_MUXED_F_N USB3_EXTA_RX_P USB3_EXTA_RX_N USB3_EXTA_TX_P USB3_EXTA_TX_N USB3_EXTA_RX_F_P USB3_EXTA_RX_F_N USB3_EXTA_TX_F_P USB3_EXTA_TX_F_N USB3_EXTA_TX_C_P USB3_EXTA_TX_C_N USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB USB USB USB USB USB USB3_PCH_RX USB3_PCH_RX USB3_PCH_RX USB3_PCH_RX USB3_PCH_RX USB3_PCH_RX USB3_PCH_TX USB3_PCH_TX USB3_PCH_TX USB3_PCH_TX USB_EXTB_P USB_EXTB_N USB_EXTB_EHCI_P USB_EXTB_EHCI_N USB_EXTB_XHCI_P USB_EXTB_XHCI_N USB3_EXTB_RX_P USB3_EXTB_RX_N USB3_EXTB_RX_RC_P USB3_EXTB_RX_RC_N USB3_EXTB_RX_CONN_P USB3_EXTB_RX_CONN_N USB3_EXTB_TX_P USB3_EXTB_TX_N USB3_EXTB_TX_C_P USB3_EXTB_TX_C_N (USB_TPAD_HUB) (USB_TPAD_HUB) USB_80D USB_80D USB USB USB_EXTD_XHCI_P USB_EXTD_XHCI_N PCH_USB_RBIAS PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_USB_RBIAS CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CPU_45S CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE PCH_USB_RBIAS PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK WEIGHT TABLE_SPACING_RULE_ITEM * =4x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SATA3_PCH_TX SATA3_PCH_TX * SATA3_TX2TX SATA3_PCH_RX SATA3_PCH_RX * SATA3_RX2RX SATA3_PCH_TX *_PCH_TX * SATA3_TX2OTHERTX SATA3_PCH_RX *_PCH_RX * SATA3_RX2OTHERRX SATA3_PCH_TX *_PCH_RX * SATA3_TX2RX SATA3_PCH_RX *_PCH_TX * SATA3_RX2TX SATA3_PCH_TX *_TX * SATA3_2OTHERHS SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT SATA3_TX2TX TOP,BOTTOM =5x_DIELECTRIC ? SATA3_RX2RX TOP,BOTTOM LAYER =5x_DIELECTRIC ? SATA3_TX2OTHERTX TOP,BOTTOM =5x_DIELECTRIC ? SATA3_RX2OTHERRX TOP,BOTTOM =5x_DIELECTRIC ? SATA3_TX2RX TOP,BOTTOM =7x_DIELECTRIC ? SATA3_RX2TX TOP,BOTTOM =7x_DIELECTRIC ? SATA3_2OTHERHS TOP,BOTTOM =6x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM USB_HUB1_UP USB_HUB1_UP USB_BT USB_BT TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM * TABLE_SPACING_RULE_ITEM SATA3_2OTHERHS SATA3_2OTHER TOP,BOTTOM ? =5x_DIELECTRIC TABLE_SPACING_ASSIGNMENT_ITEM SATA3_PCH_TX *_RX * SATA3_2OTHERHS TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM SATA3_PCH_RX *_RX * SATA3_2OTHERHS SATA3_PCH_TX * * SATA3_2OTHER SATA3_PCH_RX * * SATA3_2OTHER LINE-TO-LINE SPACING WEIGHT SATA3_TX2TX LAYER * =2.5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM USB_TPAD USB_TPAD TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SATA3_RX2RX * =2.5x_DIELECTRIC ? SATA3_TX2OTHERTX * =4x_DIELECTRIC ? SATA3_RX2OTHERRX * =4x_DIELECTRIC ? SATA3_TX2RX * =6x_DIELECTRIC ? SATA3_RX2TX * =6x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM USB_TPAD_HUB USB_TPAD_HUB TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM SATA3_2OTHERHS =4x_DIELECTRIC * ? TABLE_SPACING_RULE_ITEM SATA3_2OTHER C * ? =3x_DIELECTRIC SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback UART Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP UART_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM UART * =2x_DIELECTRIC ? USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB3_EXTA_RX USB3_EXTA_RX USB3_EXTA_TX USB3_EXTA_TX TABLE_PHYSICAL_RULE_ITEM PCH_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM USB_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM USB * TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8 USB 3.0 Interface Constraints TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 B NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING USB3_PCH_TX * USB3_TX2TX USB3_PCH_RX USB3_PCH_RX * USB3_RX2RX TABLE_SPACING_RULE_ITEM USB3_TX2TX TOP,BOTTOM =5x_DIELECTRIC ? USB3_RX2RX TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_TX *_PCH_TX * USB3_TX2OTHERTX TABLE_SPACING_RULE_ITEM USB3_TX2OTHERTX TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_RX *_PCH_RX * USB3_RX2OTHERRX USB3_PCH_TX *_PCH_RX * USB3_TX2RX TABLE_SPACING_RULE_ITEM USB3_RX2OTHERRX TOP,BOTTOM =5x_DIELECTRIC ? USB3_TX2RX TOP,BOTTOM =7x_DIELECTRIC ? USB3_RX2TX TOP,BOTTOM =7x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM *_PCH_TX * USB3_RX2TX TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_TX *_TX * USB3_2OTHERHS USB3_PCH_RX *_TX * USB3_2OTHERHS USB3_PCH_TX *_RX * USB3_2OTHERHS USB3_EXTB_RX USB3_EXTB_RX TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_RX USB_EXTB USB_EXTB WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_TX TABLE_SPACING_RULE_ITEM USB3_2OTHERHS TOP,BOTTOM =6x_DIELECTRIC ? USB3_2OTHER TOP,BOTTOM =5x_DIELECTRIC ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM USB3_EXTB_TX USB3_EXTB_TX TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_RX *_RX * USB3_2OTHERHS * * USB3_2OTHER USB3_PCH_RX * * USB3_2OTHER SPACING_RULE_SET LAYER TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_TX USB3_TX2TX * =2.5x_DIELECTRIC ? USB3_RX2RX * =2.5x_DIELECTRIC ? USB3_TX2OTHERTX * =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM USB3_RX2OTHERRX * =4x_DIELECTRIC ? USB3_TX2RX * =6x_DIELECTRIC ? USB3_RX2TX * =6x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM USB3_2OTHERHS * =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM A 16 38 16 38 38 38 38 38 16 38 SATA SSD D 16 38 38 38 38 38 16 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM *_TX SATA_MUX_SSD_D2R SATA_MUX_SSD_D2R PCH_SATA_ICOMP TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SATA3_PCH_RX SATA_MUX_SSD_R2D SATA_MUX_SSD_R2D SATA_PCH_MUX_D2R SATA_PCH_MUX_D2R TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM D NET_TYPE SPACING PHYSICAL SATA_80D SATA_80D SATA_80D SATA_80D SATA_80D SATA_80D SATA_80D SATA_80D SATA_80D SATA_80D SATA_80D SATA_80D SATA_PCH_MUX_R2D SATA_PCH_MUX_R2D TABLE_SPACING_RULE_HEAD SATA_ICOMP PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LINE-TO-LINE SPACING USB3_2OTHER * =3x_DIELECTRIC ? SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback 18 24 18 24 24 37 24 37 37 37 37 37 49 USB Hub nets 49 6 24 24 24 49 24 49 49 49 24 33 24 33 C 24 41 24 41 18 40 18 40 USB Camera nets 18 39 18 39 39 41 42 39 41 42 39 39 39 39 18 39 18 39 USB EXTA nets (Right USB port) 18 39 18 39 39 39 39 39 39 39 24 40 B 24 40 18 24 18 24 18 24 18 24 18 40 18 40 40 USB EXTB nets (Left USB port) 40 18 40 18 40 40 40 18 24 18 24 Unused USB nets 18 16 16 16 16 16 16 16 SYNC_MASTER=J13_CONSTRAINTS SYNC_DATE=01/11/2012 PAGE TITLE PCH Constraints DRAWING NUMBER Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R BRANCH PAGE 102 OF 109 SHEET 68 OF 73 A LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM LPC_AD LPC_FRAME_L TABLE_PHYSICAL_RULE_ITEM CLK_LPC_45S * SPACING_RULE_SET LAYER =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING LPC_CLK33M WEIGHT TABLE_SPACING_RULE_ITEM LPC * =3x_DIELECTRIC ? LPC_CLK33M TABLE_SPACING_RULE_ITEM CLK_LPC D * PCH Net Properties =4x_DIELECTRIC ? LPC_CLK33M SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15 SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH SMB_45S_R_50S TOP,BOTTOM =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE SMB_45S_R_50S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM NET_TYPE PHYSICAL SPACING LPC_45S LPC_45S LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S LPC LPC LPC CLK_LPC CLK_LPC CLK_LPC CLK_LPC CLK_LPC CLK_LPC ELECTRICAL_CONSTRAINT_SET LPC_AD LPC_FRAME_L LPCPLUS_RESET_L LPC_CLK33M_SMC LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS LPC_CLK33M_LPCPLUS_R PCH_CLK33M_PCIIN PCH_CLK33M_PCIOUT SMBUS_PCH_CLK SMBUS_PCH_DATA SMBUS_PCH_0_CLK SMBUS_PCH_0_DATA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB SMB SMB SMB SMB SMB SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA HDA_BIT_CLK HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDOUT HDA_SDOUT_R CLK_SLOW_45S CLK_SLOW_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S CLK_SLOW CLK_SLOW SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI PM_CLK32K_SUSCLK_R SMC_CLK32K SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L SPI_SMC_CLK SPI_SMC_MOSI SPI_SMC_MISO SPI_SMC_CS_L SPI_MLB_CLK SPI_MLB_MOSI SPI_MLB_MISO SPI_MLB_CS_L PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D CLK_PCIE_80D CLK_PCIE_80D PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_RX PCIE_PCH_RX CLK_PCIE CLK_PCIE PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D CLK_PCIE_80D CLK_PCIE_80D PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_RX PCIE_PCH_RX PCIE_PCH_RX PCIE_PCH_RX CLK_PCIE CLK_PCIE PCIE_TBT_R2D_P PCIE_TBT_R2D_N PCIE_TBT_R2D_C_P PCIE_TBT_R2D_C_N PCIE_TBT_D2R_P PCIE_TBT_D2R_N PCIE_TBT_D2R_C_P PCIE_TBT_D2R_C_N PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE CLK_PCIE PEG_CLK100M_P PEG_CLK100M_N PCH_45S PCH_45S PCH_45S PCH_45S PCH_ITP PCH_ITP PCH_ITP PCH_ITP XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_TCK 16 41 43 16 41 43 DP_TBT_ML DP_TBT_ML 25 43 25 41 18 25 25 43 DP_TBT_AUXCH DP_TBT_AUXCH 18 25 16 25 LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SMB =2x_DIELECTRIC * ? HDA_SYNC HD Audio Interface Constraints HDA_RST_L TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD HDA_SDIN0 HDA_SDOUT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC ? PM_SUS_CLK SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15 SPI_CLK SIO Signal Constraints SPI_MOSI TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_MISO SPI_CS0 TABLE_PHYSICAL_RULE_ITEM C CLK_SLOW_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW * =4x_DIELECTRIC ? SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SPI_45S * =45_OHM_SE SPACING_RULE_SET LAYER =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD PCIE_AP_R2D PCIE_AP_R2D TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SPI * =4x_DIELECTRIC ? XDP Constraints PCIE_AP_D2R PCIE_AP_D2R PCIE_CLK100M_AP PCIE_CLK100M_AP TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCH_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM PCIE_TBT_R2D PCIE_TBT_R2D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2:1_SPACING ? TABLE_SPACING_RULE_ITEM PCH_ITP * PCIE_TBT_D2R PCIE_TBT_D2R DisplayPort B TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM DP_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM * =3x_DIELECTRIC ? * =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM DP_2DP TOP,BOTTOM =4x_DIELECTRIC ? DP_2OTHERHS TOP,BOTTOM =6x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM * =3x_DIELECTRIC ? DP_AUX * =3x_DIELECTRIC ? DP_TX DP_TX DP_TX DP_TX DP_AUX DP_AUX DP_AUX DP_AUX DP_TBTSNK0_ML_P DP_TBTSNK0_ML_N DP_TBTSNK0_ML_C_P DP_TBTSNK0_ML_C_N DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_TX DP_TX DP_TX DP_TX DP_AUX DP_AUX DP_AUX DP_AUX DP_TBTSNK1_ML_P DP_TBTSNK1_ML_N DP_TBTSNK1_ML_C_P DP_TBTSNK1_ML_C_N DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N 34 34 34 34 34 34 16 44 DP_TBT_ML DP_TBT_ML 34 D 34 16 44 16 44 16 44 16 44 DP_TBT_AUXCH DP_TBT_AUXCH 16 44 34 34 34 34 34 34 34 34 16 40 16 16 40 Clock Net Properties 16 16 16 40 ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING 16 40 16 40 SYSCLK_CLK32K_RTC CLK_SLOW_45S CLK_SLOW SYSCLK_CLK32K_RTC SYSCLK_CLK25M_SB CLK_25M_45S CLK_25M_45S CLK_25M CLK_25M SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB_R SYSCLK_CLK25M_TBT CLK_25M_45S CLK_25M_45S CLK_25M CLK_25M SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT_R CLK_25M CLK_25M CLK_25M SYSCLK_CLK25M_X1 SYSCLK_CLK25M_X2 SYSCLK_CLK25M_X2_R 16 25 16 25 17 42 16 25 16 41 42 16 43 43 25 34 34 16 43 SYSCLK_CLK25M_XTAL 43 16 43 16 43 CLK_25M_45S CLK_25M_45S CLK_25M_45S 25 25 C 25 43 41 42 41 42 41 42 41 42 42 43 50 42 43 50 42 43 50 42 43 50 37 37 16 37 16 37 16 37 16 37 16 37 16 37 34 34 34 34 34 34 B 34 34 16 34 16 34 16 16 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM DP_2OTHER DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D TABLE_SPACING_RULE_HEAD WEIGHT DP_2DP DP_2OTHERHS PCIE_CLK100M_TBT PCIE_CLK100M_TBT NET_TYPE PHYSICAL SPACING 18 25 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET Chipset Net Properties XDP_TDI XDP_TDO XDP_TMS XDP_TCK TABLE_SPACING_RULE_ITEM DP_2OTHER TOP,BOTTOM =4x_DIELECTRIC ? DP_AUX TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 16 23 16 23 16 23 16 23 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM DP_TX DP_TX * DP_2DP DP_TX *_TX * DP_2OTHERHS DP_TX *_RX * DP_2OTHERHS DP_TX * * DP_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM A System Clock Signal Constraints SYNC_MASTER=J13_CONSTRAINTS MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD LAYER CLK_SLOW_45S CLK_25M_45S SYNC_DATE=01/11/2012 PAGE TITLE PCH Constraints TABLE_PHYSICAL_RULE_HEAD ALLOW ROUTE ON LAYER? PHYSICAL_RULE_SET DRAWING NUMBER TABLE_PHYSICAL_RULE_ITEM Apple Inc TABLE_PHYSICAL_RULE_ITEM 051-9277 NOTICE OF PROPRIETARY PROPERTY: TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED TABLE_SPACING_RULE_ITEM CLK_SLOW * TABLE_SPACING_RULE_ITEM CLK_25M * =5x_DIELECTRIC ? NOTE: 25MHz system clocks very sensitive to noise SIZE D REVISION 2.8.0 R BRANCH PAGE 103 OF 109 SHEET 69 OF 73 A DisplayPort Signal Constraints ELECTRICAL_CONSTRAINT_SET Thunderbolt SPI Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TBT_SPI_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM TBT_SPI D * =2x_DIELECTRIC ? TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_TX TBTDP_TX TBTDP_TX TBTDP_TX TBT_A_R2D_C_P TBT_A_R2D_C_N TBT_A_R2D_P TBT_A_R2D_N DP_TBTPA_ML1 DP_TBTPA_ML1 DP_TBTPA_ML3 DP_TBTPA_ML3 DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_TX DP_TX DP_TX DP_TX DP_TX DP_TX DP_TX DP_TX DP_TBTPA_ML_C_P DP_TBTPA_ML_C_N DP_TBTPA_ML_C_P DP_TBTPA_ML_C_N DP_TBTPA_ML_P DP_TBTPA_ML_N DP_A_LSX_ML_P DP_A_LSX_ML_N TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBT_A_D2R_C_P TBT_A_D2R_C_N TBT_A_D2R_P TBT_A_D2R_N TBT_A_D2R_P TBT_A_D2R_N DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D TBTDP_80D TBTDP_80D DP_AUX DP_AUX DP_AUX DP_AUX DP_AUX DP_AUX TBTDP_RX TBTDP_RX DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_P DP_TBTPA_AUXCH_N DP_A_AUXCH_DDC_P DP_A_AUXCH_DDC_N TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N TBT_B_R2D TBT_B_R2D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_TX TBTDP_TX TBTDP_TX TBTDP_TX TBT_B_R2D_C_P TBT_B_R2D_C_N TBT_B_R2D_P TBT_B_R2D_N DP_TBTPB_ML DP_TBTPB_ML DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_TX DP_TX DP_TX DP_TX DP_TX DP_TX DP_TBTPB_ML_C_P DP_TBTPB_ML_C_N DP_TBTPB_ML_P DP_TBTPB_ML_N DP_B_LSX_ML_P DP_B_LSX_ML_N TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBT_B_D2R_C_P TBT_B_D2R_C_N TBT_B_D2R_P TBT_B_D2R_N DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D TBTDP_80D TBTDP_80D DP_AUX DP_AUX DP_AUX DP_AUX DP_AUX DP_AUX TBTDP_RX TBTDP_RX DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_P DP_TBTPB_AUXCH_N DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N Thunderbolt/DP Connector Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TBTDP_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TBTDP_TX TBTDP_TX * TBTDP_TX2TX TBTDP_RX TBTDP_RX * TBTDP_RX2RX TBTDP_TX TBTDP_RX * TBTDP_TX2RX TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TOP,BOTTOM =6x_DIELECTRIC ? TBTDP_RX2RX TOP,BOTTOM =6x_DIELECTRIC ? TBTDP_TX2RX TOP,BOTTOM =10x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TBTDP_TX * TBTDP_TX2RX TBTDP_TX *_TX * TBTDP_2OTHERHS TBTDP_RX *_TX * TBTDP_2OTHERHS TBT_A_D2R1 TBT_A_D2R1 TBT_A_D2R0 TBT_A_D2R0 TABLE_SPACING_RULE_ITEM TBTDP_TX2TX TABLE_SPACING_ASSIGNMENT_ITEM TBTDP_RX TBT_A_AUXCH TBT_A_AUXCH TABLE_SPACING_RULE_ITEM TBTDP_2OTHERHS TOP,BOTTOM =10x_DIELECTRIC ? TBTDP_2OTHER TOP,BOTTOM =6x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TBTDP_TX *_RX * TBTDP_2OTHERHS TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TBTDP_RX *_RX * TBTDP_2OTHERHS TABLE_SPACING_RULE_ITEM TBTDP_TX2TX * =4x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM TBTDP_TX * * TBTDP_2OTHER TBTDP_RX * * TBTDP_2OTHER TABLE_SPACING_RULE_ITEM TBTDP_RX2RX * =4x_DIELECTRIC ? TBTDP_TX2RX * =6x_DIELECTRIC ? TBTDP_2OTHERHS * =6x_DIELECTRIC ? * =4x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TBTDP_2OTHER C NET_TYPE SPACING PHYSICAL TBT_A_R2D TBT_A_R2D TABLE_PHYSICAL_RULE_ITEM LAYER Thunderbolt/DP Net Properties NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page SPACING_RULE_SET TBT_B_D2R TBT_B_D2R TBT_B_AUXCH TBT_B_AUXCH 34 64 34 64 64 64 34 64 34 64 34 64 D 34 64 64 64 64 64 64 64 34 64 34 64 34 64 34 64 34 64 34 64 64 64 64 64 64 64 34 34 34 C 34 Only used on dual-port hosts 34 34 34 34 Thunderbolt IC Net Properties ELECTRICAL_CONSTRAINT_SET B TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L NET_TYPE PHYSICAL SPACING DP_80D DP_80D DP_80D DP_80D DP_TX DP_TX DP_AUX DP_AUX DP_TBTSRC_ML_C_P DP_TBTSRC_ML_C_N DP_TBTSRC_AUXCH_C_P DP_TBTSRC_AUXCH_C_N TBT_SPI_45S TBT_SPI_45S TBT_SPI_45S TBT_SPI_45S TBT_SPI TBT_SPI TBT_SPI TBT_SPI TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L A B Only used on hosts supporting Thunderbolt video-in 34 34 34 34 SYNC_MASTER=J13_CONSTRAINTS SYNC_DATE=01/11/2012 PAGE TITLE Thunderbolt Constraints DRAWING NUMBER Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R BRANCH PAGE 105 OF 109 SHEET 70 OF 73 A PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM ELECTRICAL_CONSTRAINT_SET SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA D NET_TYPE SPACING PHYSICAL SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA 41 44 41 44 41 44 41 44 41 44 41 44 41 44 D 41 44 41 44 41 44 SMBus Charger Net Properties ELECTRICAL_CONSTRAINT_SET SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_DIFFPAIR NET_TYPE SPACING PHYSICAL 1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N 1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N 53 53 53 53 53 53 53 53 C C B B A SYNC_MASTER=J13_CONSTRAINTS SYNC_DATE=01/11/2012 PAGE TITLE SMC Constraints DRAWING NUMBER Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R BRANCH PAGE 106 OF 109 SHEET 71 OF 73 A J11/J13 Specific Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_45S * =1:1_DIFFPAIR SENSE_1TO1_P2MM * =1:1_DIFFPAIR THERM_1TO1_45S * =1:1_DIFFPAIR =45_OHM_SE =45_OHM_SE =45_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR 0.200 MM 0.100 MM =45_OHM_SE =45_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =45_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM D SPKR_DIFFPAIR * SPACING_RULE_SET LAYER =1:1_DIFFPAIR 0.300 MM 0.100 MM =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING * =2:1_SPACING NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE CPU_COMP GND * * =2:1_SPACING ? * =2:1_SPACING ? CPU_VCCSENSE GND * GND_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET GND CLK_PCIE * GND_P2MM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING TABLE_SPACING_ASSIGNMENT_ITEM WEIGHT TABLE_SPACING_RULE_ITEM GND * =STANDARD TABLE_SPACING_ASSIGNMENT_ITEM ? GND PCIE* * GND_P2MM GND SATA* * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT GND_P2MM LAYER * 0.20 MM 1000 PWR_P2MM * 0.20 MM 1000 TBT_THERMD_P TBT_THERMD_N TBT_MLBBOT_THMSNS_P TBT_MLBBOT_THMSNS_N TBTTHMSNS_D2_R_P TBTTHMSNS_D2_R_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE CPU_THERMD_P CPU_THERMD_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE CPUTHMSNS_D2_P CPUTHMSNS_D2_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE SENSE_1TO1_P2MM SENSE CPUVCCIOS0_CS_N CPUVCCIOS0_CS_P SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE SENSE SENSE CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N CPUIMVP_ISUM_R_P CPUIMVP_ISUM_R_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE SENSE SENSE CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N CPUIMVP_ISUMG_R_P CPUIMVP_ISUMG_R_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE SENSE SENSE VCCSAS0_CS_P VCCSAS0_CS_N VCCSAISNS_R_P VCCSAISNS_R_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE SENSE SENSE ISNS_3V3S0_P ISNS_3V3S0_N ISNS_3V3S0_R_P ISNS_3V3S0_R_N TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD LAYER INLET_THMSNS_D1_P INLET_THMSNS_D1_N THERM THERM THERM THERM THERM THERM SPACING_RULE_SET TABLE_SPACING_RULE_ITEM SPACING_RULE_SET THERM THERM THERM_1TO1_45S THERM_1TO1_45S THERM_1TO1_45S THERM_1TO1_45S THERM_1TO1_45S THERM_1TO1_45S GND_P2MM TABLE_SPACING_RULE_ITEM AUDIO THERM_1TO1_45S THERM_1TO1_45S SENSE_DIFFPAIR SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM ? THERM SENSE_DIFFPAIR SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_HEAD WEIGHT TABLE_SPACING_RULE_ITEM SENSE =1:1_DIFFPAIR NET_TYPE PHYSICAL SPACING GND USB* * GND_P2MM GND LVDS* * GND_P2MM SB_POWER CLK_PCIE * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SB_POWER SATA* * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM SB_POWER SATA* * PWR_P2MM C SENSE_1TO1_P2MM SENSE SENSE_1TO1_P2MM SENSE CPUIMVP_ISUMG_P CPUIMVP_ISUMG_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE SENSE_1TO1_P2MM SENSE CPUIMVP_ISUM_P CPUIMVP_ISUM_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE ISNS_HS_COMPUTING_N ISNS_HS_COMPUTING_P SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE ISNS_HS_OTHER_N ISNS_HS_OTHER_P SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE ISNS_1V5_S3_N ISNS_1V5_S3_P SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE ISNS_AIRPORT_N ISNS_AIRPORT_P SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE ISNS_SSD_N ISNS_SSD_P SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_1TO1_45S SENSE SENSE ISNS_LCDBKLT_N ISNS_LCDBKLT_P AUD_DIFF AUD_DIFF 1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR SPKR_DIFFPAIR SPKR_DIFFPAIR AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO SPKRAMP_INR_P SPKRAMP_INR_N MAX98300_R_P MAX98300_R_N SPKRAMP_ROUT_P SPKRAMP_ROUT_N SB_POWER SB_POWER PP3V3_S5 PP3V3_S0 GND GND SENSE_DIFFPAIR SENSE_DIFFPAIR B SPKR_OUT SPKR_OUT 46 47 46 47 47 47 47 D 47 47 47 47 47 47 47 45 59 45 59 45 57 58 45 58 45 45 45 58 45 58 45 45 45 54 45 54 45 45 C 45 61 45 61 45 45 57 58 57 58 57 58 57 58 46 46 46 46 46 56 46 56 37 46 37 46 38 46 38 46 B 46 46 40 51 40 51 51 51 51 52 51 52 7 A SYNC_MASTER=J13_CONSTRAINTS SYNC_DATE=01/11/2012 PAGE TITLE Project Specific Constraints DRAWING NUMBER Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R BRANCH PAGE 108 OF 109 SHEET 72 OF 73 A J11/J13 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 16.2 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DEFAULT TOP,BOTTOM Y =50_OHM_SE =50_OHM_SE DEFAULT ISL2,ISL11 Y =45_OHM_SE =45_OHM_SE DEFAULT ISL3,ISL10 Y =45_OHM_SE =45_OHM_SE DEFAULT ISL4,ISL9 Y =45_OHM_SE =45_OHM_SE DEFAULT * N 100 MM 100 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM D D TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 10 MM MM MM TABLE_PHYSICAL_RULE_ITEM STANDARD * =DEFAULT =DEFAULT =DEFAULT =DEFAULT =DEFAULT =DEFAULT MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP Single-ended Physical Constraints Spacing Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.310 MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 0.100 MM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM 1:1_SPACING * TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE ISL2,ISL11 Y 0.182 MM 0.182 MM 27P4_OHM_SE ISL3,ISL10 Y 0.182 MM 0.182 MM 27P4_OHM_SE ISL4,ISL9 Y 0.182 MM 0.182 MM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT 1x_DIELECTRIC TOP,BOTTOM LAYER 0.071 MM ? 1x_DIELECTRIC ISL3,ISL10 0.053 MM ? 1x_DIELECTRIC ISL4,ISL9 0.050 MM ? 1x_DIELECTRIC * 0.090 MM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE * N 100 MM 100 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 35_OHM_SE TOP,BOTTOM Y 0.195 MM 0.195 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 35_OHM_SE ISL2,ISL11 Y 0.125 MM 0.125 MM 35_OHM_SE ISL3,ISL10 Y 0.125 MM 0.125 MM 35_OHM_SE ISL4,ISL9 Y 0.125 MM 0.125 MM 35_OHM_SE * N 100 MM 100 MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT DEFAULT LAYER * 0.1 MM ? STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? BGA_P2MM * =DEFAULT ? TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD C NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM MEM_CLK * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM C TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.170 MM 0.170 MM 40_OHM_SE ISL2,ISL11 Y 0.096 MM 0.096 MM 40_OHM_SE ISL3,ISL10 Y 0.096 MM 0.096 MM 40_OHM_SE ISL4,ISL9 Y 0.099 MM 0.099 MM 40_OHM_SE * N 100 MM 100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 45_OHM_SE TOP,BOTTOM Y 0.135 MM 0.135 MM 45_OHM_SE ISL2,ISL11 Y 0.075 MM 0.075 MM 45_OHM_SE ISL3,ISL10 Y 0.075 MM 0.075 MM 45_OHM_SE ISL4,ISL9 Y 0.080 MM 0.080 MM 45_OHM_SE * N 100 MM 100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 50_OHM_SE TOP,BOTTOM Y 0.110 MM 0.110 MM 50_OHM_SE * N 100 MM 100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM 55_OHM_SE * N 100 MM 100 MM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD MAXIMUM NECK LENGTH Differential Pair Physical Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 72_OHM_DIFF TOP,BOTTOM Y 0.165 MM 0.165 MM 0.130 MM 0.130 MM 72_OHM_DIFF ISL2,ISL11 Y 0.109 MM 0.109 MM 0.150 MM 0.150 MM 72_OHM_DIFF ISL3,ISL10 Y 0.109 MM 0.109 MM 0.150 MM 0.150 MM 72_OHM_DIFF ISL4,ISL9 Y 0.114 MM 0.114 MM 0.150 MM 0.150 MM 72_OHM_DIFF * N 100 MM 100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF TOP,BOTTOM Y 0.132 MM 0.132 MM 0.130 MM 0.130 MM 80_OHM_DIFF ISL2,ISL11 Y 0.081 MM 0.081 MM 0.115 MM 0.115 MM 80_OHM_DIFF ISL3,ISL10 Y 0.081 MM 0.081 MM 0.115 MM 0.115 MM 80_OHM_DIFF ISL4,ISL9 Y 0.088 MM 0.088 MM 0.110 MM 0.110 MM 80_OHM_DIFF * N 100 MM 100 MM =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM A TABLE_PHYSICAL_RULE_ITEM SYNC_MASTER=J13_CONSTRAINTS SYNC_DATE=01/11/2012 TABLE_PHYSICAL_RULE_ITEM =STANDARD PAGE TITLE PCB Rule Definitions DRAWING NUMBER Apple Inc 051-9277 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.8.0 R BRANCH PAGE 109 OF 109 SHEET 73 OF 73 A ... AP2 AP4 AP7 AP9 AP11 AP17 AP21 AP23 AP25 AP29 AP31 AP33 AP35 AP37 AP41 AP43 AP45 AP48 AP50 AR6 AR8 AR17 AR19 AR21 AR31 AR35 AR37 AT7 AT9 AT11 AT39 AT41 AT43 AT45 AU17 AU37 AV2 AV4 AV48 AV50 AW7... AB48 AB50 AC7 AC9 AC11 AC17 AC25 AC41 AC43 AC45 AE7 AE9 AE11 AE13 AE15 AE17 AE25 AE35 AE41 AE43 AE45 AF2 AF4 AF8 AF19 AF25 AF27 AF29 AF31 AF35 AF48 AF50 AG7 AG9 AG11 AG17 AG19 AG29 AG31 AG35 AG41... VSS AM34 AM38 AM42 AM45 AM48 AM58 D AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP7 AP10 AP51 AP55 AR7 AR13 AR17 AR21 AR41 AR48 AR61 AT4 AT14 AT19 AT36 C AT45 AT52 AT58 AU1 AU7 AU11 AU28