cf328 compal LA 7071p r10

A B ZZZ0 ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 PCB LA-7071P LS-7071P LS-7074P LS-7075P LA-7076P M/B DAZ@ M/B DA@ USB IO/B DA@ HDD/B DA@ LED/B DA@ TP/B DA@ PCB C D E DAZ0I200101 MB USB IO/B HDD/B LED/B TP/B DA60000KP10 DA60000KQ10 DA400011R10 DA400011T10 DA400013910 1 Compal Confidential P1VE6 LA7071P Schematics Document 2 AMD Ontario Processor with DDRIII + Hudson M1 11.6" M/B 2011-03-17 Rev : 1.0 3 4 2010/11/09 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Cover Page Size Document Number Custom Rev 1.0 P1VE6 Schematics Date: Thursday, March 17, 2011 Sheet E of 37 A B C D E Compal Confidential Brazos Platform Model Name : P1VE6 File Name : LA-7071P HDMI RGB LVDS AMD Ontario FT1 Memory Bus (DDRIII) Dual Channel APU 204 Pin DDRIII SO-DIMM x2 1.5V DDRIII 800/1066 BANK 0, 1, 2, 6.4G/8.5G BGA 413-Ball 19mm X 19mm Page , 100M/133M Page 4,5,6 HDMI Conn D-Sub Conn Page 10 Page 11 LVDS Conn UMI x4 Gen.1 Page USB Conn.x2 (Left Side) Port , 2.5GT/s per Lane (Right Side) Port IO/B Fan Circuit PWM Page 25 Camera Bluetooth Port Port Page Card Reader RTS 5138 Port Page 20 Page 19 Page 27 PCI-Express X3 100MHz Port PCIE Gen1 2.5GT/S Port WWAN WLAN JMINI1 JMINI2 Media processor Port USB Conn.x1 Wireless Card Port Page 20 Page 21 USB AMD Hudson M1 HD Audio FCH Port LAN(10/100) 3.3V 48MHz SATA 3.3V 24MHz Gen1 1.5GT/S ,Gen2 3GT/S 3G Card 100MHz BGA 605-Ball 23mm X 23mm Port 3, Page 20 Page 12 ~ 16 AR8158 SIM Card HDD Port Page 18 (2.5") Port LPC Port Page 20 Page 22 33MHz 3 RJ-45 WLAN Page 18 Port ENE KB930 Page 21 Small Board Page 26 IO/B HDD/B LS-7071P HDA Codec+AMP LS-7074P CX20584 Page 17 RTC Ckt LED/B Page 12 TP BTN/B LS-7072P BIOS ROM LS-7073P HP Jack x1 MIC Jack x1 2MB Power Button Page 27 IO/B Page 23 Page 28 A 2010/11/09 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification DC/DC Interface Ckt 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C D Title Block Diagrams Size B Date: Document Number Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet E of 37 C Voltage Rails Power Plane Description S1 VIN Adapter power supply (19V) N/A B+ AC or battery power rail for power circuit N/A S5 FCH Hudson-M1 USB Port List N/A N/A USB1.1 N/A N/A S3 +APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF +APU_CORE_NB 1.0V switched power rail ON OFF OFF +1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF +0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF +1.05VS 1.05V switched power rail for NB VDDC & VGA ON OFF OFF +1.1VS 1.1VS switched power rail ON OFF OFF +1.8VS 1.8V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +1.1VALW 1.1V always on power rail ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +1.5VS 1.5VS switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCBATT RTC power ON ON ON EC SM Bus1 address Address HEX Device Address HEX Smart Battery 0001-011xb 16H SB-TSI 1001-100xb 98H SM Bus Controller Device * SM Bus Controller Device NC (FCH_SMB0) Address HEX 1001-000xb 90 PCIE1 PCIE2 NC HDD SATA1 NC SATA2 PCIE3 NC SATA3 NC Port0 Left conn PCIE0 NC SATA4 NC Port1 Left conn PCIE1 WWAN SATA5 NC Port2 Right conn PCIE2 LAN Port3 WWAN PCIE3 WLAN Port4 SIM Port5 USB Camera Port6 CardReader Port7 BT Port8 WiMax Port9 WWAN Port10 NC Port11 NC Port12 NC Port13 NC Board ID H_THERMTRIP# (FCH_ALERT#) DDR DIMM1 (FCH_SMB0) NC Port1 Vcc Ra HEX APU SIC/SID (FCH_SMB3) Port0 SATA0 Board ID / SKU ID Table for AD channel (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#) Address PCIE0 FCH Hudson-M1 SATA Port List EC SM Bus2 address Device E Brazos PCIE Port List USB2.0 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF D APU B FCH A +3VALW 100K +/- 5% Rb 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V PCB Revision 0.1 0.2 SMBUS Control Table Source BATT EC_SMB_CK1 EC_SMB_DA1 KB930 V EC_SMB_CK2 EC_SMB_DA2 KB930 HDMI_DATA HDMI_CLK APU FT1 EDID_DATA EDID_CLK APU FT1 FCH_SMDAT0 FCH_SMCLK0 FCH M1 BOM Structure HDMI@ : BT@ : CONN@ : 45@ : 3G@ : N3G@ : CMBS@ : NCMBS@: HDMI function BT function Connetors 45 Level 3G function None 3G function Combo Jack POPO noise Solution None Combo Jack POPO noise Solution DIMM MINI Card LCD DDC ROM APU V V V 2010/11/09 Issued Date V V Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A HDMI DDC ROM B C D Title Notes List Size B Date: Document Number P1VE6 Schematics Thursday, March 17, 2011 Sheet E of 37 Rev 1.0 APU C50 P/N change to SA00004KD50 Tock 2010/12/30 R9 * SA00004KD50 @ @ mount 1 1 2 2 HDMI_DATA HDMI_CLK APU_PROCHOT# APU_ALERT#_R APU_SIC APU_SID 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% @ C435 100P_0402_50V8J Power Circuit @ EC_PROCHOT# @ 0_0402_5% APU_PROCHOT# Power Circuit 0_0402_5% Power Circuit TDP1_TXP2 TDP1_TXN2 C4 C5 1 2 1U_0402_16V7K 1U_0402_16V7K HDMI_CLKP_C HDMI_CLKN_C A10 B10 TDP1_TXP3 TDP1_TXN3 LVDS_A2 LVDS_A2# B5 A5 LTDP0_TXP0 LTDP0_TXN0 LVDS_A1 LVDS_A1# D6 C6 LTDP0_TXP1 LTDP0_TXN1 LVDS_A0 LVDS_A0# A6 B6 LVDS_ACLK LVDS_ACLK# D8 C8 D2 D1 APU_SVC APU_SVD APU_SIC APU_SID CLKIN_H CLKIN_L DISP_CLKIN_H DISP_CLKIN_L SVC SVD P3 P4 SIC SID APU_PROCHOT# U1 APU_THERMTRIP# U2 APU_ALERT#_R T2 R24 @ 0_0402_5% R26 @ 0_0402_5% APU_TDI N2 APU_TDO need to pull-down N1 APU_TCK P1 APU_TMS P2 APU_TRST# M4 APU_DBRDY M3 Close to APU APU_DBREQ# M1 F4 G1 F3 APU_VDDNB_RUN_FB_H APU_VDD0_RUN_FB_H LTDP0_TXP3 LTDP0_TXN3 J1 J2 T3 T4 LDT_RST# APU_PWRGD LTDP0_TXP2 LTDP0_TXN2 APU_VDD0_RUN_FB_L R379 0_0402_5% F1 APU_VDDNB_RUN_FB_L R380 0_0402_5% B4 W11 V5 DP MISC D10 C10 PROCHOT_L THERMTRIP_L ALERT_L TDI TDO TCK TMS TRST_L DBRDY DBREQ_L R1 H3 DP_BLON DP_DIGON DP_VARY_BL G2 H2 H1 TDP1_AUXP TDP1_AUXN B2 C2 TDP1_HPD C1 LTDP0_AUXP LTDP0_AUXN A3 B3 EDID_CLK EDID_DATA LTDP0_HPD D3 LTDP0_HPD DAC_RED DAC_REDB DAC_GREEN DAC_GREENB DAC_BLUE DAC_BLUEB DAC_HSYNC DAC_VSYNC DAC_SCL DAC_SDA DAC_ZVSS RESET_L PWROK DP_ZVSS DP_ZVSS TEST4 TEST5 TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST25_H TEST25_L TEST28_H TEST28_L TEST31 TEST33_H TEST33_L TEST34_H TEST34_L TEST35 TEST36 TEST37 VDDCR_NB_SENSE VDDCR_CPU_SENSE VDDIO_MEM_S_SENSE C12 D13 A12 B12 A13 B13 APU_ENBKL APU_ENVDD APU_BLPWM HDMI_CLK HDMI_DATA 8/25 Pull-up 100k(@ R352) to +3VS on LTDP0_HPD for eDP HDMI_DET R12 EDID_CLK EDID_DATA R9 R18 CRT_DDC_CLK CRT_DDC_DATA D12 DAC_ZVSS R19 499_0402_1% TEST15 R20 1K_0402_5% TEST18 TEST19 TEST25_H TEST_25_L R21 R22 R25 1 1K_0402_5% 1K_0402_5% 510_0402_1% 10/01 Remove T1,T3~T7,T11,T12,T31,T32 TEST31 TEST33_H TEST33_L TEST35 TEST36 TEST37 PAD T8 C9 C10 R30 0.1U_0402_16V4Z 0.1U_0402_16V4Z @ PAD T13 R386 C R28 R29 51_0402_1% 51_0402_1% 1 1K_0402_5% 1K_0402_5% +1.8VS 9/9 Add R386 (1k@) to +1.8VS on TEST35 VSS_SENSE TEST38 DMAACTIVE_L RSVD_1 RSVD_2 RSVD_3 9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend) K3 T1 ALLOW_STOP# R31 1K_0402_5% +1.8VS ALLOW_STOP# @ 8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P DMIC_CLK CRT_HSYNC CRT_VSYNC F2 D4 C438 100P_0402_50V8J Reserve C438 for ALLOW_STOP# Michael 2010/11/18 E Q1 B H_THERMTRIP# C 0_0402_5% DMIC_CLK Reserve R389 for eDP function Tock 2010/12/30 B APU_THERMTRIP# +3VS 100K_0402_5% R389 DAC_BLU 150_0402_1% 100K_0402_5% DAC_GRN 150_0402_1% @ eDP@ DAC_RED 150_0402_1% R15 R352 1K_0402_5% B D HDMI_CLK HDMI_DATA E1 E2 R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5 eDP 150_0402_1% S IC ONTARIO CMC50AFPB22GT 1G BGA ABO! 9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L R32 10K_0402_5% HDMI_TX0P_C HDMI_TX0N_C T14PAD +3VS R33 1U_0402_16V7K 1U_0402_16V7K DISP_CLK DISP_CLK# Add C429 for APU_PROCHOT# Michael 2010/11/18 2 APU_ALERT#_FCH APU_ALERT#_EC R27 1 V2 V1 Connection to EC, FCH input R23 C7 C8 APU_CLK APU_CLK# C434 100P_0402_50V8J C429 100P_0402_50V8J FCH_PROCHOT# TDP1_TXP1 TDP1_TXN1 9/15 Change R24 from mount to @ B9 A9 9/9 Change R24 from @ to mount R26 from mount to @ APU_PROCHOT# HDMI_TX1P_C HDMI_TX1N_C LDT_RST# APU_SIC @ 1U_0402_16V7K 1U_0402_16V7K C432 100P_0402_50V8J 10/05 Add 100p(C405) on LDT_RST# C 2 APU_SID 2 100P_0402_50V8J 1 Reserve C432, C433, C434, C435 Michael 2010/11/18 Change R10, R11 to RP1 Michael 2010/12/23 C405 C2 C3 TDP1_TXP0 TDP1_TXN0 VGA DAC 10K_0402_5% 10K_0402_5% A8 B8 TEST R13 R14 R16 R17 1 HDMI_TX2P_C HDMI_TX2N_C DISPLAYPORT R10 R11 HDMI_CLKP HDMI_CLKN 1U_0402_16V7K 1U_0402_16V7K CLK APU_SVC @ +3VS HDMI_TX1P HDMI_TX1N HDMI_TX0P HDMI_TX0N TEST_25_L TEST36 510_0402_1% 1K_0402_5% 1 C433 100P_0402_50V8J 2 SER R8 R6 APU_SVC APU_SVD 1K_0402_5% 1K_0402_5% 1 1 CTRL R3 R4 C1 C6 JTAG D HDMI_TX2P HDMI_TX2N DISPLAYPORT APU_SVD @ LVDS mount U1B +1.8VS Display R352 MMBT3904_NL_SOT23-3 R34 @ +1.8VS 0_0402_5% 9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32 If FCH internal pull-up disabled, level-shifter could be deleted Need BIOS to disable internal pull-up!! +3VS 9/20 Delete R41~R43 AMD Debug 2N7002DW-T/R7 Vgs(th): 1.0V Typ 1.6V Max 2.0V R39 10K_0402_5% @ R37 1K_0402_5% APU_TDI R38 1K_0402_5% APU_TMS R36 1K_0402_5% APU_TCK R35 1K_0402_5% APU_PWRGD R5 300_0402_5% LDT_RST# R7 300_0402_5% R2 300_0402_5% APU_PWRGD If Q8 or R429, R432 implemented, EC side pull-up need to be mounted C421 100P_0402_50V8J @ T29PAD G APU_TRST# APU_TDO DMN66D0LDW-7_SOT363-6 APU_SID D S A @ EC_SMB_DA Q2A R49 R47 R48 @ 0_0402_5% 0_0402_5% FCH_SID EC_SMB_DA2 FCH_SID EC_SMB_DA2 T30PAD Reserve C421 for APU_PWRGD Michael 2010/11/18 T0 FCH TO EC APU_DBRDY APU_DBREQ# A 0_0402_5% G 8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6) DMN66D0LDW-7_SOT363-6 S D APU_SIC @ Q2B R52 EC_SMB_CK R50 R51 @ FCH_SIC 0_0402_5% EC_SMB_CK2 0_0402_5% FCH_SIC EC_SMB_CK2 T0 FCH TO EC Compal Secret Data Security Classification 2010/11/09 Issued Date 2012/11/09 Deciphered Date Compal Electronics, Inc FT1 CTRL/DP/CRT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 0_0402_5% Title Size Document Number Custom Date: Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet of 37 B C DDR_A_D[0 63] DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_MA[0 15] DDR_A_DM[0 7] DDR_A_DM[0 7] U1E R18 T18 F16 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 A16 B16 B20 A20 E23 E22 J22 J23 R22 P22 W22 V22 AC20 AC21 AB16 AC16 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 M17 M16 M19 M18 N18 N19 L18 L17 DDR_CKE0 DDR_CKE1 DDR_CKE0 DDR_CKE1 D15 B19 D21 H22 P23 V23 AB20 AA16 DDR_RST# DDR_EVENT# DDR_RST# DDR_EVENT# DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB# F15 E15 DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1 W19 V15 U19 W15 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB# T17 W16 U17 V16 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# L23 N17 U18 V19 V17 M_ADD0 M_ADD1 M_ADD2 M_ADD3 M_ADD4 M_ADD5 M_ADD6 M_ADD7 M_ADD8 M_ADD9 M_ADD10 M_ADD11 M_ADD12 M_ADD13 M_ADD14 M_ADD15 M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 DDR SYSTEM MEMORY R17 H19 J17 H18 H17 G17 H15 G18 F19 E19 T19 F17 E18 W17 E16 G15 M_BANK0 M_BANK1 M_BANK2 M_DM0 M_DM1 M_DM2 M_DM3 M_DM4 M_DM5 M_DM6 M_DM7 M_DQS_H0 M_DQS_L0 M_DQS_H1 M_DQS_L1 M_DQS_H2 M_DQS_L2 M_DQS_H3 M_DQS_L3 M_DQS_H4 M_DQS_L4 M_DQS_H5 M_DQS_L5 M_DQS_H6 M_DQS_L6 M_DQS_H7 M_DQS_L7 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_CLK_H0 M_CLK_L0 M_CLK_H1 M_CLK_L1 M_CLK_H2 M_CLK_L2 M_CLK_H3 M_CLK_L3 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_RESET_L M_EVENT_L M_CKE0 M_CKE1 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63 M0_ODT0 M0_ODT1 M1_ODT0 M1_ODT1 M0_CS_L0 M0_CS_L1 M1_CS_L0 M1_CS_L1 B14 A15 A17 D18 A14 C14 C16 D16 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 C18 A19 B21 D20 A18 B18 A21 C20 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 C23 D23 F23 F22 C22 D22 F20 F21 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 H21 H23 K22 K21 G23 H20 K20 K23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 N23 P21 T20 T23 M20 P20 R23 T22 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 V20 V21 Y23 Y22 T21 U23 W23 Y21 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 M23 +MEM_VREF M22 +M_ZVDDIO E 8/22 Delete C11~C18 (No VGA) 9/6 Change PCI-E from FCH to APU 9/6 Update PCI-E port List 9/15 Change PCI-E from APU to FCH U1A AA6 Y6 AB4 AC4 AA1 AA2 Y4 Y3 +1.05VS R53 2K_0402_1% P_ZVDD_10 Y14 P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3 P_GPP_TXP0 P_GPP_TXN0 PCIE I/F DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 D P_ZVDD_10 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3 P_ZVSS AB6 AC6 AB3 AC3 Y1 Y2 V3 V4 AA14 P_ZVSS R54 1.27K_0402_1% Less than 1" Less than 1" AA12 Y12 UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N AA10 Y10 UMI_RX2P UMI_RX2N AB10 AC10 UMI_RX3P UMI_RX3N AC7 AB7 P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3 P_UMI_TXP0 P_UMI_TXN0 UMI I/F A P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3 AB12 AC12 UMI_TX0P_C UMI_TX0N_C C19 C20 1 2 1U_0402_16V7K 1U_0402_16V7K AC11 AB11 UMI_TX1P_C UMI_TX1N_C C21 C22 1 2 1U_0402_16V7K 1U_0402_16V7K AA8 Y8 UMI_TX2P_C UMI_TX2N_C C23 C24 1 2 1U_0402_16V7K 1U_0402_16V7K AB8 AC8 UMI_TX3P_C UMI_TX3N_C C25 C26 1 2 1U_0402_16V7K 1U_0402_16V7K UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N S IC ONTARIO CMC50AFPB22GT 1G BGA ABO! M_VREF M_RAS_L M_CAS_L M_WE_L R55 M_ZVDDIO_MEM_S S IC ONTARIO CMC50AFPB22GT 1G BGA ABO! +1.5V 39.2_0402_1% 9/11 Delete DDR Signal link to JDIMM2 Reserve C439 for DDR_EVENT# Michael 2010/11/18 1K_0402_5% @ 1 R56 1K_0402_1% DDR_EVENT# +MEM_VREF R57 1 C439 100P_0402_50V8J R58 1K_0402_1% C27 C28 1 +1.5V +1.5V 1000P_0402_50V7K 0.1U_0402_16V4Z Place within 1000 mils to APU 20100526 Compal Secret Data Security Classification Issued Date 2010/11/09 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc FT1 DDRIII/UMI/PCIE Size Document Number Custom Date: Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet E of 37 +APU_CORE +1.8VS 4500 mA + 10U_0603_6.3V6M 1U_0402_6.3V6K C40 1U_0402_6.3V6K C39 1U_0402_6.3V6K C38 1U_0402_6.3V6K C37 180P_0402_50V8J C35 1U_0402_16V7K C36 10U_0603_6.3V6M 1U_0402_6.3V6K C51 1 FBMA-L11-201209-221LMA30T_0805 8/25 Change +1.0VS to +1.05VS +1.05VS L3 2 10U_0603_6.3V6M 1U_0402_6.3V6K C60 1U_0402_16V7K C59 L4 +VDD_10 2 2 FBMA-L11-201209-221LMA30T_0805 +3VS 500 mA A4 VDD_33 10U_0603_6.3V6M C67 1U_0402_6.3V6K C66 1U_0402_6.3V6K C65 1U_0402_16V7K C64 U13 W13 V12 T12 VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4 FBMA-L11-201209-221LMA30T_0805 10U_0603_6.3V6M C57 5500 mA +VDD_33 1 R333 0_0603_5% VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSSBG_DAC N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11 D C S IC ONTARIO CMC50AFPB22GT 1G BGA ABO! 8/22 Reserve R333 ( ohm 0603 ) C91 1U_0402_6.3V6K C90 C83 10U_0603_6.3V6M B 2 C98 C97 1 180P_0402_50V8J C96 180P_0402_50V8J 9/15 Change C99,C100 to 470U(SGA00003K00) POWER +APU_CORE SGA00003K00 8/22 Change C111~C113 from E-Cap to Poly-Cap (SGA20331E10) 8/25 Change C111 from poly-cap to E-cap (SF000002Z00) By case (Along split) 9/11 Change C111 to SGA20331E10 +1.5V + C114 330U_D2_2V_Y C117 SGA20331E10 Near CPU Socket SGA20331E10 10U_0603_6.3V6M Near CPU Socket @ 2 2 Compal Secret Data Security Classification Issued Date 2010/11/09 Deciphered Date 2012/11/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 2 C110 A Compal Electronics, Inc P07-FT1 PWR/VSS Size C Date: SGA20331E10 Near CPU Socket change C99,C100 from 470U to 330U , 2011/01/28 Tock change C99,C100 footprint from C_D2 to C_X for placement C109 C108 C107 180P_0402_50V8J C112 330U_D2_2V_Y C116 + 180P_0402_50V8J + C115 C111 330U_D2_2V_Y 22U_0805_6.3V6M 1 180P_0402_50V8J A 180P_0402_50V8J +1.8VS Near CPU Socket +APU_CORE_NB C106 +1.5V POWER C105 POWER 1U_0402_16V7K C104 330U_D2_2V_Y C102 @ 10U_0603_6.3V6M 1U_0402_16V7K C100 C103 330U_D2_2V_Y + 1U_0402_16V7K C99 1U_0402_16V7K 10U_0603_6.3V6M 1U_0402_16V7K C95 SGA00004L00 + 1U_0402_16V7K L2 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 C93 220U_D2_2VY_R15M C94 2 U1D A7 B7 B11 B17 B22 C4 D5 D7 D9 D11 D14 B15 D17 D19 E7 E9 E12 E20 F8 F11 F13 G4 G5 G7 G9 G12 G20 G22 H6 H11 H13 J4 J5 J7 J20 K10 K14 L4 L6 L8 L11 L13 L20 L22 M7 N4 N6 N8 N11 9/20 Change C93 to SGA00004L00 1U_0402_16V7K C92 @ 10U_0603_6.3V6M +1.05VS 1U_0402_6.3V6K C89 1U_0402_6.3V6K 1 +1.5V B POWER +VDDL_10 C82 10U_0603_6.3V6M C81 180P_0402_50V8J 180P_0402_50V8J C80 C79 C88 2 1U_0402_6.3V6K 1 1U_0402_6.3V6K C78 C87 1U_0402_6.3V6K 1U_0402_16V7K 1U_0402_6.3V6K C77 C86 1U_0402_16V7K 1U_0402_6.3V6K C76 C85 1 1U_0402_16V7K 1U_0402_6.3V6K C75 C84 1 1U_0402_16V7K C34 C49 U11 VDDPL_10 S IC ONTARIO CMC50AFPB22GT 1G BGA ABO! 180P_0402_50V8J C50 1U_0402_16V7K C63 VDDIO_MEM_S_1 VDDIO_MEM_S_2 VDDIO_MEM_S_3 VDDIO_MEM_S_4 VDDIO_MEM_S_5 VDDIO_MEM_S_6 VDDIO_MEM_S_7 VDDIO_MEM_S_8 VDDIO_MEM_S_9 VDDIO_MEM_S_10 VDDIO_MEM_S_11 W = 15 mil / Spcae = 20 mil DP Phy/IO G16 G19 E17 J16 L16 L19 N16 R16 R19 W18 U16 2 1U_0402_6.3V6K C72 C71 10U_0603_6.3V6M 10U_0603_6.3V6M C70 10U_0603_6.3V6M C69 10U_0603_6.3V6M C68 1 DDR3 10U_0603_6.3V6M +VDD_18_DAC POWER +1.5V C VDD_18_DAC PCIE/IO/DDR3 Phy 2000 mA +1.8VS W9 180P_0402_50V8J C58 +APU_CORE_NB VDDCR_NB_1 VDDCR_NB_2 VDDCR_NB_3 VDDCR_NB_4 VDDCR_NB_5 VDDCR_NB_6 VDDCR_NB_7 VDDCR_NB_8 VDDCR_NB_9 VDDCR_NB_10 VDDCR_NB_11 VDDCR_NB_12 VDDCR_NB_13 VDDCR_NB_14 VDDCR_NB_15 VDDCR_NB_16 VDDCR_NB_17 VDDCR_NB_18 VDDCR_NB_19 VDDCR_NB_20 VDDCR_NB_21 VDDCR_NB_22 W = 20 mil / Spcae = 20 mil +APU_CORE_NB E8 E11 E13 F9 F12 G11 G13 H9 H12 K11 K13 L10 L12 L14 M11 M12 M13 N10 N12 N14 P11 P13 C61 8000 mA 180P_0402_50V8J C62 10U_0603_6.3V6M C33 C48 180P_0402_50V8J U8 W8 U6 U9 W6 T7 V7 VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6 VDD_18_7 C73 VDDCR_CPU_1 VDDCR_CPU_2 VDDCR_CPU_3 VDDCR_CPU_4 VDDCR_CPU_5 VDDCR_CPU_6 VDDCR_CPU_7 VDDCR_CPU_8 VDDCR_CPU_9 VDDCR_CPU_10 VDDCR_CPU_11 VDDCR_CPU_12 VDDCR_CPU_13 VDDCR_CPU_14 VDDCR_CPU_15 1U_0402_16V7K C74 10U_0603_6.3V6M C30 C47 C56 180P_0402_50V8J C42 10U_0603_6.3V6M 10U_0603_6.3V6M C41 2 E5 E6 F5 F7 G6 G8 H5 H7 J6 J8 L7 M6 M8 N7 R8 1U_0402_16V7K 1U_0402_6.3V6K C46 C55 1U_0402_16V7K C32 10U_0603_6.3V6M 1U_0402_6.3V6K C45 C54 1U_0402_16V7K C29 10U_0603_6.3V6M 1U_0402_6.3V6K C44 C53 1 DIS PLL 2 1U_0402_16V7K 10U_0603_6.3V6M C31 C43 C52 1 GPU AND NB CORE 2 DAC 1 L1 FBMA-L11-201209-221LMA30T_0805 GND CPU CORE 1 1U_0402_6.3V6K 1U_0402_16V7K +VDD_18 TSense/PLL/DP/PCIE/IO D 2000 mA U1C +APU_CORE Document Number Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet of 37 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 R396 DDR_CKE0 100_0402_1% C DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA# DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 B DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 R63 10K_0402_5% R64 10K_0402_5% 2 0.1U_0402_16V4Z C139 A C138 +3VS 2.2U_0603_6.3V6K DDR_A_DM7 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT 205 207 GND1 BOSS1 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 GND2 BOSS2 206 208 R60 1K_0402_1% DDR_A_D6 DDR_A_D7 +VREF_CA DDR_A_DM1 DDR_RST# 2 D R61 1K_0402_1% C413 100P_0402_50V8J R62 1K_0402_1% @ Reserve C413 for DDR_RST# Michael 2010/11/18 +VREF_DQ DDR_RST# DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 9/23 Reserve R396,R397 on CKE0 & CKE1(S3 hang Issue) DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 +1.5V R397 100_0402_1% DDR_A_MA15 DDR_A_MA14 DDR_CKE1 0.1U_0402_16V4Z DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 0.1U_0402_16V4Z C120 C121 0.1U_0402_16V4Z C122 C123 0.1U_0402_16V4Z 0.1U_0402_16V4Z C124 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C125 C126 @ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C127 @ C128 @ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C129 @ C130 @ 0.1U_0402_16V4Z C C131 @ 10/11 Change R396 R397 from @ to mount (For A1 APU,B0 APU no Need) DDR_A_MA2 DDR_A_MA0 9/11 Change C137 to SGA00004L00 DDR_A_CLK1 DDR_A_CLK#1 CRB 0.1u X1 DDR_A_BS1 DDR_A_RAS# +VREF_CA DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 W=20mil @ CRB 100U X2 +0.75VS DDR_A_ODT1 DDR_A_D36 DDR_A_D37 4.7u X1 +1.5V DDR_CS0_DIMMA# DDR_A_ODT0 2 1 + @ C137 220U_6.3V_M B Place near JDIMM1 SGA00004L00 DDR_A_DQS#5 DDR_A_DQS5 change C137 to SF000002Y00 2010/12/14 Tock DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 8/25 Change C137 from poly-cap to E-cap (SF000002Y00) 8/25 Reserve C381 E-cap (SF000002Y00) on +1.5V DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 9/11 Remove C381 +0.75VS DDR_EVENT# FCH_SMDAT0 FCH_SMCLK0 A 100 mA FOX_AS0A621-U4RG-7H Compal Secret Data Security Classification 2010/11/09 Issued Date 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC R59 1K_0402_1% DDR_A_DQS#0 DDR_A_DQS0 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_A_DM[0 7] +1.5V 4.7U_0603_6.3V6K DDR_A_D10 DDR_A_D11 DDR_A_DM[0 7] +1.5V DDR_A_DQS#1 DDR_A_DQS1 C136 DDR_A_D8 DDR_A_D9 DDR_A_D[0 63] DDR_A_MA[0 15] 0.1U_0402_16V4Z DDR_A_D2 DDR_A_D3 DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_D4 DDR_A_D5 C135 DDR_A_DM0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 0.1U_0402_16V4Z DDR_A_D0 DDR_A_D1 CONN@ C134 C119 1000P_0402_50V7K D 0.1U_0402_16V4Z C118 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 0.1U_0402_16V4Z JDIMM1 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Change JDIMM1 socket to SP07000NN00 2010/12/06 Tock Change JDIMM1 socket to SP07000NZ00 2010/12/14 Tock C133 W=20mil +VREF_DQ 3500 mA +1.5V 1000P_0402_50V7K +1.5V C132 Title Compal Electronics, Inc DDR3 SODIMM-I Socket Size Document Number Custom Date: Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet of 37 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 @ R421 DDR_CKE0 C DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_B_CLK2 DDR_B_CLK#2 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMB# DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 B DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 R131 @ @ 0.1U_0402_16V4Z C159 C158 @ 2.2U_0603_6.3V6K +3VS A 10K_0402_5% DDR_A_D58 DDR_A_D59 @ R130 10K_0402_5% +3VS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 G1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 DDR_A_DM[0 7] DDR_A_DM[0 7] DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 D DDR_A_D12 DDR_A_D13 DDR_A_DM1 DDR_RST# DDR_A_D14 DDR_A_D15 DDR_RST# DDR_A_D20 DDR_A_D21 Reserve C414 for DDR_RST# Michael 2010/11/18 @ DDR_A_DM2 C414 100P_0402_50V8J DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 +1.5V @ R401 100_0402_1% DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 0.1U_0402_16V4Z 2 DDR_CKE1 100_0402_1% DDR_A_MA15 DDR_A_MA14 C167 @ 0.1U_0402_16V4Z C145 @ 0.1U_0402_16V4Z C141 @ 0.1U_0402_16V4Z C144 @ 0.1U_0402_16V4Z C143 @ 0.1U_0402_16V4Z C150 @ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C154 @ C151 @ 0.1U_0402_16V4Z C149 @ 0.1U_0402_16V4Z C157 @ 0.1U_0402_16V4Z C C155 @ 9/23 Reserve R421,R401 on CKE0 & CKE1(S3 hang Issue) 10/11 Change R421 R401 from @ to mount (For A1 APU,B0 APU no Need) DDR_A_MA2 DDR_A_MA0 DDR_B_CLK3 DDR_B_CLK#3 CRB 0.1u X1 4.7u X1 DDR_A_BS1 DDR_A_RAS# +0.75VS DDR_CS0_DIMMB# DDR_B_ODT0 DDR_B_ODT1 +VREF_CA DDR_A_D36 DDR_A_D37 DDR_A_DM4 @ DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 @ W=20mil @ @ @ B Place near JDIMM2 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 +0.75VS DDR_EVENT# FCH_SMDAT0 FCH_SMCLK0 A 206 G2 100 mA FOX_AS0A621-U4SG-7H Compal Secret Data Security Classification 2010/11/09 Issued Date 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 0.1U_0402_16V4Z 2 C140 @ C152 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D4 DDR_A_D5 4.7U_0603_6.3V6K DDR_A_D8 DDR_A_D9 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 0.1U_0402_16V4Z DDR_A_D2 DDR_A_D3 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 C153 DDR_A_DM0 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 0.1U_0402_16V4Z @ DDR_A_D0 DDR_A_D1 Change JDIMM2 socket to SP07000NZ00 for reverse 2010/12/06 Tock DDR_A_D[0 63] Change JDIMM2 socket to SP07000NN00 DDR_A_MA[0 15] 2010/12/14 Tock C148 @ D 1000P_0402_50V7K C160 C166 0.1U_0402_16V4Z +VREF_DQ CONN@ 0.1U_0402_16V4Z JDIMM2 3500 mA C147 +1.5V 1000P_0402_50V7K +1.5V W=20mil C146 Title Compal Electronics, Inc DDR3 SODIMM-II Socket Size Document Number Custom Date: Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet of 37 Camera 11/02 Change Q3 PN to SB934130020 LCD POWER CIRCUIT J1 +LCDVDD Q3 +LCDVDD +3VS +3VS AO3413L_SOT23-3 +LCDVDD_R C165 100K_0402_5% W=40mils R68 G 2 R69 USB20_N5_1 USB20_P5_1 4 USB20_N5 USB20_P5 USB20_P5 R72 0_0402_5% Change C163 BOM Struture to @ Michael 2010/11/18 USB20_N5 D @ WCM2012F2S-900T04_0805 Remove C164 4.7U Michael 2010/11/18 C163 @ C161 0.1U_0402_16V4Z 2 0.047U_0402_16V4Z D Q32A DMN66D0LDW-7_SOT363-6 4.7U_0603_6.3V6K 0.1U_0402_16V4Z C162 470_0402_5% +CAM_VCC 2 JUMP_43X39 @ W=40mils L5 G D S D W=40mils +3VALW R67 R71 0_0402_5% 2011/02/11 Change Q3 PN to SB000006R10 9/15 Remove D1 L5 R71 R72 C166 C167 for layout spacing 9/23 Remove D1 C166 C167 9/23 Add D1 L5 R71 R72 C166 C167 for ESD 9/24 Swap L5 4.7K_0402_5% S 8/31 Change R68.2 link to +3VALW 8/26 Change Q4 Q5 to Q32A Q32B (SB00000DH00) Standard Part D Q32B DMN66D0LDW-7_SOT363-6 G APU_ENVDD S R70 100K_0402_5% 8/26 Change Q3 to SB934130020 Standard Part C C 9/9 Reserve 100k PD to GND on INVTPWM 9/17 Change R387 from @ to mount 10/04 Add 100p(C401) on INVT_PWM 100K_0402_5% CMOS & LCD/PANEL BD Conn R387 INVTPWM DMIC 8/25 JLVDS1.5 change to INT_MIC0 JLVDS1.6 change to GNDA ohm for +3VS_MIC Add R344 Michael 2010/11/18 0_0402_5% 0_0402_5% @ R310 INVT_PWM EC R311 APU_BLPWM APU 8/31 Update JLVDS1 Pin definition Delete R74 R76 GND1 GND2 GND3 GND4 GND5 GND6 8/22 Reserve R327~R332( ohm) for eDP +3VS 8/31 Reserve R353 R354 on LVDS_ACLK camera +CAM_VCC W=20mil DMIC_CLK DMIC_DATA DMIC LVDS_ACLK LVDS_ACLK# 0_0402_5% 0_0402_5% LVDS@ R327 LVDS@ R328 LVDS_A2 LVDS_A2# LVDS@ R329 LVDS@ R330 LVDS@ R331 LVDS@ R332 0_0402_5% 0_0402_5% LVDS@ R381 LVDS@ R382 9/7 Reserve R381,R382( ohm)R383(100k@) for eDP 0_0402_5% R334 +LCDVDD 2 L6 FBMA-L11-201209-221LMA30T_0805 L7 LVDS_A0 LVDS_A0# STARC_107K30-000001-G2 W=20mil C168 220P_0402_50V7K 3G@ EDID_DATA EDID_CLK R381 DA2 PJDLC05C_SOT23-3 R382 eDP@ eDP@ SE070104Z80 eDP@ ohm 0.1uF R381 ohm 0.1uF R382 ohm @ 0.1uF 100k ohm R73 2.2k ohm @ R75 2.2k ohm 100k ohm CA55 22P_0402_50V8J CA56 22P_0402_50V8J 9/3 Pull-Down 10k(R377) to GND on BKOFF# R377 A 10K_0402_5% 2010/11/09 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z eDP@ R328 R328 0.1uF DMIC_DATA @ C171 100P_0402_50V8J 3G@ BKOFF# R327 ohm B DMIC_CLK A change JLVDS1 to SP010011S00 2010/12/14 Tock R327 R383 For RF W=20mil FBMA-L11-201209-221LMA30T_0805 C169 1000P_0402_50V7K 3G@ 8/22 Reserve R334(0402 ohm) B+ C170 330P_0402_50V7K 3G@ SD028100380 BKOFF# +3VS eDP INVT_PWM BKOFF# LVDS eDP@ LVDS_A1 LVDS_A1# EDID_DATA EDID_CLK Display eDP@ 100K_0402_5% LVDS@ R353 LVDS@ R354 0_0402_5% 0_0402_5% * R75 100K_0402_5% R383 EDID_DATA_R 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% EDID_CLK_R LVDS@ 1 R344 2 0_0402_5% B CONN@ +3VS_MIC 1 USB20_P5_1 2 USB20_N5_1 3 4 DMIC_CLK 5 DMIC_DATA 6 7 LVDS_ACLK_R 8 LVDS_ACLK#_R 9 10 10 LVDS_A2_R 11 11 LVDS_A2#_R 12 12 13 13 LVDS_A1_R 14 14 LVDS_A1#_R 15 15 16 16 LVDS_A0_R 17 17 LVDS_A0#_R 18 18 19 19 EDID_DATA_R 20 20 EDID_CLK_R 21 21 BKOFF# 22 22 INVTPWM 23 23 +3VS_LVDS 24 24 +LCDVDD_L 25 25 26 26 27 27 +LEDVDD 28 28 29 29 30 30 JLVDS1 LVDS@ R73 2.2K_0402_5% 10/04 Change C401 on INVTPWM 10/01 Remove R74,R76 R75 2.2K_0402_5% 9/13 Add Net Name +3VS_DMIC 100P_0402_50V8J +3VS 9/13 Update LVDS Pin definition, Add R74,R76 Connect DMIC_CLK, DMIC_DATA to JLVDS1 pin and Michael 2010/11/18 31 32 33 34 35 36 C401 INVTPWM 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title LVDS / Camera / DMIC Size B Date: Document Number Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet of 37 HDMI@ R107 HDMI@ R112 HDMI_CLKN HDMI_CLKP +5VS 0_0402_5% 0_0402_5% HDMI_CLK-_CONN HDMI_CLK+_CONN Change RP13 to R107 , R112 Tock 2010/12/30 +5VS D HDMI_TX0N HDMI_TX0P HDMI@ R141 HDMI@ R142 0_0402_5% 0_0402_5% HDMI_TX0-_CONN HDMI_TX0+_CONN Change RP14 to R141 , R142 Tock 2010/12/30 HDMI_TX1N HDMI_TX1P HDMI@ R143 HDMI@ R187 0_0402_5% 0_0402_5% HDMI_TX1-_CONN HDMI_TX1+_CONN Change RP15 to R143 , R187 Tock 2010/12/30 +5VS 3 HDMIDAT_R @ D2 BAT54S-7-F_SOT23-3 HDMICLK_R 1 @ D3 BAT54S-7-F_SOT23-3 HDMI_HPD @ D4 BAT54S-7-F_SOT23-3 EMI/ESD D +3VS HDMI@ R188 HDMI@ R192 HDMI_TX2N HDMI_TX2P 0_0402_5% 0_0402_5% HDMI_TX2-_CONN HDMI_TX2+_CONN Change RP16 to R188 , R192 Tock 2010/12/30 G Swap HDMI Net of RP13~RP16 for layout Tock 2010/12/24 @ L8 HDMI_CLK+_CONN 4 3 HDMI_CLK-_CONN HDMI_CLK-_CONN R86 HDMI_TX0+_CONN WCM-2012-900T_4P R87 HDMI_TX0N 4 HDMI_TX0+_CONN HDMI_TX0-_CONN R88 HDMI_TX1+_CONN R89 HDMI_TX1-_CONN R90 HDMI_TX2+_CONN WCM-2012-900T_4P R91 HDMI_TX2-_CONN C HDMI_TX1P HDMI_TX1N 4 2 HDMI_TX1+_CONN 3 HDMI_TX1-_CONN R93 4 3 499_0402_1% 499_0402_1% @ R95 100K_0402_5% HDMI_TX2+_CONN HDMI_TX2-_CONN NEAR CONNECT D C Q7 SSM3K7002FU_SC70-3 G S 8/19 Change Q9A Q9B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6) HDMI@ 10/29 Add C409~C412(0.1U) on +5VS_HDMI 10/29 Add C415~C416(0.1U) on +5VS_HDMI_F HDMI_TX2N HDMIDAT_R Q9B DMN66D0LDW-7_SOT363-6 HDMI@ 499_0402_1% @ L11 HDMI_TX2P HDMI_DATA 499_0402_1% +5VS WCM-2012-900T_4P 499_0402_1% @ L10 Q9A DMN66D0LDW-7_SOT363-6 HDMI@ 499_0402_1% 499_0402_1% HDMICLK_R D 499_0402_1% S HDMI_TX0-_CONN @ L9 HDMI_TX0P HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ G R85 HDMI_CLKN HDMI_CLK HDMI_CLK+_CONN D S HDMI_CLKP 0.1U_0402_16V4Z 0.1U_0402_16V4Z HDMI@ C410 0.1U_0402_16V4Z HDMI@ C411 0.1U_0402_16V4Z HDMI@ C412 +5VS_HDMI C409 0.1U_0402_16V4Z 0.1U_0402_16V4Z HDMI@ C416 +5VS_HDMI_F C415 WCM-2012-900T_4P 8/26 Change Q7 to SB000009610 Standard Part HDMI@ +5VS W=60mil 9/20 Add F2 on HDMI @ R96 0_0805_5% HDMI@ D5 RB491D_SC59-3 10/27 Change D5 P/N from SC1B491D000 to SCS00003H00 HDMI@ 10/27 Change F2 P/N from SP04301P120 to SP040001B00 1 +3VS HDMI_DET HDMIDAT_R HDMICLK_R HDMI_HPD HDMI_CLK+_CONN HDMI_TX0-_CONN @ R102 100K_0402_5% HDMI_TX0+_CONN HDMI_TX1-_CONN @ R101 200K_0402_5% R103 100K_0402_5% HDMI@ HDMI_CLK-_CONN R100 150K_0402_5% HDMI@ B JHDMI1 HDMI_HPD +5VS_HDMI_F 10/28 Change JHDMI1 footprint from ACON_HMR2E-AK120D_19P-T to ACON_HMR2E-AK120D_19P-S E F2 HDMI@ 1.1A_6V_SMD1812P110TF 0_0402_5% @ C HDMI@ Q8 MMBT3904_NL_SOT23-3 C172 0.1U_0402_16V4Z HDMI@ B HDMI@ R98 2.2K_0402_5% 9/20 Change Q8,R100 from @ to HDMI@ R99 2 HDMI@ R97 2.2K_0402_5% B +5VS_HDMI W=60mil 9/20 Change R99 from HDMI@ to @ 10/07 Update JHDMI1 footprint from ACON_HMR2E-AK120D_19P to ACON_HMR2E-AK120D_19P-T HDMI_TX1+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 22 23 ACON_HMR2E-AK120D CONN@ 11/16 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P) A 19 18 17 16 15 14 13 12 11 10 A 8/23 Update JHDMI1 Symbol (SUYIN_100042GR019S268ZR_19P-T) 9/7 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P) 2010/11/09 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HDMI Connector Size Document Number Custom Date: Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet 10 of 37 ON/OFF Button 8/26 Change D11 to SC600000B00 Standard Part G G updated SW1 symbol for SN100002K00 2010/12/06 Tock ON/OFFBTN# +3VALW SW1 EVQPLMA15_4P 9/20 Remove R245,R248,D12 R247 100K_0402_5% FOR EMI D11 ON/OFF# ON/OFFBTN# ON/OFF# 51_ON# 51_ON# BAV70W_SOT323-3 PWR_LED1# C299 @ 100P_0402_50V8J ON/OFFBTN# C301 @ 100P_0402_50V8J place close to PR4 C300 51_ON# 1000P_0402_50V7K Q14 SSM3K7002FU_SC70-3 10K_0402_5% 1 9/6 Change D13 from mount to @ S C478 100P_0402_50V8J Reserve C478 for 51_ON# Tock 2011/01/07 G R249 EC_ON EC_ON EC_ON D C473 100P_0402_50V8J 8/26 Change Q14 to SB000009610 Standard Part Reserve C473 for EC_ON Tock 2011/01/07 10/05 Remove D13 9/1 Remove LED2 LED3 circuit, Change 70@ to mount 9/24 Change U9 to SA00001TC00 9/20 Add LED2 LED3 Circuit 9/21 Remove LED2 LED3 Circuit LID Switch W=20mil +3VS change R251 from 51 ohm to 220 ohm 2011/03/07 Tock (BLUE) C302 0.1U_0402_16V4Z R251 100_0402_1%~N VDD AH180WG-7_SC59-3 GND change R251 from 220 ohm to 100 ohm 2011/03/16 Tock +3VALW LID_SW# U9 LED1 HT-191NB5-DT BLUE 0603 C303 1 PWR_LED1# 10P_0402_50V8J @ 2 OUTPUT LED2 HT-191NB5-DT BLUE 0603 PWR_LED1# 10mil Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/11/09 Deciphered Date 2012/11/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size B Date: ON/OFF / PWR SW/ LID SW Document Number P1VE6 Schematics Thursday, March 17, 2011 Sheet 23 of 37 Rev 1.0 KSO15 KSO14 KSO13 KSO12 C398 C419 C448 C449 1 1 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J Change CP4 to C461 , C458 , C460 , C459 Change CP5 to C465 , C462 , C464 , C463 Change CP6 to C469 , C466 , C468 , C467 Tock 2010/12/30 KSO7 KSO6 KSO5 KSO4 C461 C458 C460 C459 1 1 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSI5 KSO9 KSI4 KSO8 C453 C450 C452 C451 1 1 C457 C454 C456 C455 2 2 1 1 2 2 KSI[0 7] 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSO3 KSI3 KSO2 KSO1 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSI[0 7] C465 C462 C464 C463 KSO0 KSI2 KSI1 KSI0 C469 C466 C468 C467 1 1 2 2 1 1 2 2 To TP/B Conn JKB1 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 KSI0 KSI1 KSI2 KSO0 KSO1 KSO2 KSI3 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSI4 KSO9 KSI5 KSI6 KSO10 KSO11 KSI7 KSO12 KSO13 KSO14 KSO15 Swap KB signal for layout Tock 2010/12/24 D KSI7 KSO11 KSO10 KSI6 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 8/22 Update JP3 Symbol from database (ACES_85201-0605N_6P) 8/22 Reserve R339 (0 ohm 0402) Add Net name +5VS_TP G2 G1 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 8/24 Update JTP1 Symbol from database (ACES_85201-0405N_4P) & Update pin definition W=20mil TP_DATA TP_CLK +5VS 0_0402_5% TP_DATA TP_CLK +5VS_TP R339 Change CP1 to C398 , C419 , C448 , C449 Change CP2 to C453 , C450 , C452 , C451 Change CP3 to C457 , C454 , C456 , C455 Tock 2010/12/30 JTP1 D G1 G2 ACES_85201-0405N CONN@ D14 @ PJDLC05C_SOT23-3 ACES_85202-24051 CONN@ 8/22 Update JKB1 Symbol from database (ACES_85202-24051_24P) 8/23 Update KB pin definition KSO[0 15] KSO[0 15] INT_KBD Conn Combo Jack CMBS@ QA36 MMBT3906H_SOT23-3 RA14 CMBS@ +LDO_OUT_3.3V 0_0402_5% COM_MIC_R change RA59 from 750 to 220 ohm by vender review for bo bo noise Tock 2011/03/16 RA35 2.2K_0402_5% NCMBS@ 2 RA13 D S G 2 CMBS@ change RA57 from 47K to 15K ohm by vender review for bo bo noise Tock 2011/03/16 CA26 1U_0603_10V6K CMBS@ JIO1 INT_MIC0 MIC1_L MIC1_R +MIC1_VREFO MIC_PLUG# COM_MIC HP_LEFT HP_RIGHT RA14 change RA12 BOM structure to @ by vender review for pop issue Tock 2010/12/08 Add net INT_MIC0 on JIO1 pin Tock 2010/11/26 1K_0402_5% NCMBS@ USB_ON# COM_MIC_PLUG# RA9 0_0402_5% RA41 20K_0402_5% 0_0402_5% QA4 BSS138_NL_SOT23-3 QA1B 2N7002KDW H_SOT363-6 CA49 @ 0.1U_0402_16V4Z USB_ON# USB20_P0 USB20_N0 USB20_P1 USB20_N1 USB_OC0# USB20_P0 USB20_N0 USB20_P1 USB20_N1 RA55 10K_0402_5% 2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 G1 G2 B Add IO connector Michael 2010/11/18 CONN@ ACES_85202-24051 COM_MIC S Add QA4,RA55,CA29,RA36 for Internal Mic can't record issue Tock 2011/02/21 CA29 1U_0603_10V6K A remove CA4 change QA1 , QA2 from SB501380020 to SB00000EO10 Tock 2011/02/24 Compal Electronics, Inc Compal Secret Data Security Classification change CA49 BOM structure to @ change RA41 from 47K to 4.7K by vender review for pop issue Tock 2010/12/08 G 2 A USB_OC0# QA1A 2N7002KDW H_SOT363-6 D RA36 HP_SENSE +5VS HP_PLUG# COM_MIC_PLUG# change RA9 from 20K to ohm Tock 2011/03/03 HP_PLUG# MIC_PLUG# COM_MIC HP_LEFT HP_RIGHT +5VALW 11/17 Add Combo solution circuit for P0VE6 "POPO" noise change RA52,DA10,CA26 BOM structure to @ by vender review for pop issue Tock 2010/12/08 INT_MIC0 MIC1_L MIC1_R HP_SENSE 2 RA57 15K_0402_1% QA3 CMBS@ BSS138_NL_SOT23-3 RA58 270K_0402_5% CMBS@ 11/17 Move HP JACK and MIC JACK Circuit to IO Board COM_MIC 1 1 RA52 100K_0402_5% CMBS@ COM_MIC CA28 10U_0805_10V6K CMBS@ RB491D_SC59-3 CMBS@ 2K_0402_5% HP_SENSE B CMBS@ CMBS@ RA50 10K_0402_5% DA10 CMBS@ RA59 220_0402_5% change GPIO_1 to GPIO_0 Tock 2011/01/03 GPIO_0 CMBS@ RA30 100K_0402_5% Add RA58 for net GPIO_1 by vender review for pop issue Tock 2010/12/08 1 CA25 10U_0805_10V6K @ C C 2010/11/09 Issued Date Deciphered Date 2012/11/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title KB Conn/TP/IO Conn Size B Date: Document Number Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet 24 of 37 A B C D E 1 11/17 Move Left Side USB CONN Circuit to IO board 2 +5VALW USB_ON# GND VIN VIN EN W=80mils U11 EPAD C338 0.1U_0402_16V4Z Right Side USB CONN +USB_VCCC1 W=80mils VOUT VOUT VOUT FLG Change C340 to SF000001500 2010/12/14 Tock USB_OC1# AP2301MPG-13_MSOP8 +USB_VCCC1 9/28 Swap L28 W=80mils C339 @ 1000P_0402_50V7K C340 220U_6.3V_M SA00003XM00 + 2 C341 R257 0_0402_5% @ 470P_0402_50V7K L28 8/25 Change C340 from poly-cap to E-cap (SF000001500) USB20_N2 JUSB1 SGA00002N80 USB20_N2_1 USB20_P2_1 VCC DD+ GND GND GND GND GND USB20_P2 3 USB20_N2_1 USB20_P2_1 WCM-2012-900T_4P R258 @ 0_0402_5% SUYIN_020173GB004M25MZL CONN@ change JUSB1 to SP060004B00 2010/12/14 Tock 4 delete D17 for DFB issue 2011/02/25 Tock 2010/11/09 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title USB PORTS Size B Date: Document Number Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet E 25 of 37 8/23 Pull up 10k (R345) to +3VALW on USB_ON# place close to PU4 and PU7 R272 2.2K_0402_5% EC_SMB_DA1 2.2K_0402_5% EC_SMB_CK1 C353 R275 10P_0402_50V8J 22_0402_5% 1 8/23 Change R271 R279 from mount to @ Reserve for EMI please close to U12 R276 +3VALW R277 @ 2.2K_0402_5% EC_SMB_CK2 @ 2.2K_0402_5% EC_SMB_DA2 KSI[0 7] KSO[0 15] KSI[0 7] KSO[0 15] 9/5 Change R276 R277 from mount to @ R279 @ EC_SCI# 10K_0402_5% 8/31 EC_SCI# Pull up to +3VALW 8/23 Delete R280 Reserve C436, C437 for SMB Michael 2010/11/18 EC_SMB_CK2 8/25 Delete KSO16 KSO17 C436 100P_0402_50V8J C437 100P_0402_50V8J EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK1 Battery EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 APU_ALERT#_EC APU @ C407 100P_0402_50V8J EC_XCLK1 OSC OSC 1 8/24 Delete Net FAN_SPEED1 C355 INVT_PWM FAN_SPEED1 BT_ON# EC_TX_P80_DATA EC_RX_P80_CLK ON/OFF# PWR_SUSP_LED# 15P_0402_50V8J X1 32.768KHZ_12.5PF_Q13MC14610002 Board ID R282 @ C357 0.1U_0402_16V4Z ECAGND KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 67 9/23 Reserve R395 on ACIN PS2 EC_XCLK1 EC_XCLK0 0_0402_5% 122 123 21 23 26 27 63 64 65 66 75 76 DAC_BRIG/DA0/GPO3C EN_DFAN1/DA1/GPO3D IREF/DA2/GPO3E DA3/GPO3F 68 70 71 72 EC_MUTE#/PSCLK1/GPIO4A USB_EN#/PSDAT1/GPIO4B CAP_INT#/PSCLK2/GPIO4C Interface PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F SDICS#/GPXIOA00 WOL_EN/SDICLK/GPXIOA01 ME_EN/SDIMOSI/GPXIOA02 LID_SW#/GPXIOD00 10/08 Change D18 to SCS00000Z00 C399 ACOFF 83 84 85 86 87 88 97 98 99 109 ACOFF GPIO EC_SMB_CK1/SCL0/GPIO44 EC_SMB_DA1/SDA0/GPIO45 EC_SMB_CK2/SCL1/GPIO46 EC_SMB_DA2/SDA1/GPIO47 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO GPIO0C SUS_PWR_DN_ACK/GPIO0D INVT_PWM/PWM2/GPIO11 FAN_SPEED1/FANFB0/GPIO14 FANFB1/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A BATT_TEMP GPI SPIDI/MISO SPIDO/MOSI SPICLK/GPIO58 SPICS# GPIO40 H_PECI/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 PWR_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 PM_SLP_S4#/GPXIOD01 ENBKL/GPXIOD02 EAPD/GPXIOD03 EC_THERM#/GPXIOD04 SUSP#/GPXIOD05 PBTN_OUT#/GPXIOD06 EC_PME#/GPXIOD07 XCLK1 XCLK0 V18R SA00003QQ10 @ C424 100P_0402_50V8J Reserve C424, C425, for SLP_S3#, SLP_S5# Michael 2010/11/18 Reserve C428 for ON/OFF# Michael 2010/11/18 ADP_I 0_0402_5% @ RB751V-40_SOD323-2 D19 ICH_POK_EC LID_SW# 2 R273 PWR_LED1# TP_CLK TP_DATA Follow PAWGC EN_FAN1 IREF CHGVADJ EC_MUTE# USB_ON# ACIN C470 220P_0402_50V7K 0_0402_5% ICH_POK @ R274 +3VS C 10K_0402_5% Reserve C470 for LID_SW# Tock 2011/01/07 9/25 Change VLDT_EN to VLDT_EN# EN_WOL# VLDT_EN# LID_SW# EN_WOL# VLDT_EN# LID_SW# 119 120 126 128 EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL# 73 74 89 90 91 92 93 95 121 127 EDP_BIST R390 eDP@ 0_0402_5% 110 112 114 115 116 117 118 VGATE APU_ENBKL EAPD EC_PROCHOT# SUSP# PBTN_OUT# WWAN_WAKEUP# 124 V18R R278 DMIC_DATA VR_ON EC_RSMRST# EC_LID_OUT# EC_ON EC_PME# ICH_POK_EC BKOFF# WL_OFF# WXMIT_OFF# LID_SW# DMIC_DATA +3VALW place close to PU2 Project ID Ra C400 2 EC_RSMRST# 100P_0402_50V8J EC_LID_OUT# EC_ON VGATE @ BKOFF# WL_OFF# WXMIT_OFF# 100K_0402_5% FSTCHG BATT_AMB_LED# PWR_LED# SYSON VR_ON +3VALW R285 100K_0402_5% FSTCHG BATT_BLUE_LED# BATT_AMB_LED# PWR_LED# SYSON VR_ON EC_ACIN 100 101 102 103 104 105 106 107 108 Add EDP_BIST and Reserve C390 , R285 Tock 2010/12/30 EDP_BIST EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL# FSTCHG BATT_BLUE_LED# C477 100P_0402_50V8J R398 @ 0_0402_5% AD_PID0 Reserve C477 for FSTCHG Tock 2011/01/07 Rb R399 @ 8.2K_0402_5% C393 @ 0.1U_0402_16V4Z B C423 100P_0402_50V8J Reserve C423 for VGATE Michael 2010/11/18 VGATE APU_ENBKL EAPD EC_PROCHOT# SUSP# PBTN_OUT# WWAN_WAKEUP# R281 100K_0402_5% C356 PME Follow PAWGC +3VALW C447 100P_0402_50V8J R322 10K_0402_5% Reserve C447 for APU_ENBK Tock 2011/01/07 R324 C471 100P_0402_50V8J Reserve C471,C472 Tock 2011/01/07 @ 0_0402_5% PCI_PME# C472 100P_0402_50V8J +3VALW A Q29 SSM3K7002FU_SC70-3 @ for LAN_WAKE# , BKOFF# Compal Secret Data 2010/11/09 EC_PME# 0_0402_5% BKOFF# C430 100P_0402_50V8J Security Classification @ R323 LAN_WAKE# LAN_WAKE# Reserve C430 for EC_PROCHOT# Michael 2010/11/18 R395 L30 ECAGND FBMA-L11-160808-800LMT_0603 Issued Date @ 8/23 Delete DAC_BRIG 8/25 Delete CHG_ON# 8/31 Add EN_FAN1 on U12.70 PWR_LED1# TP_CLK TP_DATA RB751V-40_SOD323-2 100P_0402_50V8J C352 BATT_TEMP EC_MUTE# USB_ON# C428 100P_0402_50V8J EC_ACIN 4.7U_0603_6.3V6K C425 100P_0402_50V8J D18 100P_0402_50V8J ECAGND EN_FAN1 IREF CHGVADJ 200K_0402_5% 2 10/27 Change C356 from 10V_0805 to 6.3V_0603 20mil ON/OFF# ADP_I AD_BID0 AD_PID0 EC_PROCHOT# SLP_S5# ACOFF @ EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 EC_ON/GPXIOA05 EC_SWI#/GPXIOA06 ICH_PWROK/GPXIOA07 BKOFF#/GPXIOA08 GPO RF_OFF#/GPXIOA09 GPXIOA10 GPXIOA11 10/11 Change R282 R358 from mount to @ SLP_S3# C351 BEEP# +3VALW 100P_0402_50V8J BEEP# SPI Device I/F SPI Flash ROM D 8/26 Change D18 to SCS00002G00 Standard Part 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 4.7K_0402_5% 10/04 Add 100p(C399) on ACOFF BATT_TEMP/AD0/GPI38 BATT_OVP/AD1/GPI39 ADP_I/AD2/GPI3A AD3/GPI3B AD Input AD4/GPI42 AD5/GPI43 DA Output KB930QF-A1_LQFP128_14X14 R284 8.2K_0402_5% 14 15 16 17 18 19 25 28 29 30 31 32 34 36 8/31 Add 100k(R358) pull-down on SUSCLK 2 G 1 SUSCLK @ D AD_BID0 Rb CLK_PCI_EC/PCICLK PCIRST#/GPIO05 EC_RST#/ECRST# EC_SCI#/GPIO0E CLKRUN#/GPIO1D R358 @ 100K_0402_5% change R284 from ohm to 8.2K , 2011/01/28 Tock change R283 from ohm to 100K , 2011/02/11 Tock R264 S Analog Board ID definition, Please see page R283 100K_0402_5% Ra LPC & MISC 10/11 Change C354,C355, X1 from @ to mount 8/23 Change R282 from mount to @ X1 C354 C355 from @ to mount 8/26 Change R282 from @ to mount X1 C354 C355 from mount @ +3VALW INVT_PWM FAN_SPEED1 BT_ON# EC_TX_P80_DATA EC_RX_P80_CLK ON/OFF# PWR_SUSP_LED# NC 15P_0402_50V8J EC_XCLK0 77 78 79 80 SLP_S3# SLP_S5# EC_SMI# APU_ALERT#_EC SLP_S5# EC_SMI# APU_ALERT#_EC NC C354 A PWM0/GPIO0F BEEP#/PWM1/GPIO10 FANPWM0/GPIO12 ACOFF/FANPWM1/GPIO13 SM Bus 10/05 Add 100p(C407) on APU_ALERT#_EC SLP_S3# B TP_DATA 9/23 Update EC pin definition follow P5WE6 Delete EC_FAN_PWM Tock 2011/01/28 PWM Output EC_SMB_DA2 @ 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ# LPC_FRAME#/LFRAME# LPC_AD3/LAD3 LPC_AD2/LAD2 LPC_AD1/LAD1 LPC_AD0/LAD0 GND GND GND GND GND @ 12 13 37 20 38 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 11/02 Change C353 to 10p R275 to 22 ohm +3VS 2 LPC_CLK0_EC PLT_RST# EC_SMI# 1K_0402_5% 4.7K_0402_5% R266 C @ 1 10 LPC_CLK0_EC PLT_RST# EC_RST# EC_SCI# EC_SCI# R271 2 KSO2 1 47K_0402_5% R263 +5VS C444 100P_0402_50V8J 1 TP_CLK 10K_0402_5% KSO1 2 R270 47K_0402_5% R345 10/1 ENE Recommand R269 USB_ON# 10K_0402_5% C443 @ 100P_0402_50V8J +3VALW C348 0.1U_0402_16V4Z @ TP_DATA C403 @ 100P_0402_50V8J R259 R268 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 0.1U_0402_16V4Z Reserve C420 for PLT_RST# Michael 2010/11/18 TP_CLK @ AGND C350 C420 100P_0402_50V8J EC_RST# C347 1000P_0402_50V7K 47K_0402_5% U12 R267 2 C346 1000P_0402_50V7K PLT_RST# C345 0.1U_0402_16V4Z LPC_CLK0_EC C344 0.1U_0402_16V4Z C343 0.1U_0402_16V4Z @R265 @ R265 33_0402_5% C342 0.1U_0402_16V4Z D ADP_I EC_MUTE# +3VALW_EC @C349 @ C349 22P_0402_50V8J L29 W=20mils FBMA-L11-160808-800LMT_0603 +EC_VCCA W=40mils AVCC R262 +3VALW 0_0603_5% 69 Reserve C475,C476 for SUSP# Tock 2011/01/07 +3VALW +3VALW 8/21 Change R262 from ohm 0805 to ohm 0603 22 33 96 111 125 C476 100P_0402_50V8J Reserve C403, C443, C444 for ADP_I, TP_CLK, DATA Michael 2010/11/18 11 24 35 94 113 C475 100P_0402_50V8J +3VS 8/31 Change EC_MUTE# Pull-up to +3VS(@) VCC VCC VCC VCC VCC VCC SUSP# Title Compal Electronics, Inc EC ENE-KB930 Size Document Number Custom Rev 1.0 P1VE6 Schematics Date: Thursday, March 17, 2011 Sheet 26 of 37 +3VALW R201 8/31 Remove EC ROM , Add SPI ROM EC_SPICLK_R 2SPI_HOLD# 3.3K_0402_5% R202 9/2 Change EC_SPICLK to EC_SPICLK_R 2MB SPI ROM Share ROM SPI_WP# 3.3K_0402_5% R200 33_0402_5% @ W=20mil +3VALW C212 CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0) SPI_HOLD# 0_0402_5% R206 EC_SPICLK_R EC_SPICLK EC_SPI_SI EC_SO_SPI_SI SA00003FO00 EC_SPICLK EC_SO_SPI_SI EMI 33_0402_5% R205 W25Q16BVSSIG_SO8 Layout Note: R204 close to U7 C211 22P_0402_50V8J @ 0.1U_0402_16V4Z U7 EC_SPICS#/FSEL#_R EC_SPI_SO SPI_WP# 33_0402_5% R204 Layout Note: R203 R205 R206 close to U12 Delete U17,C382,C386,R355,D20,C383,C384,C385 for Fan control IC circuit 2010/12/15 Tock Add U17,C382,C386,R355,D20,C383,C384,C385 for Fan control IC circuit 2011/01/19 Tock +5VS FAN Conn EC_SPICS#/FSEL# EC_SI_SPI_SO EC_SPICS#/FSEL# EC_SI_SPI_SO R203 0_0402_5% 2 D20 DAN217_SC59 @ +5VS C382 2.2U_0603_10V6K @ 2 C383 U17 H2 H_3P2 H3 H_3P2 9/15 Update the Screw Hole R355 @ GND GND GND GND 4.7U_0603_6.3V6K @ 10/07 Change H13 from LANGND to GND @ EN VIN VOUT VSET APL5607KI-TRG_SO8 10/07 Change H13 from GND to LANGND @ +VCC_FAN1 EN_FAN1_R 330_0402_5% 1 9/20 Add H20 (H_3P4X3P2N) EN_FAN1 H4 H_3P0N C385 +3VS C386 0.01U_0402_16V7K 40mil 1000P_0402_50V7K +VCC_FAN1 H1 H_3P2 3P2 x (APU) 4.7U_0603_6.3V6K @ C384 R290 10K_0402_5% +5VS R289 @ @ H9 H_2P3 2P3 x 1 @ H6 H_2P5 H7 H_2P5 1 1 @ @ H15 H_0P6X2P3 GND GND ACES_50273-0030N-001 CONN@ FM3 @ FM4 @ @ FIDUCIAL_C40M80 8/25 Update JFAN1 Symbol from database (ACES_85205-04001_4P) & Update pin definition 8/25 Add R290 10k pull-up +3VS FM2 @ H11 H_2P5 H10 H_2P5 2P5 x @ 8/24 Update JFAN1 Symbol from database (ACES_85205-03001_3P) & Update pin definition 8/24 Delete R290 FM1 H12 H_0P6X2P3 Update the Screw Hole 2010/12/22 Tock @ @ JFAN1 +VCC_FAN1 Update the Screw Hole 2010/12/16 Tock H8 H_2P3 +VCC_FAN1 0_0603_5% FAN_SPEED1 C360 @ 10U_0805_10V6K 2 40mil 3P0N x 8/31 Reserve U17,C382~C386, R355~R357, D20 (Fan Drive Circuit) change JFAN1 footprint from ACES_85205-04001_4P to ACES_50273-0030N-001_3P , 2011/01/28 Tock , delete EC_FAN_PWM and R356,R357 , 2011/01/28 Tock , 1 0P6X2P3 x @ @ H13 H_3P0X4P0N H14 H_3P0X4P0N 1 3P0X4P0N x @ @ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/11/09 Deciphered Date 2012/11/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Screw / EC ROM /FAN Size B Date: Document Number Rev 1.0 P1VE6 Schematics Thursday, March 17, 2011 Sheet 27 of 37 C +3VALW TO +3VS S C370 0.1U_0603_25V7K G Q20 S C371 0.1U_0603_25V7K 9/27 Change Q21.2 from SUSP# to SUSP SUSP# G Q21 100K_0402_5% 10/12 Change R402 from mount to @ 1 +1.1VS_ON# G Q22 @ S C404 @ SUSP R400 100K_0402_5% 0_0402_5% 0_0402_5% SUSP SUSP SYSON# 10/04 Add 100p(C403) on SUSP VLDT_EN# 10/06 Remove C403 VLDT_EN# R403 0_0402_5% 100P_0402_50V8J G Q30 SUSP# 10/04 Add 100p(C404) on VLDT_EN# +1.1VS_GATE_R C408 100P_0402_50V8J 10/06 Change C404 on +1.1VS_ON# R404 10K_0402_5% D SYSON SYSON S SSM3K7002FU_SC70-3 @ G Q31 SSM3K7002FU_SC70-3 D S 2 D +1.1VS_ON# G Q24 R402 @ R303 100K_0402_5% +1.1VS_ON# D R302 100K_0402_5% 9/28 Remove C372 R300 470_0603_5% @ R304 47K_0402_5% 1 9/28 Change U19 to Q15(SB934130020) SSM3K7002FU_SC70-3 S +1.1VS_GATE R351 +5VALW 9/28 Change R296.1 from +VSB to +5VALW C376 1U_0603_10V6K SB548000210 +VSB +5VALW 2011/02/11 Change Q15 to SB000006R10 +5VALW 10/29 Change R298 from ohm to 100k C373 0.1U_0402_16V4Z 10/31 Change C373 from 0603_25V to 0402_16V 9/28 Change Q21.2 from SUSP to SUSP# 10/12 Change R400 R403 from @ to mount Remove C375 10U Michael 2010/11/18 +1.5VS_GATE_R S SSM3K7002FU_SC70-3 +1.1VS SUSP +1.5VS_GATE R298 D 9/27 Change Q15 to U19(SB00000GV00) U16 +1.1VALW AP4800BGM-HF_SO-8 Remove C374 10U Michael 2010/11/18 G Q18 SSM3K7002FU_SC70-3 S 9/27 Change R296.1 from +5VALW to +VSB +1.1ALW to +1.1VS D R296 200K_0402_5% change R295 from 200K to 120K Tock 2011/01/03 0_0402_5% SSM3K7002FU_SC70-3 D S G 2+3VS_GATE_R SB000006R10 1 SUSP +3VS_GATE R350 D +5VALW SUSP G Q17 @ SSM3K7002FU_SC70-3 R291 470_0603_5% +5VS_GATE_R C363 1U_0603_10V6K 2 G 20K_0402_5% SSM3K7002FU_SC70-3 Q19 S 2 D 1 R293 470_0603_5% @ D R295 120K_0402_5% R297 +5VS_GATE Remove C362 10U Michael 2010/11/18 SUSP S C369 1U_0603_10V6K SB548000210 SUSP G Q16 @ SSM3K7002FU_SC70-3 1 R294 82K_0402_5% +VSB D SB548000210 +1.5VS Q15 AO3413L_SOT23-3 +VSB R292 470_0603_5% @ +1.5V 1 C366 1U_0603_10V6K Remove C361 10U Michael 2010/11/18 Remove C368 10U Michael 2010/11/18 +3VS 10/27 Change R291 Q18 from @ to mount +1.5V to +1.5VS U15 +3VALW Remove C367 10U AP4800BGM-HF_SO-8 Michael 2010/11/18 Remove C365 10U Michael 2010/11/18 +5VS U14 +5VALW Remove C364 10U AP4800BGM-HF_SO-8 Michael 2010/11/18 E +5VALW TO +5VS D B A C378 0.1U_0603_25V7K 10/27 Add C408(100P) on SUSP# close to PR70 9/27 Change R302 from @ to mount, remove R301 8/19 Change Q16~Q22 Q24~Q28 toSB000009610(SSM3K7002FU_SC70-3) SSM3K7002FU_SC70-3 10/12 Change R294 to 100k 9/27 Change R304.1 from +5VALW to +VSB 10/12 Change R295, R296 to 200k Change Q25 package to SOT363-6 Remove Q26 Michael 2010/11/18 +1.8VS 10/12 Change R304 to 47k Change Q27 package to SOT363-6 Remove Q28 Michael 2010/11/18 +1.05VS 10/12 Change R294 to 82k 10/12 Change R297 to 20k +1.5V 8/19 Change Q29 Q30 to Q23A Q23B (SB00000DH00 S TR DMN66D0LDW-7 2N SOT363-6) 10/31 Change C361 C362 from mount to @ 8/21 Change U14~U16 to SB548000310 (SI4800BDY-T1-E3_SO8) 8/23 Remove R305 R299 Add R350 R351 for Sequence 8/24 Change Q23A Q23B to Q30 Q31(@) (SB000009610 SSM3K7002FU_SC70-3) +0.75VS @ Q27B R309 470_0603_5% @ 8/25 Change C361,C362,C364,C365,C367,C368,C374,C375 to SE000004880 Standard Part 8/26 Change U14, U15, U16 to SB00000GV00 Standard Part 9/3 Delete C377(DIS@) @ Q27A SUSP 2N7002DW-T/R7_SOT363-6 R307 470_0603_5% @ @ Q25B SUSP 2N7002DW-T/R7_SOT363-6 @ Q25A 6 R308 470_0603_5% @ SYSON# 2N7002DW-T/R7_SOT363-6 R306 470_0603_5% @ 2 1 8/25 Change C363,C366,C369,C376 to SE080105K80 Standard Part SUSP 2N7002DW-T/R7_SOT363-6 9/23 Reserve R400~403, Q36 for VLDT_EN 9/25 Remove R401 Q36 on VLDT_EN 9/25 Add 10k(R404) PD on SUSP# Compal Electronics, Inc Compal Secret Data Security Classification 2010/11/09 Issued Date 2012/11/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title DC Interface Size Document Number Custom Date: Rev 1.0 P1VE6 Schematics Sheet Thursday, March 17, 2011 E 28 of 37 A B C D VMB 1 PL2 HCB2012KF-121T50_0805 PJP2 VMB 10 BATT+ EC_SMCA PR6 1K_0402_1% PC8 0.01U_0402_25V7K PC7 1000P_0402_50V7K PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 72 degree C EC_SMDA B/I TS VL @ PR10 100K_0402_1% MAINPW ON PU1 PR8 22.1K_0402_1% VCC TMSNS1 GND RHYST1 OT1 TMSNS2 PR11 15K_0402_1% OT2 RHYST2 +3VALW PR14 1K_0402_1% PR13 100_0402_1% PR12 100_0402_1% G718TM1U_SOT23-8 2 @ PR15 47K_0402_1% BATT_TEMP 2 PR9 6.49K_0402_1% PR7 10K_0402_1% VL PC9 0.1U_0402_10V7K 1 @ SUYIN_200275MR008G15QZR 2 GND GND PH2 @ EC_SMB_CK1 PH1 100K_0402_1%_NCP15W F104F03RC 100K_0402_1%_NCP15W F104F03RC EC_SMB_DA1 PQ2 TP0610K-T1-E3_SOT23-3 B+ +VSBP PR18 100K_0402_1% PR17 @ 2 VL PC10 0.22U_0603_25V7K PR16 100K_0402_1% PC11 @ 0.1U_0603_25V7K D 22K_0402_1% S PR19 POK PQ3 SSM3K7002FU_SC70-3 G PC12 1U_0402_16V7K 0_0402_5% 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/12 Deciphered Date 2012/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title BATTERY CONN / OTP Size Date: Document Number Rev 1.0 Thursday, March 17, 2011 Sheet D 29 of 37 A B C D VIN PD1 RLS4148_LL34-2 +CHGRTC 2 VS 2 PC6 0.22U_0603_25V7K PC5 0.1U_0603_25V7K PR4 51_ON# @ PJ2 @ PC248 1U_0402_16V7K +1.1VALW P 2 1 JUMP_43X118 PC241 1U_0402_16V7K @ PC254 1U_0402_16V7K +1.1VALW +3VALW PC242 1U_0402_16V7K 1 +3VLP PJ1 PR5 0_0603_5% @ 2 JUMP_43X118 22K_0402_1% 3 PR2 68_1206_5% PR3 100K_0402_1% SP02000GC00 +3VALW P N1 RLS4148_LL34-2 2 PC4 100P_0402_50V8J PC3 1000P_0402_50V7K PC2 100P_0402_50V8J 1 PR1 68_1206_5% PD2 BATT+ PC1 1000P_0402_50V7K GND GND PJP1 PQ1 TP0610K-T1-E3_SOT23-3 DC_IN_S1 CONN@ ACES 88266-04001 VIN PL1 HCB2012KF-121T50_0805 1 1 +5VALW @ PC252 1U_0402_16V7K 2 PC243 1U_0402_16V7K JUMP_43X39 +1.05VS PC244 1U_0402_16V7K @ PC253 1U_0402_16V7K +VSB +0.75VSP @ PJ6 2 1 JUMP_43X79 PC245 1U_0402_16V7K 1 2 @ PC255 1U_0402_16V7K @ PJ5 +VSBP JUMP_43X118 JUMP_43X118 +1.05VSP @ PC256 1U_0402_16V7K +0.75VS PJ3 PC246 1U_0402_16V7K @ 1 @ PJ4 +5VALW P @ PJ7 1 JUMP_43X118 @ PC257 1U_0402_16V7K +1.8VS 2 +1.8VSP PC247 1U_0402_16V7K @ PJ9 2 JUMP_43X118 PC258 1U_0402_16V7K +1.5V +1.5VP PC249 1U_0402_16V7K Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/12 Deciphered Date 2012/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title DCIN/VIN DECTOR Size Date: Document Number Rev 1.0 Thursday, March 17, 2011 Sheet D 30 of 37 1 EN CSON 22 PR34 PHASE 18 LX_CHG 6251VREF VREF UGATE 17 DH_CHG 1U_0402_16V7K 6251VREF 6251ACLIM CHLIM BOOT 16 PR42 BST_CHG 0_0603_5% 10 ACLIM VDDP 15 6251VDDP 11 VADJ LGATE 14 DL_CHG 12 GND PGND 13 1 20K_0402_1% 1 4.7K_0402_1% PR46 0.01U_0402_25V7K PC31 ACOFF PR44 100K_0402_1% PQ12 DTC115EUA_SC70-3 ACOFF PR43 PL4 10UH_VMPI0703AR-100M-Z01_3.5A_20% CHG PC27 BST_CHGA 0.1U_0603_25V7K PD5 SD103AW S SOD323-2 6251VDD PR45 PC32 4.7U_0603_6.3V6M PR38 BATT+ @ PR41 4.7_1206_5% 0.05_1206_1% ICM 2_0402_5% 19 @ PC28 680P_0603_50V7K IREF CSIP C PC26 PR39 62K_0402_1% VCOMP 20_0402_5% PC25 0.1U_0603_25V7K PR36 1 47K_0402_1% ADP_I S PR37 @ PC21 2200P_0402_50V7K PQ10 AON7408L_DFN8-5 PR40 47K_0402_1% 20 PR27 100K_0402_1% 2BATT_ON CSOP PQ11 AON7408L_DFN8-5 CSIN 6800P_0402_25V7K 10K_0402_1% 0.01U_0402_25V7K ICOMP CSON PR35 CSOP D G PACIN PC24 CELLS 21 PQ9B DMN66D0LDW -7_SOT363-6 PR32 20_0402_5% PC22 0.047U_0402_16V7K PR33 20_0402_5% PC23 PQ7 DTC115EUA_SC70-3 1 PQ9A DMN66D0LDW -7_SOT363-6 PR28 14.3K_0402_1% 0.1U_0603_25V7K ACPRN S ACSETIN @ PC204 10U_0805_25V6K 23 VIN PC205 10U_0805_25V6K ACSET ACPRN 47K_0402_1% 2 C G PC19 1000P_0402_25V8J 1 6251_EN D 24 2 100K_0402_1% DCIN D PR21 PR25 10K_0402_1% PC20 DCIN VDD PR31 PR30 150K_0402_1% PQ8 DTC115EUA_SC70-3 6251VDD PU2 PQ6 DTA144EUA_SC70-3 PR29 10K_0402_1% FSTCHG 1 PR26 10_1206_5% PR24 191K_0402_1% PD4 RB751V-40_SOD323-2 2 BATT_ON PC18 2.2U_0603_6.3V6K ACSETIN PR23 200K_0402_1% PC17 0.1U_0603_25V7K PR22 200K_0402_1% 1 VIN PC13 5600P_0402_25V7K PC16 4.7U_0805_25V6-K CSIP D CSIN PC15 4.7U_0805_25V6-K 2 PQ5 AON7403L_DFN8-5 CHG_B+ @ PL3 HCB2012KF-121T50_0805 @ PC30 10U_0805_25V6K @ PC14 4.7U_0805_25V6-K 1 @ PC29 10U_0805_25V6K 1 SX34_SMA2 B+ PR20 0.05_1206_1% PL18 1.2UH_1231AS-H-1R2N=P3_2.9A_30% PC251 10U_0805_25V6K VIN P3 AON7403L_DFN8-5 PQ4 P2 PD3 PC250 10U_0805_25V6K CP = 85%*Iada ; CP = 1.789A ADP_I = 19.9*Iadapter*Rsense PC237 10U_0805_25V6K Iada=0~2.105A(40W/19V=2.105A) @ 4.7_0603_5% ISL6251AHAZ-TR5283_QSOP24 B B CHGVADJ PR47 CV mode PR48 31.6K_0402_1% CC=0.25~3.52A Vth,rise(typical) = ((191K/14.3K)+1)*1.26 6251VDD = 18.089V BATT Type 15.4K_0402_1% Charging Voltage (0x15) Vth,fall(typical) = ((191K/14.3K)+1)*1.26 -3.4uA*191K IREF=0.7224*Icharge 12.60V IREF=0.43V~3.24V 12600mV = 17.44V Normal 3S LI-ON Cells PR49 47K_0402_1% PR50 10K_0402_1% ACIN PACIN Ki Vchlim=Iref*(PR39/(PR39+PR44)) =Iref*(100K/(80.6K+100K)) =Iref*0.617 Ichanrge=(165mV/PR38)*(Vchlim/3.3V) =(165m/50m)*(1/3.3V)*Iref*0.617 =0.617*Iref Iref=1.62*Ichanrge =>Ki=1.62 PR51 10K_0402_1% PQ13 DTC115EUA_SC70-3 PR52 14.3K_0402_1% A ACPRN Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451 A 2010/08/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2012/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CHARGER Size Date: Document Number Rev 1.0 Thursday, March 17, 2011 Sheet 31 of 37 2VREF D D PC33 1U_0402_6.3V6K UGATE1 21 LX_3V 11 PHASE2 PHASE1 20 LX_5V LG_3V 12 LGATE2 LGATE1 19 LG_5V PC37 0.1U_0603_25V7K PC240 4.7U_0805_25V6-K PL7 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 1 + PC46 @ 680P_0603_50V7K PC44 220U_6.3V_M PQ17 FDMC7692S_MLP8-5 VL PC48 4.7U_0603_6.3V6K B++ PQ18B DMN66D0LDW -7_SOT363-6 B PR64 2 +5VALWP NC RT8205EGQW _W QFN24_4X4 2VREF PC49 0.1U_0603_25V7K PR65 VL PC42 0.1U_0603_25V7K PR62 @ 4.7_1206_5% 18 17 16 13 C UGATE2 PC40 4.7U_0805_25V6-K 1 10 POK PQ15 AON7408L_DFN8-5 S DMN66D0LDW -7_SOT363-6 FB1 UG_3V PR60 BST_5V 0_0603_5% UG_5V EN D G S ENTRIP1 22 G REF BOOT1 VREG5 BOOT2 VIN ENTRIP2 ENTRIP1 D BST_3V 1 PC47 1U_0402_6.3V6K B PQ18A TONSEL 23 GND 24 PGOOD PR63 499K_0402_1% B++ PQ16 FDMC7692S_MLP8-5 ENTRIP2 VO1 VREG3 100K_0402_5% PC45 @ 680P_0603_50V7K ENTRIP2 VO2 + PR58 143K_0402_1% 4.7_1206_5% B++ PR61 @ PC43 220U_6.3V_M P PAD 15 PR59 0_0603_5% +3VALWP PL6 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 25 2 PC41 0.1U_0603_25V7K PU3 SKIPSEL PR57 130K_0402_1% 14 PC38 PQ14 AON7408L_DFN8-5 PR56 19.1K_0402_1% 4.7U_0603_6.3V6K PC36 2200P_0402_50V7K PC239 4.7U_0805_25V6-K PC35 4.7U_0805_25V6-K C +3VLP PR55 20K_0402_1% ENTRIP1 B+ PL5 HCB2012KF-121T50_0805 PR54 30K_0402_1% FB2 B++ +5VALW Vo= (2*30K/19.1K)+2=5.141V PR53 13.7K_0402_1% PC39 2200P_0402_50V7K +3VALW Vo= (2*13.7K/20K)+2=3.37V TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ (+3VALWP) 1 100K_0402_1% MAINPW ON PR66 100K_0402_1% PC50 0.1U_0402_10V7K A @ PR67 42.2K_0402_1% VS PQ19 DTC115EUA_SC70-3 +3.3VALWP Imax=4.214A ; Ipeak=6.02A ; Iocp=1.2*Ipeak=7.224A f=375KHz, L=4.7UH,Rentrip2=130K ohm Rdson=14.5~17.9m ohm (IRFH3707) 1/2Delta I = 1/2 *(19-3.3)*(3.3/19)/(375KHz*4.7UH)=0.773A Vtrip2=(10*10^-6*150Kohm/9)-24mV=0.143V Ilimit=0.143/(17.9m*1.2)~0.143/(14.5m)=6.642A~9.839A Iocp=7.415A~10.613A (7.415A>7.224A -> OK) +5VALWP Imax=4.9A ; Ipeak=7A ; Iocp=1.2*Ipeak=8.4A f=300KHz, L=4.7UH,Rentrip1=143K ohm Rdson=14.5~17.9m ohm (IRFH3707) 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A Vtrip1=(10*10^-6*162Kohm/9)-24mV=0.156V Ilimit=0.156/(17.9m*1.2)~0.156/(15m)=7.263~10.759A Iocp=8.569~12.065A (8.569>8.4 -> OK) Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/12 Issued Date Deciphered Date 2012/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title 3VALWP/5VALWP Size Document Number Rev 1.0 Date: Thursday, March 17, 2011 Sheet 32 of 37 B C FB PC55 @ 200K_0402_1% PC56 PR72 0.22U_0402_10V6K FB_1.8VS PR71 10K_0402_1% VFB=0.6V Vo=VFB*(1+PR69/PR71)=0.6*(1+20.5K/10K)=1.83V Ipeak=2A, Imax=1.4A 2 499K_0402_1% PR69 20.5K_0402_1% PC54 22U_0805_6.3VAM NC FB=0.6Volt NC TP 11 EN_1.8VS PR68 PR70 SUSP# +1.8VSP PC51 22U_0805_6.3VAM EN SVIN PC53 22U_0805_6.3VAM LX LX_1.8VS PVIN PC52 68P_0402_50V8J JUMP_43X39 LX PVIN 10 1 680P_0603_50V7K 4.7_0603_5% +5VALW D PL8 1UH_FDV0630-1R0M-P3_10.3A_20% PU4 SY8033BDBC_DFN10_3X3 @ PJ10 PG A 2 14 BST VFB=0.75V FB PGOOD 13 DH_1.5V LX_1.5V LX 12 ILIM 11 VDD 10 DL PR73 15K_0402_1% PC61 0.1U_0603_25V7K PC62 2200P_0402_50V7K 1 +1.5VP @ PR79 4.7_1206_5% +5VALW DL_1.5V + PC65 330U_2.5V_M PC67 4.7U_0603_6.3V6K PQ21 FDMC7692S_MLP8-5 @ PC66 680P_0603_50V7K G5603RU1U_TQFN14_3P5X3P5 PGND AGND PC58 4.7U_0603_6.3V6K 0.1U_0603_25V7K VCC DH PL10 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% PC64 OUT BST_1.5V-1 100_0603_5% 0_0603_5% PR78 TON 1 +5VALW 15 EN_SKIP PU5 TP PC63 @ 1U_0402_16V7K 2 PR76 30K_0402_5% B+ BST_1.5V 0_0402_5% PR77 2 PR75 1 SYSON PC60 4.7U_0805_25V6-K PR74 255K_0402_1% PQ20 AON7408L_DFN8-5 PC59 4.7U_0805_25V6-K PL9 HCB2012KF-121T50_0805 PR80 5.36K_0402_1% PR81 5.1K_0402_1% VFB=0.75V V=0.75*(1+5.36K/5.1K)=1.538V Cout ESR=25m ohm Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm (IRFH3707) Ipeak=6.5A, Imax=4.55A, Iocp > 7.8A G5603 Temperature Compensated RT8209B ℃ -1180ppm/ ℃ 1600ppm/ TPS51117 ℃ 4500ppm/ OCP setting RT8209B TPS51117 RT8209M 6.821A 7.235A 8.000A 8.178A RT8209M ℃ 4800ppm/ Vtrip_min (SPEC) 30mV 50mV 30mV 50mV Vtrip_max (SPEC) 200mV 200mV 200mV 200mV Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/12 Deciphered Date 2012/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A G5603 B C Title 1.8VSP/1.5VP Size Document Number Custom Date: Rev 1.0 Thursday, March 17, 2011 D Sheet 33 of 37 A B C D PR82 255K_0402_1% 2 PR88 13K_0402_1% DL_1.1VALW DL PGND AGND PC75 4.7U_0603_6.3V6K +5VALW G5603RU1U_TQFN14_3P5X3P5 PC76 4.7U_0603_6.3V6K PC71 2200P_0402_50V7K PC70 0.1U_0603_25V7K 1 PC74 330U_2.5V_M 10 G5603 RT8209B TPS51117 RT8209M 5.799A 6.183A 6.845A 6.976A +1.1VALW P OCP setting @ PR86 4.7_1206_5% 11 BST ILIM VDD 0.1U_0603_25V7K @ PC77 680P_0603_50V7K PGOOD LX_1.1VALW VFB=0.75V DH_1.1VALW 12 FB 13 LX PQ23 FDMC7692S_MLP8-5 VCC 14 15 DH OUT TON +5VALW PL12 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% PC73 PR87 100_0603_1% TP PU6 EN_SKIP PC72 1U_0402_16V7K @ PR84 30K_0402_5% @ Cout ESR=25m ohm Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm (IRFH3707) Ipeak=4.02A, Imax=2.814A, Iocp > 4.824A PQ22 AON7408L_DFN8-5 BST_1.1V ALW POK PR85 0_0603_5% PR83 0_0402_5% B+ VFB=0.75V V=0.75*(1+4.99K/10K)=1.124V 1 PC69 4.7U_0805_25V6-K PC68 4.7U_0805_25V6-K PL11 HCB2012KF-121T50_0805 1.1VALW _B+ 1 + PR89 4.99K_0402_1% 2 PR90 10K_0402_1% PL13 HCB2012KF-121T50_0805 DL PGND PGOOD AGND PC85 4.7U_0603_6.3V6K G5603RU1U_TQFN14_3P5X3P5 PC86 4.7U_0603_6.3V6K PC80 0.1U_0603_25V7K PC79 4.7U_0805_25V6-K 1 PC81 2200P_0402_50V7K +1.05VSP PC84 330U_2.5V_M DL_1.05VALW +5VALW @ PR97 4.7_1206_5% PR96 15K_0402_1% @ PC87 680P_0603_50V7K 10 VDD LX_1.05VALW ILIM 11 14 15 BST 12 0.1U_0603_25V7K FB LX VCC VFB=0.75V 13 PQ25 FDMC7692S_MLP8-5 OUT DH_1.05VALW DH PL14 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% PC83 PR95 100_0603_1% +5VALW TON B+ PQ24 AON7408L_DFN8-5 BST_1.05V ALW TP PU7 EN_SKIP PC82 1U_0402_16V7K 2 PR94 30K_0402_5% @ 1 SUSP# PR93 0_0603_5% PR92 200K_0402_1% 2 PR91 255K_0402_1% PC78 4.7U_0805_25V6-K 1.05VALW _B+ + VFB=0.75V V=0.75*(1+3.57K/8.25K)=1.074V Cout ESR=25m ohm Rdson(max)=17.9m ohm Rdson(typ)=14.5 mohm.(IRFH3707) Ipeak=5.5A, Imax=3.85A, Iocp > 6.6A PR98 3.57K_0402_1% OCP setting RT8209B TPS51117 RT8209M 6.524A 7.003A 7.768A 7.881A PR99 8.25K_0402_1% G5603 4 G5603 Temperature Compensated RT8209B ℃ -1180ppm/ ℃ 1600ppm/ TPS51117 ℃ 4500ppm/ RT8209M ℃ 4800ppm/ 30mV 50mV 30mV 50mV Vtrip_max (SPEC) 200mV 200mV 200mV 200mV A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Vtrip_min (SPEC) 2010/08/12 Deciphered Date 2012/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C Title 1.1VALWP/1.0VSP Size Document Number Custom Date: Rev 1.0 Thursday, March 17, 2011 D Sheet 34 of 37 D D PJ11 JUMP_43X118 @ C PU8 2 GND NC VREF VCNTL C +3VALW PC89 1U_0402_6.3V6K PR100 1K_0402_1% NC VOUT PC88 4.7U_0603_6.3V6K VIN 1 +1.5V NC TP PQ26 SSM3K7002FU_SC70-3 +0.75VSP PR102 1K_0402_1% PC90 1U_0402_16V7K 1 S PC91 10U_0603_6.3V6M PC92 1U_0402_16V7K D G PR101 300K_0402_5% SUSP APL5336KAI-TRL_SOP8P8 For shortage changed B B A A Compal Secret Data Security Classification 2010/08/12 Issued Date 2012/08/12 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc 0.75VSP Size Date: Document Number Rev 1.0 Thursday, March 17, 2011 Sheet 35 of 37 B C D E PL15 HCB2012KF-121T50_0805 CPU_B+ PC93 33P_0402_50V8J PR124 0_0402_5% PR126 26.1K_0402_1% SVC PGND0 LGATE0 RBIAS PVCC OCSET LGATE1 VDIFF0 PGND1 35 BOOT0 34 UGATE0 33 PHASE0 32 APU_VDD0_RUN_FB_H PC99 68U_25V_M_R0.44 PC98 2200P_0402_50V7K PC97 0.1U_0603_25V7K PC96 4.7U_0805_25V6-K PC103 220U_D2_2VY_R15M 1 PC110 2200P_0402_50V7K PC109 0.1U_0603_25V7K PC108 4.7U_0805_25V6-K PC107 4.7U_0805_25V6-K PC106 4.7U_0805_25V6-K +5VALW 30 29 28 PQ30 FDMC7692S_MLP8-5 PR123 7.5K_0402_1% @PC112 @PC112 680P_0603_50V7K PC113 0.1U_0603_16V7K PC114 1U_0603_16V6K LGATE0 27 PR127 1.69K_0402_1% 26 TP 25 49 ISN1 24 ISP1 23 VW1 22 COMP1 21 FB1 20 VDIFF1 19 VSEN1 18 RTN1 17 14 ISN0 ISP0 VSEN1 PR129 0_0402_5% PR130 0_0402_5% BOOT1 +APU_CORE @ PR122 4.7_1206_5% LGATE0 31 +APU_CORE ISP0 ISN0 PR128 10_0402_1% 13 VSEN1 RTN0 UGATE1 VW0 VSEN0 COMP0 ISP0 12 PHASE1 16 11 FB0 PC111 0.22U_0603_10V7K PHASE0 36 PL17 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% UGATE0 SVD ISL6265CHRTZ-T_TQFN48_6X6 PR118 2.2_0603_1% BOOT0 38 39 40 41 PWROK 15 10 37 UGATE_NB PHASE_NB LGATE_NB PGND_NB 42 43 44 45 46 BOOT0 BOOT_NB BOOT_NB PGOOD ENABLE + ISN0 PR125 90.9K_0402_1% 1 VR_ON @ PC104 680P_0603_50V7K ISP0 100P_0402_50V8J 1 2 PR121 0_0402_5%2 +APU_CORE_NB PHASE0 PQ29 AON7408L_DFN8-5 @ PC124 @PC124 OFS/VFIXEN OCSET_NB ISN0 PC123 100P_0402_50V8J @ ISL6265_PWROK APU_SVD APU_SVC @ PR119 100K_0402_5% PR120 100K_0402_5% RTN_NB VSEN_NB H_PWRGD_L FSET_NB FCH_PWRGD FB_NB VCC VGATE COMP_NB 47 48 VIN PU9 @PR107 4.7_1206_5% CPU_B+ UGATE0 @ PR117 105K_0402_1% PQ28 FDMC7692S_MLP8-5 PHASE_NB 2 @ PR114 105K_0402_1% APU_VDDNB_RUN_FB_L UGATE_NB @ PR116 10K_0402_1% PR115 105K_0402_1% PC102 0.22U_0603_10V7K APU_VDDNB_RUN_FB_H 2 1 PR113 0_0402_5% LGATE_NB + PL16 2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% 2 PR139 10_0402_5% 100P_0402_50V8J 1 PR111 0_0402_5% PR112 PHASE_NB 17.8K_0402_1% LGATE_NB 1 +3VS PR108 10_0402_5% +APU_CORE_NB @ PC122 2 PC105 0.1U_0603_25V7K PHASE_NB PR105 2.2_0603_1% BOOT_NB B+ 2 PR109 2_0603_5% +3VS +5VS @ 1 1 UGATE_NB PR106 22K_0402_1% PR110 0_0402_5% @ PC121 100P_0402_50V8J 2 PC101 0.1U_0603_16V7K CPU_B+ PC100 1000P_0402_50V7K 1 +5VALW PC95 4.7U_0805_25V6-K PR104 2_0603_5% 2 PC94 1000P_0402_50V7K 1 PR103 44.2K_0402_1% PQ27 AON7408L_DFN8-5 A VSEN0 @ PC119 @PC119 100P_0402_50V8J APU_VDD0_RUN_FB_L PR131 10_0402_1% 1 @ PC120 @PC120 100P_0402_50V8J RTN0 0_0402_5% PR132 DIFF_0 VW0 PR134 PC115 255_0402_1% 4700P_0402_25V7K 2 COMP0 PC116 100P_0402_50V8J PR135 1K_0402_5% PR136 PC118 2 +3VS 7.87K_0402_1% PR133 6.49K_0402_1% PR140 PC117 1000P_0402_50V7K PR137 6.81K_0402_1% 54.9K_0402_1% 1200P_0402_50V7K Compal Secret Data Security Classification PR138 36.5K_0402_1% 2010/08/12 Issued Date 2012/08/12 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC @ A B C D Title Compal Electronics, Inc CPU_CORE Size Date: Document Number Rev 1.0 Thursday, March 17, 2011 Sheet E 36 of 37 Version change list (P.I.R List) Item Rev PG# Modify DCIN/VIN DECTOR power sequence 30 Modify charger power sequence 31 Modify 3VALWP/5VALWP power sequence 32 Modify charger power sequence Modify charger power sequence Modify 3VALWP/5VALWP power sequence B Reason for change C Page of for PWR Fixed Issue D 1 Modify List Date Add PC248 for +3VALWP PC252 for +5VALWP PC253 for +VSBP PC254 for +1.1VALWP PC255 for +1.05VSP PC256 for +0.75VSP PC257 for +1.8VSP Phase 20101228 EVT delete PC234 20101228 EVT delete PC34 20101228 EVT 31 Chang PD5 from SCS00000Z00 (RB751V-40_SOD323-2 to SCS00005I00 (SD103AWS SOD323-2) 20110104 EVT 31 Chang PD3 from SCS00001I80 ( B340A SMA ) to SCS00000W00 (SX34_SMA2) Chang PQ4&PQ5 fromSB00000KI00(SI7121DN-T1-GE3 1P POWERPAK1212-8) to SB00000KZ00(AON7403L_DFN8-5) 20110106 EVT 32 Chang PL6 &PL7 from SH00000F900(4.7UH_FDVE0630-H-4R7M= P3_5.5A_20%) to SH00000MB00(4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%) 20110110 EVT EVT Modify 1.8VSP/1.5VP power sequence 33 Chang PL10 from SH00000F800(2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%) 20110110 to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%) Modify 1.1VALWP/1.05VSP power sequence 34 Chang PL12 &PL14 from SH00000F800(2.2UH_FDVE0630-H-2R2M= P3_8.3A_20%) to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%) 20110110 EVT 20110110 EVT 20110110 EVT Modify CPU_CORE power sequence 36 Chang PL16 &PL17 from SH00000F800(2.2UH_FDVE0630-H-2R2M= P3_8.3A_20%) to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%) 10 Modify CPU_CORE power sequence 36 Chang PR112 from SD034237280 (23.7k_0402_1%) to SD034178280 (17.8k_0402_1%) Chang PR123 from SD000002680 (6.98k_0402_1%) to SD034750180 (7.5k_0402_1%) Chang PR127 from SD034187180 (1.87k_0402_1%) to SD00000JB80 (1.69k_0402_1%) 11 Modify 1.8VSP/1.5VP power sequence 33 add PC258 to +1.5V output capacitor (co-lay higt from 4.5 to 2.5) for thermal issue 20110208 DVT 12 Modify 1.1VALWP/1.05VSP power sequence 34 add PC259 to +1.1VALWP output capacitor (co-lay higt from 4.5 to 2.5) for thermal issue 20110208 DVT 13 Modify 1.8VSP/1.5VP power sequence 33 delete co-lay PC258 for +1.5V output capacitor 20110225 PVT 14 Modify 1.1VALWP/1.05VSP power sequence 34 delete co-lay PC259 for +1.1VALW output capacitor 20110225 PVT 15 Modify charger power sequence 31 delete co-lay PJ32 modify PQ4 PQ5 footprint from AON7403L_DFN8-5 to SIS412DN-T1-GE3_POWERPAK8-5 20110226 PVT 16 Modify charger power sequence 31 change charger IC from G5209 to ISL6251 change output choke from 8.2u to 10u 20110226 PVT 17 Modify DCIN/VIN DECTOR power sequence 30 Add PC258 for +1.5V jump by RF test 2010302 PVT D C B 18 19 20 21 22 A A 23 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/12 Deciphered Date 2012/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PIR (PWR) Size Document Number Custom Date: Thursday, March 17, 2011 Rev 1.0 Sheet 37 of 37 ... APU_CLK# 0_0402_5% 0_0402_5% APU_CLK_R APU_CLK#_R - WLAN CLK_PCIE_WLAN CLK_PCIE_WLAN# R134 R135 0_0402_5% 0_0402_5% CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R WWAN CLK_PCIE_WWAN CLK_PCIE_WWAN#... Part D10 L29 L28 PCI_CLK3 PCI_CLK4 V2 D CLK_PCIE_LAN_R CLK_PCIE_LAN#_R PCI_CLK1 S CLK_PCIE_LAN CLK_PCIE_LAN# LAN 0_0402_5% 0_0402_5% PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN... 11 LAN_WAKE# WAKE# VDD33 +3V_LAN LX +1.7_LX VDDCT VDDCT_REG +1.7_VDDCT +1.7_VDDCT_REG 30 +1.1_DVDDL 0_0402_5% 18 19 SMCLK SMDATA TESTMODE GND LAN_X1 LAN_X2 CL11 27P_0402_50V8J XTLO XTLI 21 LAN_RBIAS