MEMORY CONTROL SYSTEM Considering a typical and enough structure for a system shown in Figure 3. Assuming the ratio of CPU speed and memory speed is M, % is the probability that a ne[r]
(1)Chu Dire Toin Tap chl KHOA HQC & CONG NGHE 93(05): -
T H E M E T H O D O F C O N T R O L L I N G C O U N T E R R E S T R U C T U R E I N P A R A L L E L P R O C E S S I N G S Y S T E M
Chu Due Toan Electric Power University A B S T R A C T
In parallel processing systems, the efficient use of system resources Is an important requirement Improving performance and increasing speed are related to many issues, both hardware and software [1, 2] The analysis of processing system operation shows which affects the performance and speed of processing system: During referencing to memory, the processor uses only a command cycle in order to require to read or write data into memory, then wait for the completion of memory cycle before next memory access Therefore, CPU speed is not taken full advantage, memory access conflicts occur when two or more components simultaneously access to a memory location This paper proposes the method of controlling counter restructure to meet the requirements of information processing speed The model used is a restructure controller with F P G A technology The solution of speed increase is done by maintaining the maximized chain of memory access requests
Keywords: restructure controller with FPGA technology; speed; parallel processing system; performance; Ihe mechanism of parallel memory controller
associated with a data latch T h e data from each m o d u l e is delivered through latch and multiplexer to a single data channel Figure s h o w s a time graph for many- word reading accesses using S- access configuration Suppose that the memory access time T^ and latch delay time T, time to access a single data word is T^ + x However, the total time to access the next string k word, starting at module /, is T^ + k.x \fi + k<M, and opposite case \s2T^+(i + k-M)x In both cases, ( M is the ratio of C P U speed and memory speed) T h e condition to access vectors efficiently is Mz < T^ if not data overflow will occur [3]
I N T R O D U C T I O N
Current processing systems have a big difference between the operation speed of processor and that of m e m o r y operations This rate is generally from to 15 times [4, 5] T o take full advantage of processor time, the m e m o r y is organized in parallel as an interleaving model with S-access memory architecture This is a solution for memory conflicts in accordance with parallel m e m o r y m o d e l s in parallel processing systems S-access model using lower interleaving address order is described in Figure S-access method allows all modules to be accessed simultaneously Each module is
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(3)Chu Diic Toan Tap chl KHOA HQC & CONG NGHE 93(05): 17-21 THE STRUCTURE OF PARALLEL
MEMORY CONTROL SYSTEM Considering a typical and enough structure for a system shown in Figure Assuming the ratio of CPU speed and memory speed is M, % is the probability that a next request accesses the next memory modules, is the probability that a next request accesses a determined memory module, but not the next memory module
To improve the performance of data flow, considering the characteristics of the system with the assistance of FPGA technology, we can create software architecture for information collecting and information processing Parallel memory control structure followed the combination method with M factor and restructure control block in FPGA
technology for memory module M = 16 is illustrated in Figure and Figure
Processing mode:
In this mode, specific control partition for address channel and system control channel is described in detail in Table I
Where: Addr Multiplexer is a pointer to memory module corresponding'requirements and SCAN Multiplexer allows right access as scanning cycle to ensure memory recovery time
* Information collection:
When switching to information collecting, specific control partition for address channel and system control channel in this mode is described In detail in Table
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Figure The time graph for the process After collection is complete, to read the data just follow 2- step algorithm:
Step Copy data from 16 memory modules in corresponding position on each other As a result, we have 16 data regions containing same content
Step Composite address channel as table by FPGA technology The result is that memory space is organized into 16 parallel standard memory modules and reading process conducts as normal
Suppose to retrieve data as the order of memory access request sequence with address 00, 02, 04, 06, 08, 10 12, 14, 16 then the system will ignore the modules U 1, # , # 5, # 7, # 9, # 11, # 13, # 15, although there are full of original data
In this case the length of request string k is only 8, equal to half of maximum value of k (= 16) CONCLUSION
This paper proposes degradation processing system When the task of processing is only
of reading information from memory in one direction, the system optimization is nearly absolute by the aid of FPGA technology with system arch itecture rearrangement technique Architecture rearrangement control system by FPGA always requires data read/ write line to achieve maximum value k = max = constant
REFERENCES
[I] Barry W (1996) "Computer architecture design and performance" University of North Carolina, Prentice Hall New York
[2] Chou Y., Pahs B., AND Abraham S (2004), "Microarchitecutre optimizations for exploiting memory-level parallelism" ACM pp 29-70 [3] Hamacher, C , Vranesic, Z., Zaky, S (2002), Computer Organization McGraw-Hill, Inc., New York,
(5)Tap chi KHOA HQC & CONG NGH$ 93(05): -
M O T PHU'ONG PHAP DIEU KHIEN TAI KIEN TRUC B O DEM
TRONG HE XU" LY SONG SONG
Chu Du-c To^n'
Dai hpc Di4n luc T O M T A T
Trong cdc h^ xii ly song song, vi^c su dyng hipu qua cdc t^i nguyen h^ ihong \k yeu c^u het siic quan trgng, Vi^c nSng cao hieu nSng, nSng cao toe d§ g6m nhi^u v^n d^, lifin quan cS den phan Cling \k phSn mem [1, 2] Phan tIch hoat d^ng cOa h$ xCr 1^ cho thdy nguySn nhSn lAm dnh hudaig d^n hieu nSng, toe dp cua h6 xii ly Id: qud trlnh tham chi^u dfin hi} nh6, bO xCr 1^^ chi sir dyng mpt chu ky lenh de yeu cSu dpc ho^c ghi dft lifiu vdo bp nhd, sau d6 phdi chir chu V.y bO nhd ket thiic trudc c6 the truy c§p tiSp bO nhd Do d6, khong tdn dyng tri^t 6k t6c dO cCia CPU; xung dpt truy cap bO nhd xdy c6 hai hay nhi^u thdnh ph^n dong thdi truy cap tdi mOt vi tri nhd Bdi bdo de xuat phucmg phdp di6u khi^n tdi kien triic bp d^m nhdm ddp ling ySu c^u toe dp xir ly thong tin Mo hinh dupc dCing Id bo di^u khiin tdi kiln triic bdng cong ngh^ FPGA, gidi phdp tdng toe dp dupc thuc hi$n bdng cdch tri chu6i yeu cdu truy cap bO nhd lu6n d^t cue d?i
TCi" kh6a: Dieu khien ldi hen true bdng cong nghe FPGA; toe dg; h$ xu ly song song; hiiu ndng; ca cdu dieu khien bg nhd song song
Ngdy nhdn bdi: 24/2/2012, ngdy phdn biin: 14/3/2012, ngdy duyel ddng-12/6/2012