Journal of Science: Advanced Materials and Devices (2018) 348e352 Contents lists available at ScienceDirect Journal of Science: Advanced Materials and Devices journal homepage: www.elsevier.com/locate/jsamd Original Article Low power organic field effect transistors with copper phthalocyanine as active layer Lekshmi Vijayan a, Anna Thomas b, K Shreekrishna Kumar a, *, K.B Jinesh b, ** a b Department of Electronics, School of Technology and Applied Sciences, Mahatma Gandhi University, Kottayam, 686041, Kerala, India Department of Physics, Indian Institute of Space-Science and Technology (IIST), Valiamala, Thiruvananthapuram, 695547, Kerala, India a r t i c l e i n f o a b s t r a c t Article history: Received 12 June 2018 Received in revised form August 2018 Accepted August 2018 Available online 17 August 2018 Bottom gate, top contact Organic Field Effect Transistors (OFETs) were fabricated using copper phthalocyanine (CuPc) as an active layer The electrical properties of OFETs fabricated with CuPc annealed at different annealing temperatures and different channel length to width (L/W) ratios were studied The transfer characteristics of the devices appear to improve with annealing temperature of CuPc and increasing L/W ratios of the devices Upon annealing, the field effect mobility increased from 0.03 ± 0.004 cm2/V to 1.3 ± 0.02 cm2/V Similarly, the interface state density reduced from 5.14 ± 0.39 Â 1011 cmÀ2eVÀ1 for the device fabricated using as deposited CuPc, to 2.41 ± 0.05 Â 1011 cmÀ2eVÀ1 for the device with CuPc annealed at 80 C The on/off current ratio increased from 102 for the as-deposited device, to 105 for the device with CuPc annealed at 80 C The dependence of the subthreshold swing on the L/W ratio was also investigated © 2018 The Authors Publishing services by Elsevier B.V on behalf of Vietnam National University, Hanoi This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/) Keywords: Organic field effect transistors CuPc Scanning tunneling microscope Interface trap density Carrier mobility Introduction The major challenge in the realization of low power organic field effect transistors (OFETs) is the reduction of the manufacturing cost, especially when scaling up to meet industrial demands Low leakage current, reduction in power consumption, high mobility, light-weight and low-cost are the advantages of organic thin film transistors (OTFTs) [1] An efficient way to reduce the overall size of the device is the use of thin inorganic dielectric and organic semiconducting layers [2] Even though a large spectrum of organic semiconductors has been proposed for the fabrication of OFETs, only a few can meet the requirements for electronic device applications in terms of processibility and stability in normal atmosphere [3] There has been a growing interest in developing new organic channel materials in order to fabricate the electronic devices [4] OFETs provide two principal advantages over field effect transistors (FETs) based on inorganic semiconductors Firstly, they can be fabricated at lower temperature and lower cost [5] * Corresponding author ** Corresponding author E-mail addresses: kshreekk@gmail.com (K.S Kumar), kbjinesh@iist.ac.in (K.B Jinesh) Peer review under responsibility of Vietnam National University, Hanoi Among various organic materials that have been extensively studied for FET applications, phthalocyanines are organic dyes that attained a lot of research interests These materials have potential applications for various electronic components such as thin film transistors (TFTs), light emitting diodes (LEDs) etc [6] In this work, TFTs fabricated with a typical p-type organic semiconducting material, copper phthalocyanine (CuPc), are used as the channel material for OFET fabrication CuPc based TFTs have shown better current saturation and high field effect mobility [6] Due to its good chemical stability and heat resistance [7], CuPc thin films can be fabricated using physical vapour deposition techniques, which is ideal from the perspective of scaling up with good uniformity for large area electronics In addition, CuPc has good stability in ambient conditions CuPc is a stable compound, normally found with a monoclinic crystal structure [8] The solubility of CuPc in common organic solvents is very less, but due to its thermal stability, uniform films can be fabricated using thermal evaporation technique, which allows industrial level scaling up Fig shows the molecular structure of CuPc The dielectric material plays a crucial role in device operation since it influences the electric field, current leakage through the gate insulator and the quality of the interface between the organic semiconductor and gate dielectric [5] Organic dielectric materials show high leakage current with decreasing the film thickness and https://doi.org/10.1016/j.jsamd.2018.08.002 2468-2179/© 2018 The Authors Publishing services by Elsevier B.V on behalf of Vietnam National University, Hanoi This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/) L Vijayan et al / Journal of Science: Advanced Materials and Devices (2018) 348e352 349 CuPc layer was 50 nm The OFETs were fabricated with different channel widths (4 mm and 1000 mm) and different channel lengths (175 mm and 135 mm) In order to examine the improvements in the electrical properties of the OFET, the fabricated devices were annealed at different temperatures in air The schematic representation of the fabricated device is shown in Fig The surface morphology of the film was investigated by Field Emission Scanning Electron Microscopy (FESEM, Bruker Nova NanoSEM-450) The work function of CuPc thin films was studied by Scanning Tunneling Microscope (STM, Quazar Tech.) The electrical characterization of the OFETs was done in air at room temperature and different annealing temperatures using a 4-point probe station connected to an Agilent B2900A semiconductor parameter analyzer Results and discussion 3.1 Morphology of the CuPc films Fig Molecular structure of a copper phthalocyanine molecule most of them not exhibit high dielectric constant The use of inorganic dielectrics can resolve this issue [9,10] There are several approaches to improve the performance of OFET devices Especially, the use of thinner high dielectric constant materials as the gate insulator is the effective way to reduce the operating voltage [11e13] In this work, we employed a 50 nm thick silicon dioxide (SiO2) as the gate insulator, which allows us to quantify the spacecharges that influence the device performance as will be discussed later in this paper Compared to the conventional OFETs that work at large operating voltages, large threshold voltages and having low mobility [14], our devices work at much lower operating voltages with marginal threshold voltage and reasonably good carrier field effect mobility In this paper, we report on the fabrication of low power CuPc based OFET devices and their performance at various fabrication conditions and experimental temperatures The electrical characteristics of the OFETs were done to estimate the device parameters such as mobility, threshold voltage, on/off current ratio, subthreshold swing and interface trap density The influence of the channel length e to e width ratio (L/W) and annealing temperatures on the device characteristics have been analyzed in this work Experimental The bottom gate, top contact p-type OFETs were fabricated on a silicon wafer with CuPc as the channel layer The bottom gate structures are usually used in OFETs because organic semiconductors are more prone to damage during conventional manufacturing processes [15] In this study, an n-type silicon wafer (resistivity ~ 1e10 Ucm) with 50 nm thick thermally grown SiO2 layer on top was used as the substrate for device fabrication Before the deposition, the substrates were cleaned in an ultrasonic bath followed by thorough washing with acetone, isopropyl alcohol and de-ionized water for 10 each Finally the substrate was dried and loaded in the thermal evaporator (Fillunger TCS0204 model) CuPc films were thermally evaporated at a rate of 0.1 nm/s without substrate heating, at a pressure of 10À6 Torr Successively, 100 nm silver was thermally evaporated through a shadow mask, to form the source and drain Out of several thicknesses of channel layer fabricated, the optimal thickness of the Fig (a) shows the secondary electron images of CuPc thin films deposited on silicon substrates at room temperature The surface of the film appears to consist of nano-sized spherical particles with an average size of 30 nm STM was employed to image the CuPc layer deposited on ITO surface and to estimate its work function The STM images of the CuPc shown in Fig 3(b,c) were measured at a tipsample bias of À1.5 V and 120 pA tunneling current The dark regions distributed throughout the image are CuPc molecules stacked on top of each other [16,17] The tunneling current (I) to tip/sample distance (z) spectrum was taken to determine the work function CuPc, shown in Fig (d) The current is related to the tip/sample distance by the following relation [18]: I ẳ I0 exp2kdị (1) Where d the tunneling distance and k is the decay constant given ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi pis by k ¼ 2mf=h2 Here, f is the measured total potential For a tip of work function ft and tunneling current measured at a voltage V, the work function fs of the sample will be [19] f ẳ fs eV ỵ ft ị=2 (2) The value of work function measured is 4.89 ± 0.58 eV 3.2 Electrical characterization Since the estimated work function of CuPc is 4.89 eV, silver was used as the source and drain contacts to minimize the threshold shift The conductivity of CuPc increases with increasing Fig Schematic representation of OFET with CuPc as the channel layer 350 L Vijayan et al / Journal of Science: Advanced Materials and Devices (2018) 348e352 Fig (a) Secondary electron micrograph of CuPc, (b) STM images of copper phthalocyanines on ITO surface with tunneling conditions of À1.5 V and 120 pA, (c) STM images of copper phthalocyanines on ITO surface with tunneling conditions of À1.5 V and 120 pA, (d) The I-z spectra measured on CuPc surface, from which the work function was estimated temperature and this is a typical behavior of semiconductors [8] First, we focus on the effects of annealing temperatures on the fabricated OFET devices Fig shows the transfer characteristics of the CuPc based OFET with and without annealing with a channel length of 135 mm and a channel width of mm (L/W ¼ 0.034) The device shows reasonably good transfer behavior with evident saturation and gate dependent drain-source current The transfer characteristics show that CuPc behaves as a p-type semiconductor Fig is the output characteristics of the same device, showing clear gate dependence The non-saturating behavior is due to the spacecharge limited current (SCLC) dominating over the saturation current The sample annealed at 80 C shows better saturation, which could be due to less defects in the film after annealing Though the work functions of silver and CuPc are matching, a shift of approximately V in the threshold voltage is seen in the output characteristics of the devices, which could be due to Ag/CuPc interfacial imperfections and series resistance due to thin Ag electrodes The work function of silver is 4.2 eV So according to MotteSchottky vacuum level alignment scheme [20,21] there would be a barrier exist for holes at CuPc/Ag interfaces The field effect mobility was calculated from the transconductance plot shown in Fig The field effect mobility is then extracted using the standard equation: m¼ L gm WCox Vds (3) where gm is the transconductance, the derivative of the linear part of transfer characteristics and Cox is the oxide capacitance per unit area The gate oxide capacitance (Cox) of SiO2 film was calculated using the formula Cox ¼ εA/d, where ε is the dielectric constant, A is the area of the capacitor and d is the thickness of the oxide layer Then the Cox per unit area was directly measured using Si/SiO2/Al capacitors, yielding an average value of 43 pF/mm2 The on-off ratio of the drain current for the sample without annealing was 102, which increased to 103 for samples with CuPc annealed at 50 C and 105 for annealing at 80 C For CuPc based OFETs, Chaur et al have reported field effect mobilities ranging from 10À3 to 1.0 cm2/V, the value depending upon the gate dielectric material, deposition technique and operating conditions [22] In our case, the highest Fig Transfer curves of CuPc based OFETs with L/W of 0.034, fabricated using CuPc layer (a) as deposited, (b) annealed at 50 C and (c) annealed at 80 C L Vijayan et al / Journal of Science: Advanced Materials and Devices (2018) 348e352 351 Fig Output characteristics of CuPc based OFETs with L/W of 0.034, fabricated using CuPc layer (a) as deposited, (b) annealed at 50 C, and (c) annealed at 80 C mobility of 1.30 ± 0.02 cm2/V was obtained from the OFET with channel length and width of 175 mm and 1000 mm respectively, for the device layer annealed at 80 C The field effect mobility increased with increasing annealing temperature and increasing L/ W ratios This value is relatively higher than that obtained in the CuPc based OFETs prepared in the previous works Yakuphanoglu et al [23] reported a CuPc based OFET was fabricated using SiO2 as gate dielectric They obtained a field effect mobility of 5.32 Â 10À3 cm2/V Hussein et al [8] reported that top contact CuPc based OFET with Al as the source/drain electrode onto the heavily n-doped Si substrate with an oxide layer of 60 nm The calculated mobility value in their devices was 1.22 Â 10À3 cm2/V Similarly a mobility of 1.5 Â 10À3 cm2/V was obtained for 40 nm thick thermally evaporated CuPc active layers on the surface treated SiO2 gates in the top-contact OFETs [24] Huanqin et al [25] have reported a large hole mobility of 0.05 cm2/V for the OFET in combination with a buffer layer and electrode modified layer together with CuPc However, the hole mobility we report in this work shows a significant improvement over all these reported mobilities This improvement may be a consequence of the smaller dielectric thickness or the larger L/W ratio of the present device One of the previous works has demonstrated that the drain current increases with decreasing the thickness of the dielectric material [26] This behavior is also similar to one observed for the multilayer dielectric based OFETs [11] Besides, we observed that the CuPc based OFET device shows significant low drive voltage in our case compared with the values presented by other workers [26] pffiffiffiffiffiffi The extrapolation of fitted straight line of Ids versus Vgs plot gives the threshold voltage From Fig the minimum value of the threshold voltage measured is À2 V for CuPc treated at 80 C with channel length and width of 135 mm and mm respectively Fig Threshold voltage calculation of CuPc based OFETs with a channel length of 135 mm and a channel width of mm The subthreshold swing (SS) of the device is given by [13] SS ¼ d logIds À1 dVgs (4) The estimated subthreshold swing of the same device is 0.69 ± 0.05 V/decade for 80 C annealing, when measured at Vds of À5 V From the subthreshold swing, the interface trap density was estimated using the equation [27]: SS ẳ kT qNit ln10ị Â q Cox (5) where Nit is the interface trap density of the device The calculated Nit values are 5.14 ± 0.39 Â 1011 cmÀ2eVÀ1 for the case of without annealing, 3.26 ± 0.04 Â 1011 cmÀ2eVÀ1 for 50 C treated sample and 2.41 ± 0.05 Â 1011 cmÀ2eVÀ1 for 80 C treated sample From the results, it is clear that OFETs operated in the high temperature regime shows better performance In addition, the transistors kept in ambient conditions were stable, when measured after duration of one week The L/W ratio of CuPc based OFET also affected the subthreshold swing and interface trap density Fig shows the mobilities of the OFETs under different L/W ratios with a constant drain source voltage of À5 V The device shows a linear reduction in mobility upon decreasing the L/W ratio From Fig 8, comparison of SS and Nit of CuPc based OFET with different L/W ratios are examined The subthreshold slope of the device became steeper with the L/W ratio while the interface trap density slightly decreased These results suggest that increasing the L/W ratio is an effective way to keep a minimum value of subthreshold swing Fig Dependence of the measured field effect mobilities of the CuPc based OFETs with and without annealing with different L/W ratios 352 L Vijayan et al / Journal of Science: Advanced Materials and Devices (2018) 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CuPc based OFETs with and without annealing with different L/W ratios Conclusion The electrical performances of vacuum deposited thin film based p-channel OFETs with CuPc as the channel layer. .. device layer annealed at 80 C The field effect mobility increased with increasing annealing temperature and increasing L/ W ratios This value is relatively higher than that obtained in the CuPc based... CuPc based OFET was fabricated using SiO2 as gate dielectric They obtained a field effect mobility of 5.32 Â 10À3 cm2/V Hussein et al [8] reported that top contact CuPc based OFET with Al as the