Introduction to VHDL Appendix B: Targeting Xilinx FPGAs – Inference and Instantiation Examples Outline • • • I/O Resources and Attributes Global Clock and Routing Resources Internal Logic Resources and Attributes Appendix B: Targeting Xilinx FPGAs - 26 - © 2007 Xilinx, Inc All Rights Reserved I/O Resources and Attributes • This section examines I/O-related resources and attributes Proper use enhances performance, overall chip count, interface, and functionality Inferred I/O Registers • Indicates it can be inferred directly from the source code 2X Data Rate Reg I/O Pull-ups and Pull-downs Constraint • Indicates it can be assigned or controlled within the Constraints Editor in the ISE™ software ISERDES/OSERDES I/O Location SelectIO™ Technology Standard • Indicates Xilinx library instantiation is required Slew Rate/Input Delay Appendix B: Targeting Xilinx FPGAs - 26 - Instance © 2007 Xilinx, Inc All Rights Reserved I/O Registers • I/O registers can enhance performance and extend resources I/O Registers Inferred entity DESIGN_TOP is port (IN1, IN2, IN3, CLK : in std_logic ; OUT1, OUT2, : out std_logic ); end entity DESIGN_TOP; architecture RTL of DESIGN_TOP is begin process (CLK) begin if rising_edge ( CLK) then OUT3 DATA_A , D1 => DATA_B, CE => CE, CO => CLK0_BUFG, C1 => CLK0_180_BUFG, PRE => SET, CLR => RESET, Q => Q ) ; C1 Appendix B: Targeting Xilinx FPGAs - 26 - © 2007 Xilinx, Inc All Rights Reserved CLR Q Double Data Rate Registers • DDRs can be inferred or instantiated for inputs Inferred entity INPUT_DDR is port ( D : in std_logic; CLK : in std_logic; Q_AND : out std_logic ); end INPUT_DDR; architecture INPUT_DDR_ARCH of INPUT_DDR is signal Q1, Q2 : std_logic; begin process ( CLK ) begin if rising_edge ( CLK ) then Q1 Data_in_Hstl_III ) ; Xilinx Floorplan Editor Instance Appendix B: Targeting Xilinx FPGAs - 26 - 10 © 2007 Xilinx, Inc All Rights Reserved Global Buffer Instantiation • When the clock is internally sourced, the BUFG component must be instantiated Global Clock Buffers Instance Regardless of the nature of internal logic, the output clock signal should drive the BUFG IBUF or IBUFG Appendix B: Targeting Xilinx FPGAs - 26 - 16 DCM User-Defined Logic BUFG © 2007 Xilinx, Inc All Rights Reserved BUFGCE and BUFGMUX • • The BUFGCE can be used as a global clock enable The BUFGMUX can be used for glitch switching between input clocks i0 BUFGMUX and BUFGCE Instance o i1 component BUFGMUX port ( i0, i1 : in std_logic ; o : out std_logic ; end component ; o i S BUFGMUX ce BUFGCE Appendix B: Targeting Xilinx FPGAs - 26 - 17 © 2007 Xilinx, Inc All Rights Reserved Instance component BUFGCE port ( i, ce : in std_logic ; o : out std_logic ; end component ; Architecture Wizard • All attributes related to the DCM, as well as component instantiations for IBUFG, DCM, BUFG, BUFCE, and BUFGMUX, can be handled via the Architecture Wizard in the ISE™ software This includes the PMCD and PLL Appendix B: Targeting Xilinx FPGAs - 26 - 18 © 2007 Xilinx, Inc All Rights Reserved Carry Logic • To infer use of carry logic, use standard VHDL arithmetic operators at the top level of the intended module – Avoid detailed structural models that use smaller primitives Carry Logic A_In Sum B_In Carry Inferred architecture RTL of MY_ADD64 is signal SUM_I : std_logic_vector (64 downto 0) ; begin SUM_I