Memory and Record Lab Memory and Record Lab www.xilinx.com 1-877-XLX-CLAS 10b-2 Memory and Record Lab (Part of the Calculator Project) Introduction In this lab, you will write a complete RTL description for the submodule MEM by using a twodimensional array and a VHDL record data type that forms its base The MEM module is a synchronous ROM, and you will need to fully describe the clocked process Use the example from the lecture or the reference guide at this time Process statements are covered later in the course Objectives After completing this lab, you will be able to: Use the record data type to create a user-defined synchronous ROM structure Create the first component for the Calculator module Combine various VHDL data types Verify the logic structure Procedure Examine the circuit below (Figure 10b-1) In this lab, you will write the RTL description for the submodule MEM Figure 10b-1 Schematic for a Simple Calculator Circuit Memory and Record Lab www.xilinx.com 1-877-XLX-CLAS 10b-3 NOTE: Toolwire is the default platform for running labs Use R:\ for all directory references This lab comprises two primary steps: You will create a VHDL package that contains a userdefined record data type and then use that record data type to create a two-dimensional memory array For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction Note: When using Toolwire to perform this lab, all software programs, files and projects will be located on the R:\ drive instead of C:\ Note: If you are unable to complete the lab at this time, you can download the lab files for this module from the Xilinx FTP site at ftp://ftp.xilinx.com/pub/documentation/education/lang11000-9-rev1-xlnx_lab_files.zip Creating a Package with a User-Defined Record Data Type Step For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction General Flow for this Lab: Step 1: Creating a Package with Record Data Type Step 2: Creating a Synchronous RAM Open the existing My_Class_Labs project within the ISE™ software, located in the R:\training\vhdl\labs directory Create a package with a user-defined record data type Select Start Programs Xilinx ISE 9.1i Project Navigator to launch the Project Navigator Memory and Record Lab www.xilinx.com 1-877-XLX-CLAS 10b-4 By default, the ISE software should start with the last open project as the current project If not, select File Open Project My_Class_Labs ! ! Important: Unless otherwise noted, you must label your project and HDL source files as instructed, or simulation may not work properly in the Toolwire environment Select Project New Source In the New Source dialog box, select VHDL Package and enter CALC1_PACKAGE in the File name field Click Next and the ISE™ software package template opens This file contains partial code for a variety of declarations that are common to user-defined packages However, you are only creating a single record data type at this point To reduce confusion, delete everything in the file except the library, package, and end package declaration Label the package CALC1_PAK Create a record, labeled MY_RECORD, with the following elements (in this order) A_IN : std_logic_vector ( downto ) ; B_IN : std_logic_vector ( downto ) ; OP_CODE : std_logic_vector ( downto ) ; C_IN : std_logic ; EXP_OUT : std_logic_vector ( downto ) ; Save the file Note that the package appears in the Sources for window (Figure 10b-2) Figure 10b-2 Sources for Window Memory and Record Lab www.xilinx.com 1-877-XLX-CLAS 10b-5 Creating a Synchronous ROM Step General Flow for this Lab: Step 1: Creating a Package with Record Data Type Step 2: Creating a Synchronous RAM Declare a synchronous two-dimensional memory arrary (ROM) by using the record data type contained within the newly created package Select Project New Source In the New Source dialog box, select VHDL Module, enter MEM in the File name field, and click Next to open the table-based entity wizard Enter the following ports: CLK : in std_logic ; ADDR : in std_logic_vector ( downto ) ; READ_EN : in std_logic ; DATA_FRAME : out MY_RECORD ; ! ! Note that within the wizard, you cannot actually specify the data type The tool always defaults to data type std_logic Therefore, you will need to complete the port definition within the HDL editor, after exiting the wizard This explicit step will be necessary anytime you want to use the wizard and specify any data type other than std_logic or std_logic_vector Declare the package CALC1_PAK with the use clause along with the other library and package declarations for the MEM module Create a two-dimensional ROM structure with CLK and EN that contain eight elements (depth) of the record type MY_RECORD An example of this syntax is shown in the “Signals and Data Types” module At this time, assign all values to logic or unknown X You will update the values in a subsequent lab exercise Use named association to specify the ROM contents Note: Although you can use ( others => ‘0’) to define ROM contents for each record subelement (except for the scalar C_IN ), you will be required to provide detailed data later as you input actual operands and OPCODEs You can save overall time by explicitly assigning ‘0’ or “0000” to each sub-element, then simply modifying the assignments later Memory and Record Lab www.xilinx.com 1-877-XLX-CLAS 10b-6 Perform a syntax check In the Sources for window, select MEM.vhd and in the Processes window, double-click Check Syntax Correct any errors Ask for help from the instructor if needed ! ! Note that if you attempt to view the RTL schematic at this point, the schematic drawn by the tool looks incomplete This reflects the post-synthesis optimization performed because each and every value stored in the array is the same at this point Conclusion In this exercise, you first created a package to store elements that will be used repeatedly throughout your design Next, you created a user-defined record data type to enhance readability for a composite grouping of sub-elements Finally, you created a synchronous memory element whose structure was based on the record data type defined earlier The memory was defined as a ROM, which is a constant; therefore, you were required to assign values at the time of declaration You loaded dummy data for now; 0’s or X’s Later, you will update the ROM contents with actual values as you use the MEM submodule within the upper-level SIMPLE_CALC module Memory and Record Lab www.xilinx.com 1-877-XLX-CLAS 10b-7 A Answers CALC1_PACKAGE File library IEEE; use IEEE.STD_LOGIC_1164.all; package CALC1_PAK is type MY_RECORD is record A_IN : std_logic_vector ( downto ); B_IN : std_logic_vector ( downto ); OP_CODE : std_logic_vector ( downto ); C_IN : std_logic; EXP_OUT : std_logic_vector ( downto ); end record ; end package CALC1_PAK ; Memory and Record Lab www.xilinx.com 1-877-XLX-CLAS 10b-8 MEM Module library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.CALC1_PAK.ALL; entity MEM is port ( CLK, READ_EN: in std_logic ; ADDR : in std_logic_vector(2 downto 0):="000"; initialize for simulation DATA_FRAME : out MY_RECORD ); end entity MEM; architecture RTL of MEM is type ROM_ARRAY is array ( to ) of MY_RECORD; constant MY_ROM : ROM_ARRAY := ( => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ), => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ), => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ), => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ), => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ), => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ), => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ), => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" )); - Example of ROM with actual contents, to be used later -constant MY_ROM : ROM_ARRAY := ( => ( A_IN => "1000", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "1010"), => ( A_IN => "0100", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "0110" ), => ( A_IN => "0010", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "0100" ), => ( A_IN => "0001", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "0011" ), => ( A_IN => "0011", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "0101" ), => ( A_IN => "0111", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "1001" ), => ( A_IN => "0111", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "1001" ), => ( A_IN => "0111", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "1001")); begin process ( CLK ) begin if rising_edge ( CLK) then if ( READ_EN = '1') then DATA_FRAME