SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices Edited by John D Cressler Boca Raton London New York CRC Press is an imprint of the Taylor & Francis Group, an informa business The material was previously published in Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy © Taylor and Francis 2005 CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2008 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S Government works Printed in the United States of America on acid-free paper 10 International Standard Book Number-13: 978-1-4200-6685-2 (Hardcover) This book contains information obtained from authentic and highly regarded sources Reprinted material is quoted with permission, and sources are indicated A wide variety of references are listed Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use Except as permitted under U.S Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers For permission to photocopy or use material electronically from this work, please access www.copyright.com (http:// www.copyright.com/) or contact the Copyright Clearance Center, Inc (CCC) 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400 CCC is a not-for-profit organization that provides licenses and registration for a variety of users For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe Library of Congress Cataloging-in-Publication Data SiGe and Si strained-layer epitaxy for silicon heterostructure devices / editor, John D Cressler p cm Includes bibliographical references and index ISBN 978-1-4200-6685-2 (alk paper) Bipolar transistors Materials Heterostructures Silicon Electric properties Epitaxy I Cressler, John D TK7871.96.B55S53 2008 621.3815’28 dc22 Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com 2007030343 For the tireless efforts Of the many dedicated scientists and engineers Who helped create this field and make it a success I tip my hat, and offer sincere thanks from all of us Who have benefitted from your keen insights and imaginings And For Maria: My beautiful wife, best friend, and soul mate for these 25 years For Matthew John, Christina Elizabeth, and Joanna Marie: God’s awesome creations, and our precious gifts May your journey of discovery never end He Whose Heart Has Been Set On The Love Of Learning And True Wisdom And Has Exercised This Part of Himself, That Man Must Without Fail Have Thoughts That Are Immortal And Divine, If He Lay Hold On Truth Plato ồòớùũ ù íữồỉ ọỵúồỉ ụỗớ ữị ụù úụỗớ `êĩỗ êỉặ èĩỗúỗ ặỉ `ỗỉớị ểùòặ, ặỉ íữồỉ `úỗồò êỉặ ụùýụù, ớặũ ụíụùỉùũ ỡỹớù Âớọổặũ ỡùổồò ụù ọòữứũ ĩù ớặ ĩớồỉ úíồỉũ `ĩớặụồũ ặỉ ăồòồũ, ĩớ úụỗổỉữồò úụỗớ `ịồỉặ Pl atvnaĐ Foreword Progress in a given field of technology is both desired and expected to follow a stable and predictable long term trajectory Semilog plots of technology trends spanning decades in time and orders of magnitude in value abound Perhaps the most famous exemplar of such a technology trajectory is the trend line associated with Moore’s law, where technology density has doubled every 12 to 18 months for several decades One must not, however, be lulled into extrapolating such predictability to other aspects of semiconductor technology, such as device performance, or even to the long term prospects for the continuance of device density scaling itself New physical phenomena assert themselves as one approaches the limits of a physical system, as when device layers approach atomic dimensions, and thus, no extrapolation goes on indefinitely Technology density and performance trends, though individually constant over many years, are the result of an enormously complex interaction between a series of decisions made as to the layout of a given device, the physics behind its operation, manufacturability considerations, and its extensibility into the future This complexity poses a fundamental challenge to the device physics and engineering community, which must delve as far forward into the future as possible to understand when physical law precludes further progress down a given technology path The early identification of such impending technological discontinuities, thus providing time to ameliorate their consequences, is in fact vital to the health of the semiconductor industry Recently disrupted trends in CMOS microprocessor performance, where the ‘‘value’’ of processor operating frequency was suddenly subordinated to that of integration, demonstrate the challenges remaining in accurately assessing the behavior of future technologies However, current challenges faced in scaling deep submicron CMOS technology are far from unique in the history of semiconductors Bipolar junction transistor (BJT) technology, dominant in high end computing applications during the mid 1980s, was being aggressively scaled to provide the requisite performance for future systems By the virtue of bipolar transistors being vertical devices rather than lateral (as CMOS is), the length scale of bipolar transistors is set by the ability to control layer thicknesses rather than lateral dimensions This allowed the definition of critical device dimensions, such as base width, to values far below the limits of optical lithography of the day Although great strides in device performance had been made by 1985, with unity gain cutoff frequencies (fT ) in the range 20 30 GHz seemingly feasible, device scaling was approaching limits at which new physical phenomena became significant Highly scaled silicon BJTs, having base widths below 1000 A˚, demonstrated inordinately high reverse junction leakage This was due to the onset of band to band tunneling between heavily doped emitter and base regions, rendering such devices unreliable This and other observations presaged one of the seminal technology discontinuities of the past decade, silicon germanium (SiGe) heterojunction bipolar transistor (HBT) technology being the direct consequence Begun as a program to develop bipolar technology with performance capabilities well beyond those possible via the continued scaling of conventional Si BJTs, SiGe HBT technology has found a wealth of applications beyond the realm of computing A revolution in bipolar fabrication methodology, moving vii viii Foreword from device definition by implantation to device deposition and definition by epitaxy, accompanied by the exploitation of bandgap tailoring, took silicon based bipolar transistor performance to levels never anticipated It is now common to find SiGe HBTs with performance figures in excess of 300 GHz for both fT and fmax , and circuits operable at frequencies in excess of 100 GHz A key observation is that none of this progress occurred in a vacuum, other than perhaps in the field of materials deposition The creation of a generation of transistor technology having tenfold improved performance would of itself have produced far less ultimate value in the absence of an adequate eco system to enable its effective creation and utilization This text is meant to describe the eco system that developed around SiGe technology as context for the extraordinary achievement its commercial rollout represented Early SiGe materials, of excellent quality in the context of fundamental physical studies, proved near useless in later device endeavors, forcing dramatic improvements in layer control and quality to then enable further development Rapid device progress that followed drove silicon based technology (recall that SiGe technology is still a silicon based derivative) to unanticipated performance levels, demanding the development of new characterization and device modeling techniques As materials work was further proven SiGe applications expanded to leverage newly available structural and chemical control Devices employing ever more sophisticated extensions of SiGe HBT bandgap tailoring have emerged, utilizing band offsets and the tailoring thereof to create SiGe based HEMTs, tunneling devices, mobility enhanced CMOS, optical detectors, and more to come Progress in these diverse areas of device design is timely, as I have already noted the now asymptotic nature of performance gains to be had from continued classical device scaling, leading to a new industry focus on innovation rather than pure scaling Devices now emerging in SiGe are not only to be valued for their performance, but rather their variety of functionality, where, for example, optically active components open up the prospect of the seamless integration of broadband communication functionality at the chip level Access to high performance SiGe technology has spurred a rich diversity of exploratory and com mercial circuit applications, many elaborated in this text Communications applications have been most significantly impacted from a commercial perspective, leveraging the ability of SiGe technologies to produce extremely high performance circuits while using back level, and thus far less costly, fabricators than alternative materials such as InP, GaAs, or in some instances advanced CMOS These achievements did not occur without tremendous effort on the part of many workers in the field, and the chapters in this volume represent examples of such contributions In its transition from scientific curiosity to pervasive technology, SiGe based device work has matured greatly, and I hope you find this text illuminating as to the path that maturation followed Bernard S Meyerson IBM Systems and Technology Group Preface While the idea of cleverly using silicon germanium (SiGe) and silicon (Si) strained layer epitaxy to practice bandgap engineering of semiconductor devices in the highly manufacturable Si material system is an old one, only in the past decade has this concept become a practical reality The final success of creating novel Si heterostructure transistors with performance far superior to their Si only homojunction cousins, while maintaining strict compatibility with the massive economy of scale of conventional Si integrated circuit manufacturing, proved challenging and represents the sustained efforts of literally thousands of physicists, electrical engineers, material scientists, chemists, and technicians across the world In the electronics domain, the fruit of that global effort is SiGe heterojunction bipolar transistor (SiGe HBT) BiCMOS technology, and strained Si/SiGe CMOS technology, both of which are at present in commercial manufacturing worldwide and are rapidly finding a number of important circuit and system applications As with any new integrated circuit technology, the industry is still actively exploring device performance and scaling limits (at present well above 300 GHz in frequency response, and rising), new circuit applications and potential new markets, as well as a host of novel device and structural innovations This commercial success in the electronics arena is also spawning successful forays into the optoelectronics and even nanoelectronics fields The Si heterostructure field is both exciting and dynamic in its scope The implications of the Si heterostructure success story contained in this book are far ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of the twenty first century While several excellent books on specific aspects of the Si heterostructures field currently exist (for example, on SiGe HBTs), this is the first reference book of its kind that ‘‘brings it all together,’’ effectively presenting a comprehensive perspective by providing very broad topical coverage ranging from materials, to fabrication, to devices (HBT, FET, optoelectronic, and nanostructure), to CAD, to circuits, to applica tions Each chapter is written by a leading international expert, ensuring adequate depth of coverage, up to date research results, and a comprehensive list of seminal references A novel aspect of this book is that it also contains ‘‘snap shot’’ views of the industrial ‘‘state of the art,’’ for both devices and circuits, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global Si heterostructure industry This book is intended for a number of different audiences and venues It should prove to be a useful resource as: A hands on reference for practicing engineers and scientists working on various aspects of Si heterostructure integrated circuit technology (both HBT, FET, and optoelectronic), including materials, fabrication, device physics, transistor optimization, measurement, compact modeling and device simulation, circuit design, and applications A hands on research resource for graduate students in electrical and computer engineering, physics, or materials science who require information on cutting edge integrated circuit technologies ix rsu csu rth cth cjei0 vdei zei aljei cjep0 vdep zep aljep ceox cjci0 vdci zci vptci cjcx0 vdcx zcx vptcx ccox fbc cjs0 vds zs vpts t0 dt0h tbvl tef0 gtfe Substrate network Self-heating Base–emitter junction capacitance Base–collector junction capacitance Collector–substrate junction capacitance Diffusion capacitances/transit times—low currents High currents msc itss msf msr tsf (Continued) 40Â10À15 sec 1.0 2.6Â10À12 sec 0.9Â10À12 sec 0.7Â10À12 sec Low current forward transit time at Vcb ¼ V Time constant for base and BC space charge layer width modulation Time constant for modeling carrier jam at low Vce Neutral emitter storage time Exponent for current dependence of neutral emitter storage time 40Â10À15 F 0.6 V 0.3 1Â1010 V 7Â10À15 F 0.7 V 0.3 2.5 V 30Â10À15 F 0.73 V 0.4 100 V 2.5Â10À15 F 0.8 35Â10À15 F 1.0 V 0.32 2.0 5Â10À15 F 1.0 V 0.32 2.2 18Â10À15 F 700 K/W 350 pJ/K 50 V (layout dependent) 3Â10À18 F 2.5Â10À19 A 1 2Â10À12 sec Zero-bias CS depletion capacitance CS built-in voltage CS grading coefficient Punch-through voltage of CS junction Internal zero-bias BC depletion capacitance Internal BC built-in voltage Internal BC grading coefficient Punch-through voltage of internal BC junction External zero-bias BC depletion capacitance External BC built-in voltage External BC grading coefficient Punch-through voltage of external BC junction BC overlap capacitance Partitioning factor for cjcx and ccox over rbx Internal zero-bias BE depletion capacitance Internal BE built-in voltage Internal BE grading coefficient Maximum internal depletion capacitance divided by cjei0 Peripheral zero-bias BE depletion capacitance Peripheral BE built-in voltage Peripheral BE grading coefficient Maximum peripheral depletion capacitance divided by cjep0 Emitter oxide (overlap) capacitance Thermal resistance Thermal capacitance Substrate resistance Substrate capacitance CS diode non-ideality factor Transfer saturation current of substrate transistor Forward non-ideality factor of substrate transfer current Reverse non-ideality factor of substrate transfer current Transit time (forward operation)—substrate Sample SiGe HBT Compact Model Parameters A.4 kf af krbi tnom vgb alb alfav alqav zetaci alvs alces zetarbi zetarbx zetarcx zetare alt0 kt0 Noise parameters Temperature effect parameters Measurement temperature Bandgap voltage Temperature coefficient of current gain Temperature coefficient of favl Temperature coefficient of qavl Temperature coefficient for mobility in epi-collector (i.e., for collector resitance) Relative temperature coefficient of saturation drift velocity Relative temperature coefficient of vces Temperature coefficient for mobility in internal base (i.e., for internal base resistance) Temperature coefficient for mobility in extrinsic base (i.e., for extrinsic base resistance) Temperature coefficient for mobility in extrinsic collector (i.e., for extrinsic collector resistance) Temperature coefficient for emitter resistance First-order temperature coefficient of t0 Second-order temperature coefficient of t0 Flicker noise factor Flicker noise exponent factor Noise factor for internal base resistance Factor for additional delay time of minority charge Factor for additional delay time of transfer current Saturation time constant at high current densities Smoothing factor for current dependence of base and collector transit time Factor for partitioning this into base and collector portion Internal C-E saturation voltage Internal collector resistance at low electric field Voltage separating ohmic (low field) and saturation velocity (high field) regime Collector punch-through voltage Storage time for inverse operation thcs alhc fthc vces rci0 vlim vpt tr alqf alit Parameter Description Name Non-quasistatic effects Group TABLE A.4.1 HICUM (v 2.1) SiGe HBT Model Parameters (Continued) 25 C 1.17 V 6Â10À3 5Â10À5 KÀ1 2Â10À4 KÀ1 1.6 1Â10À3 KÀ1 0.4Â10À3 KÀ1 0.6 0.2 0.2 1Â10À3 KÀ1 1Â10À5 KÀ2 22Â10À6 2.5 0.125 0.45 25Â10À12 sec 0.53 0.6 0.1 V 20 V 0.7 V 15 V 20Â10À12 sec Value A.4 SiGe and Si Strained Layer Epitaxy for Silicon Heterostructure Devices Name is ik bf ibf mlf xibi bri ibr vlr xext ver vef wavl vavl sfh re rbc rbv rcc rcv scrcv ihc axi cje vde pe xcje cbeo cjc vdc pc xp Group Forward and reverse currents Early voltage Weak avalanche Resistances and quasisaturation Base–emitter junction capacitance Base–collector junction capacitance TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters Zero–bias collector–base depletion capacitance Collector–base diffusion voltage Colector–base grading coefficient Constant part of cjc Zero-bias emitter–base depletion capacitance Emitter–base diffusion voltage Emitter–base grading coefficient Fraction of the emitter–base depletion capacitance that belongs to the side-wall Emitter–base overlap capacitance Emitter resistance Constant part of the base resistance Zer-bias value of the bias-dependent base resistance Constant part of the collector resistance Resistance of the un-modulated epilayer Space charge resistance of the epilayer Critical current for velocity saturation in the epilayer Smoothness parameter for the onset of quasi-saturation Epilayer thickness used in weak-avalanche model Voltage determining curvature of avalanche current Current spreading factor of avalanche model (when exavl ¼ 1) Reverse Early voltage Forward Early voltage Transistor main saturation current Knee current for high-injection effects in the base Ideal forward current gain Saturation-current of the non-ideal forward base current Non-ideality factor of the non-ideal forward base current Sidewall component of ideal base current Ideal reverse current gain Saturation current of the non-ideal reverse base current Cross-over voltage of the non-ideal reverse base current Partitioning factor for the extrinsic region Parameter Description (Continued) 7Â10À15 F 0.75 V 0.28 1Â10À3 42Â10À15 F 0.9 V 0.23 18Â10À15 F 3.0 V 6V 20 V 17 V 52 V 54 V 3.56Â10À3 A 0.21 2.44Â10À7 M 0.63 V 1.7 4.8 V 65 V 5Â10À18 A 4.5Â10À2 A 95 2Â10À17 A 1.545 3.77 1.7Â10À15 A 1Â10À2 V 0.19 Value Sample SiGe HBT Compact Model Parameters A.4 deg xrec aqbo ae ab aepi aex ac as dvgbf dvgbr vgb vgc vgj dvgte af kf kfn iss iks rth cth HBT parameters Temperature coeffcients 1/f Noise Substrate transistor Self-heating network Diffusion capacitances/transit times Thermal resistance Thermal capacitance Base-substrate saturation current Base-substrate high-injection knee current Exponent of the flicker noise Flicker-noise coefficient of the ideal base current Flicker noise coefficient of the non-ideal base current Temperature coefficient of the zero-bias base charge Temperature coefficient of the resistivity of the emitter Temperature coefficient of the resistivity of the base Temperature coefficient of the resistivity of the epilayer Temperature coefficient of the resistivity of the extrinsic base Temperature coefficient of the resistivity of the buried layer Temperature coefficient for Iss and Iks (for a closed buried layer, as¼ac and for an open buried layer, as¼aepi) Bandgap voltage difference for forward current gain Bandgap voltage difference for reverse current gain Bandgap voltage of the base Bandgap voltage of the collector Bandgap voltage: recombination of the emitter–base junction Bandgap voltage difference of emitter stored charge Bandgap difference over the base Pre-factor of the recombination part of ideal base current Zero-bias collector–substrate depletion capacitance Collector–substrate diffusion voltage Collector–substrate grading coefficient Bandgap voltage of the substrate Non-ideality factor for the emitter stored charge Minimum transit time of stored emitter charge Transit time of stored base charge Transit time of stored epilayer charge Transit time of reverse extrinsic stored base charge Coefficient for the current modulation of the collector–base depletion capacitance Fraction of the collector–base depletion capacitance under the emitter Collector–base overlap capacitance mc xcjc cbco cjs vds ps vgs mtau taue taub tepi taur Parameter Description Name Collector–substrate junction capacitance Group TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters (Continued) 700 K/W 350 pJ/K 2.5Â10À19 A 50 A 2.5 22Â10À6 20Â10À12 0.34 1.22 1.88 8.7Â10À7 0.76 3.75Â10À2 V 4.38Â10À2 V 1.15 V 1.18 V 1.15V 0.236 V 0.03 eV 45Â10À15 F 0.6 V 0.3 1.17 V 0.388 52Â10À15 sec 1.44Â10À12 sec 14.4Â10À12 sec 20Â10À12 sec 0.5 8.7Â10À2 2.5Â10À15 F Value A.4 SiGe and Si Strained Layer Epitaxy for Silicon Heterostructure Devices Name is ibei iben ibci ibcn isp ibcip ibcnp ibeip ibenp nf nei nen nr nci ncn nfp ncip ncnp ikf ikr ikp avc1 avc2 rbi rbx rbp re rcx rs rth cth Group Saturation currents and ideality factors Knee currents Avalanche breakdown Series resistances Self-heating TABLE A.4.3 VBIC SiGe HBT Model Parameters Thermal resistance Thermal capacitance Intrinsic base resistance Extrinsic base resistance Parasitic base resistance Emitter resistance Extrinsic collector resistance Substrate resistance Base–collector weak avalanche parameter Base–collector weak avalanche parameter Forward knee current Reverse knee current Parasitic knee current Transport saturation current (collector) Ideal base–emitter saturation current Nonideal base–emitter saturation current Ideal base–collector saturation current Nonideal base–collector saturation current Parasitic transport saturation current Ideal parasitic base–collector saturation current Nonideal parasitic base–collector saturation current Ideal parasitic base–emitter saturation current Nonideal parasitic base–emitter saturation current Forward emission coefficient Ideal base–emitter emission coefficient Nonideal base–emitter emission coefficient Reverse emission coefficient Ideal base–collector emission coefficient Nonideal base–collector emission coefficient Parasitic forwad emission coefficent Ideal parasitic base–collector emission coefficient Nonideal parasitic base–collector emission coefficient Parameter Description (Continued) 700 K/W 350 pJ/W 20 V 6V 1V 3V 23 V 50 V 19.2 23.6 V 4.5Â10À2 A 4.8Â10À3 A 10 A 1Â10À40 A 2.52Â10À18 A 1Â10À28 A 1.0003 1.026 2.5 1.02 1.00 1.00 1.00 4.85Â10À18 A 7Â10À20 A 1Â10À15 A 1.5Â10À18 A 1Â10À34 A 3Â10À19 A Value Sample SiGe HBT Compact Model Parameters A.4 Name rci vo gamm hrcf qco vef ver cje me pe cbeo fc aje cjc mc pc cbco cjep ajc cjcp ms ps ccso ajs tf itf vtf qtf td ea eaie eaic eais eanc Group Quasi-saturation parameters Early effect parameters Base–emitter junction capacitance Base–collector junction capacitance Collector–substrate junction capacitance Transit times and their bias dependence Temperature effect parameters TABLE A.4.3 VBIC SiGe HBT Model Parameters (Continued) Activation energy Activation energy Activation energy Activation energy Activation energy for is for ibei for ibci and ibeip for ibcip for ibcn/ibenp Forward transit time Coefficient of tf dependence of ic Coefficient of tf dependence of Vbc Variation of tf with base-width modulation Forward excess-phase delay time Substrate–collector zero bias capacitance Substrate–collector grading coefficient Substrate–collector built-in potential Fixed collector–substrate capacitance Substrate–collector capacitance switching parameter Base–collector intrinsic zero-bias capacitance Base–collector grading coefficient Base–collector built-in potential Extrinsic base–collector overlap capacitance Base–collector extrinsic zero bias capacitance Base–collector capacitance switching parameter Base–emitter zero-bias capacitance Base–emitter grading coefficient Base–emitter built-in potential Extrinsic base–emitter overlap capacitance Forward bias depletion capacitance limit Base–emitter capacitance switching parameter Forward Early voltage Reverse Early voltage Intrinsic collector resistance Epi drift saturation voltage Epi doping parameter High-current RC factor Epi-charge parameter Parameter Description 1.17 V 1.17 V 1.17 V 1.17 V 1.17 V 2Â10À12 sec 0.32 23.7 0.7Â10À12 sec 40Â10À15 F 0.3 0.6 V 3eÀ18 F À0.9 7Â10À15 F 0.3 0.7 V 2.5Â10À15 F 30Â10À15 F À0.1 42 fF 1.0 0.3 V 18Â10À15 F 0.93 À0.1 65 V 5.5 V 40 V 1Â10À10 V 5Â10À13 V 1Â10À13 1.4Â10À15 Value A.4 SiGe and Si Strained Layer Epitaxy for Silicon Heterostructure Devices eane eans xii xin xis xre xrb xrc xrs xvo tavc Activation energy for iben Activation energy for ibcnp Temperature coefficient for ibei, ibci, ibeip, and ibcip Temperature coefficient for iben, ibcn, ibenp, and ibcnp Temperature coefficient for is Temperature coefficient for re Temperature coefficient for rbi Temperature coefficient for rc Temperature coefficient for rs Temperature coefficient for vo Temperature coefficient for avc2 1.17 V 1.17 V 2.0 2.0 1.9 0 0 250Â10À6 V Sample SiGe HBT Compact Model Parameters A.4 A.4 10 SiGe and Si Strained Layer Epitaxy for Silicon Heterostructure Devices References HICUM bipolar transistor model: http://www.iee.et.tu dresden.de/iee/eb/comp mod.html Mextram bipolar transistor model: http://www.semiconductors.phillips.com/acrobat/other/phillips models/NLUR2000811 7.pdf VBIC bipolar transistor model: http://www.designers guide.org/VBIC/references.html Index A Activation energy, 8 5, 8 15 Airy stress function, 2, 4, Anharmonic Keating model, 11 Antimony diffusion, in SiGe, 13 Arrhenius plot, 8, 10, 16, Arsenic diffusion, in SiGe, 12 ASICs, Atmospheric pressure CVD (AP CVD), 3, Auger electron spectroscopy (AES), B Bandgap energy, of strained Si on relaxed SiGe, 10 Bandgap engineering, 4, 2 4, 1, 9, 36 Bartel’s monochromators, 4 Base transit time, A.2 Bipolar complementary metal oxide semiconductor (BiCMOS) technology, Bipolar junction transistor (BJT), Boron diffusion, in SiGe, 13 Bragg’s law, 4 Burgers vector, C Capacitance voltage profiling, 10 Carbon doping, of SiGe adatom substitution, 11 basic considersations, 11 C containing alloys, growth of, 11 11 carbon concentrations, effect of, 11 defect formation, 11 dopant diffusion, control of, 11 11 thermal stability, 11 Carbon precipitation, 11 Carbon substitutionality, 11 Carrier mobility, Centura HTF reactor, Chemical loading, in SiGe growth, 22 24 Chemical vapor deposition (CVD), 3, 8, 11 CMOS quiescent current, Code division multiple access (CDMA), Complementary metal oxide semiconductor (CMOS), 12 Conduction band offset, for strained Si/relaxed SiGe heterojunctions, 10 Contact metallization, 12 12 Conventional emitter doping (CED) transistors, A.3 Critical thickness, of SiGe/Si layers, 9 D Deep level transient spectroscopy (DLTS), Defect populaiton, in bandgap, Dessis device simulator, 10 Dichlorosilane (DCS), Diffusion, in SiGe dopant diffusion antimony, 13 boron, 13 14 phosphorus, 13 mechanism of, self diffusion, 10 12 strain, effect of, 10, 14 15 Dimerization, Dislocations, 16 Divacancies, Doping, 6 7, Double gate MOS (DG MOS) transistors, 32 33 Drain induced barrier lowering (DIBL), 33, 34 Dry etching, 13 Dual channel MOS capacitor, 10 E Effective lattice mismatch, 11 Elastic strain, 2, 6, 7, 10, 13 Elasticity theory, Electron mobility enhancement, in strained Si/relaxed SiGe n MOSFETs, 10 10 Electron paramagnetic resonance (EPR), Electron trap, Emitter coupled logic (ECL) ring oscillator, Energy band lineups measurement of for Si/Si1 yCy system, 10 10 10 strained Si/strained Si1 yGey/relaxed Si1 xGex system, 10 10 silicon heterostructures, 10 I1 I2 SiGe and Si Strained Layer Epitaxy for Silicon Heterostructure Devices Energy bandgap difference, between SiGe alloys and Si, 10 Energy bands, for strained SiGe on Si, 10 Epitaxial deposition methods, Epsilon one reactor, Equilibrium lattice parameter, 10 Equilibrium theory, 1, 2, 7, 9, 10, 13 Etch rates (ERs), 13 2, 13 Etching, 32; see also Selective etching Ex situ wet chemical treatment, Excess resolved shear stress, 7, 9 10, 12 F FD silicon on insulator (SOI), 34 36 Fermi level pinning, 12 Film stress, of SiGe/Si layers, 9 Force balance model, for buried SiGe strained layers, 10 13 Frank Turnbull reaction, 11 Frank van der Merwe herteroexpitaxial growth, 4 FSA emitter base structure, 30 G Gate dielectrics, 12 Gate gll ground (GAA) MOSFETs, 13 17 13 20 Ge concentration, in SiGe, effective mass parameters, A.1 energy band structure, A.1 equilibrium lattice parameters, 10 intertsitial related interactions, properties of, A.1 segregation, 12 vacancy impurity complexes, 8 Generalized ICCR (GICCR), A.3 A.3 6, A.3 13 Germanosilicides, 12 Gibbs free energy, 12 Global loading effect, 21, 23 Global positioning systems (GPS), Global system for mobile communications (GSM), Green function method, Growth rate (GR), Gummel plots, 31 H H2 prebake, Heterojunction bipolar transistors (HBTs), 10 2, 10 Heterojunction transistors, charge control relation, A.3 A.3 12 Heterostructure MOSFET, 12 HF last clean, HICUM (v 2.1) SiGe HBT model parameters, A.4 A.4 High electron mobility transistors (HEMTs), Hole mobility, in strained SiGe, 10 11 Hole trap, Homojunction transistors, charge control relation, A.3 A.3 Hooke’s law, Hydrogen desorption, I Image force method, for strained layer relaxation, 92 94 In situ H2 prebake, In plane epitaxial film stress, 9 10 In plane misfit strain, 6, 7, 9 Integral charge control relation (ICCR), A.3 hetereojunction transistors, A.3 A.3 12 homojunction transistors, A.3 A.3 International Technology Roadmap for Semiconductors (ITRS), 1, 16, 12 Interstitial related interactions, in Si and Ge, 8 Intrinsic defects, and impurities, 8 Intrinsic defects, in SiGe alloy composition, effect of on electronic properties, 8 on formation energies, effect of strain, Inversely distorted, SiGe cell, 11 Ion implantation defects, in silicon, 2, Ion implantation process, 9, 11 2, 11 J Jahn Teller distortions, K Kroemer’s approach, A.2 L Laplace deep level transient spectroscopy (LDLTS), Lattice constant, Lattice mismatch, in Si, 10 1, 10 2, 10 10 Lattice vacancy in Ge, 8 in Si, 8 Limited reaction processing (LRP), Limited reaction processing CVD (LRP CVD), 22 24 Loading effects chemical, 22 23 definition, 21 thermal, 21 22 Local loading effect, 21, 24 Low emitter concentration (LEC) transistors, A.3 Low energy plasma enhanced (LEPE) CVD, 3, 12 Low pressure CVD (LP CVD), 1, 11 I3 Index Low temperature deposition techniques, Low temperature epitaxy (LTE) process, Low temperature Si epi growth techniques, M Metal silicides, 12 Metastable alloys, 11 Methylsilane silane flow ratio, 13 MEXTRAM 504 model parameters, A.4 A.4 Microelectromechanical systems (MEMS), and SON technology, 13 20 13 21 Misfit dislocation (s), 2, 11, 12, 20, 28, 29, 2, Misfit dislocation image dislocation pair, 6, 11 Modulus of complex dislocation, 3, Molecular beam epitaxy (MBE), cleaning scheme, doping in, 6 effusion cell, 6 electron beam source, 6 Ge evaporation, in situ analysis, pressure requirement, problems with, 6 substrate heating, temperature control, UHV requirements, 6 Moll Ross collector current density relation, A.2 Moll Ross relation assumptions for, A.2 generalized, A.2 Moore’s law, MOS capacitance voltage (C V) method, 10 MOS capacitor, with dual channel heterostructure, 10 6, 10 MOSFET, 11 4, 12 Point defects, 8 3, 7, 9, 16 Point defect species, equilibrium concentration of, Poly SiGe gate technology, 12 Polysilicon gate electrodes, 12 Polysilicon, phosphorous doped, 32 Positron annihilation spectroscopy, 8 Pt Silicide, 12 Pyrolysis, 7 Q Quadrupole mass spectrometer (QMS), 6 R Rapid thermal anneal (RTA), 12 Rapid thermal chemical vapor deposition (RT CVD), for Si SiGe(C) epitaxy advantages and disadvantages, 5 applications of double gate MOS (DG MOS), 32 34 FD SOI, 34 36 SEG based bipolar, 30 32 epitaxy techniques, comparison, 5 equipments for, low temperature epi (LTE), difficulties in deposition morphology, 24 27 loading effects (see Loading effects) pattern induced defectivity, 28 29 thermal budget limitation, 19 20 reactor, 5 steps in, 5 Reflection high energy electron diffraction (RHEED), Reflectionsupported pyrometric interferometry (RSPI), Relaxed Si epitaxial layers, lattice structures, 10 Resolved shear stress, 3, 9 7, 9, 10, 12 N Ni silicide, lattice structure, 12 Ni Si Ge ternary system, pseudophase diagrams, 12 Ni silicided films, 12 Ni silicided Si1 xGex films, 12 NMOS SON transistor, 13 14 npn bipolar transistors, electron mobillity, 11 Nuclear magnetic resonance (NMR) technique, 8 P Perturbed angular correlation (PAC) spectroscopy, 4, Phosphorus diffusion, in SiGe, 13 Phosphorus doped polysilicon, 32 Photolithography, 32, 13 18 Plastic deformation, in SiGe/Si, 9 10 PMOS SON device, 13 14 S Scaling of, Si film, 13 10 Schottky diode, 10 Secondary ion mass spectroscopy (SIMS), Selective epitaxial growth (SEG), 16 18, 24, 27, 29, 11 2, 12 Selective etching, Selective SiGe etching CMOS realization, 13 11 etch rate evolution, 13 Ge content, effect of, 13 limitation of, 13 parameters affecting, 13 13 process, 13 selective passivation, 13 selectivity determination, 13 Si loss during, 13 I4 SiGe and Si Strained Layer Epitaxy for Silicon Heterostructure Devices tool for, 13 tunnel etching, 13 13 tunnel realization, 13 Self aligned silicide process, 12 Self diffusion, SiGe, 10 12 Shallow trench isolation (STI) process, 13 11 Shibaura CDE 80 etching tool, 13 Shockley boundary condition, generelized, A.2 2, A.2 Short channel effects (SCE), 32, 11 4, 13 17 Si boron diffusion, 11 carbon doping of, 11 11 effective mass parameters, A.1 energy band structure, A.1 energy bands, effects of stresses, 10 equilibrium lattice parameters, 10 interstitial related interactions, 5, ion implantation defects, 2, lattice vacancy, 8 properties of, A.1 vacancy impurity complexes, 8 vacancy related defects, Si electron beam evaporator, in MBE, Si based high electron mobility transistors (HEMTs), 10 light emitters, 10 optoelectronic superchip, 10 transistor (s), 2, Si C phase diagram, 11 Si SiGe(C) epitaxy, using rapid thermal chemical vapor deposition (RT CVD) carbon incorporation, 12 16 development, 12 kinetics of, 13 nature of, 13 16 germanium incorporation kinetics, 10 strain effects, 11 loading effects, 21 23 low temperature epi, conclusion, growth rate (GR) plots, silane based, pattern induced defectivity, 28 29 quality of, 15 selective epitaxial growth (SEG), 16 18 surface preparation, Si strained layer epitaxy, SiGe alloys, 4, 1, 9, 8, 10 2, 12 SiGe cell, inversely distorted, 11 SiGe epitaxy, stability in, 9 10 SiGe fabrication facilities, SiGe grains, and germanosilicide grains, 12 10 SiGe HBT BiCMOS technology, generations, 5, 10 SiGe HBTs characterization techniques, development of, graded Ge base profile, A.2 high power, technology generations, performance of, 10 SiGe ICs applications, SiGe molecular beam epitaxy (MBE) system commercial, flux monitor, role of, growth chamber, schematic of, heater system in, pressure requirement, purpose of, residual gas spectrum, SiGe silicidation, 12 12 11 SiGe strained layer epitaxy, SiGe wireless transceiver, SiGe Si strained layer epitaxy, development of, 2 SiGe strained Si FETs development, SiGe:C channel pMOSFET, SiGe:C HBT technology, SiGe:C, deposition on Si, SiGeC films, boron SIMS profiles, 30 SiGeC layers, microscopic structure, 11 SiGeC SEG based HBT, gummel characteristics, 31 SiGeC silicidation, 12 11 SiH2Cl2, see Dichlorosilane Silane, 9, Silicidation of SiGe, 12 12 11 of SiGeC, 11 Silicide applications, Si CMOS Technology, 12 Silicide thickness, 12 Silicon bridge over active zone, SiGe, 33 Silicon on insulator (SOI), 34 Silicon germanium heterojunction bipolar transistor, see SiGe HBT Silicon on nothing (SON) process, 32 gate silicidation process, 13 15 gate all around (GAA) MOSFETs using, 13 17 13 20 microelectromechanical systems (MEMS) and, 13 20 13 21 MOSFET fabrication steps, 13 12 multigate device implementation, 13 20 thin films fabrication using, 13 10 without channel rupture, 13 16 Solid phase epitaxy (SPE), 11 SON MOSFETs, 13 14 13 16 SON tunnel wet etching, 13 10 Source/drain (S/D) parasitic series resistance, 12 Specific defects, in SiGe interstitial related defects, 8 metallic impurities, shallow dopants, 8 vacancy related defects, 8 Spectroscopic ellipsometry (SE), Stored elastic strain energy, 10 12 Strain stabilized layers, 11 Strained layer relaxation, 9 Strained Si /relaxed SiGe n MOSFETs, 10 10 Strained Si CMOS, 2, 6, 10, 11 I5 Index Strained Strained Strained Strained Si fabrication facilities, Si layers, characterization of, 4 Si nMOSFET, Si/relaxed SiGe heterojunctions, band offsets, 10 Strained SiGe heteroepitaxy, on Si characterization, of layers, 4 deposition rate, control of, growth modes, 4 layer growth, low temperature requirement, 10 substrate cleaning, TEM cross section, Strained SiGe layers, characterization of using x ray diffractometry (XRD ), 4 diffraction curve, rocking curves, Stranski Krastanow growth, 4, 11 STRATA plasma reactor, 13 11 Surface relaxation stress, 9 Synchronous optical network (SONET), T Temperature programmed desorption (TPD), Thermal budget limitation, 19 20 Thermal loading, in SiGe growth, 21 22 TiSi2 film resistivity, 12 Total misfit strain, in Si capped SiGe epilayer, 12 Transient ICCR (TICC), A.3 Transientenhanced diffusion (TED), 11 Transmission electron microscopy (TEM), 1, Tunnel etching, for SiGe, 13 Tunneling current, 12 U Ultrahigh vacuum chemical vapor deposition (UHV/ CVD), 3, alloys used, 7 chemical reactions in, clean reactor environment, deposition rate, dopant diffusion, 7 hydrogen desorption, reactors for, selective epitaxial growth, 7 silicon thickness maps, substrate cleaning, substrate contamination, 7 surface contamination, of substrate, 7 temperautre and pressure requirements, Ultrathin FD SOI films, 35 Ultrathin Si films, 33 V V P Ge complex, 8 Vacancy impurity complexes in Ge, 8 in Si, 8 Vacancy related defects, in Si, Valence band offset, for strained Si/relaxed SiGe heterojunctions, 10 Vapor phase epitaxy (VPE) systems, VBIC SiGe HBT model parameters, A.4 A.4 Vegard’s law, 2, 3, 10 Volmer Weber herteroexpitaxial growth, 4 Volterra dislocation model, W Wafer emissivity, 21 Work hardening, in SiGe/Si, 9 10 X X ray diffractometry (XRD), 4 7, 14 X ray photoelectron spectroscopy (XPS), 10 X ray reflectometry (XRR), .. .SiGe and Si Strained- Layer Epitaxy for Silicon Heterostructure Devices SiGe and Si Strained- Layer Epitaxy for Silicon Heterostructure Devices Edited by John D Cressler... many nuances 14 SiGe and Si Strained Layer Epitaxy for Silicon Heterostructure Devices associated with using SiGe and Si strained layer epitaxy to practice bandgap engineering in the Si material... Cressler Overview: SiGe and Si Strained- Layer Epitaxy 3-1 John D Cressler Strained SiGe and Si Epitaxy 4-1 Bernd Tillack and Peter Zaumseil Si -SiGe( C) Epitaxy by RTCVD