CRC press measurement and modeling of silicon heterostructure devices dec 2007 ISBN 1420066927 pdf

Measurement and Modeling of Silicon Heterostructure Devices Measurement and Modeling of Silicon Heterostructure Devices Edited by John D Cressler Boca Raton London New York CRC Press is an imprint of the Taylor & Francis Group, an informa business The material was previously published in Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy © Taylor and Francis 2005 CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2008 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S Government works Printed in the United States of America on acid-free paper 10 International Standard Book Number-13: 978-1-4200-6692-0 (Hardcover) This book contains information obtained from authentic and highly regarded sources Reprinted material is quoted with permission, and sources are indicated A wide variety of references are listed Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use Except as permitted under U.S Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers For permission to photocopy or use material electronically from this work, please access www.copyright.com (http:// www.copyright.com/) or contact the Copyright Clearance Center, Inc (CCC) 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400 CCC is a not-for-profit organization that provides licenses and registration for a variety of users For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe Library of Congress Cataloging-in-Publication Data Measurement and modeling of silicon heterostructure devices / editor, John D Cressler p cm Includes bibliographical references and index ISBN 978-1-4200-6692-0 (alk paper) Bipolar transistors Mathematical models Bipolar transistors Heterostructures Integrated circuits Design and construction I Cressler, John D TK7871.96.B55M33 2008 621.3815’2 dc22 Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com 2007030737 For the tireless efforts Of the many dedicated scientists and engineers Who helped create this field and make it a success I tip my hat, and offer sincere thanks from all of us Who have benefitted from your keen insights and imaginings And For Maria: My beautiful wife, best friend, and soul mate for these 25 years For Matthew John, Christina Elizabeth, and Joanna Marie: God’s awesome creations, and our precious gifts May your journey of discovery never end He Whose Heart Has Been Set On The Love Of Learning And True Wisdom And Has Exercised This Part of Himself, That Man Must Without Fail Have Thoughts That Are Immortal And Divine, If He Lay Hold On Truth Plato ồòớùũ ù íữồỉ ọỵúồỉ ụỗớ ữị ụù úụỗớ `êĩỗ êỉặ èĩỗúỗ ặỉ `ỗỉớị ểùòặ, ặỉ íữồỉ `úỗồò êỉặ ụùýụù, ớặũ ụíụùỉùũ ỡỹớù Âớọổặũ ỡùổồò ụù ọòữứũ ĩù ớặ ĩớồỉ úíồỉũ `ĩớặụồũ ặỉ ăồòồũ, ĩớ úụỗổỉữồò úụỗớ `ịồỉặ Pl atvna§ Foreword Progress in a given field of technology is both desired and expected to follow a stable and predictable long term trajectory Semilog plots of technology trends spanning decades in time and orders of magnitude in value abound Perhaps the most famous exemplar of such a technology trajectory is the trend line associated with Moore’s law, where technology density has doubled every 12 to 18 months for several decades One must not, however, be lulled into extrapolating such predictability to other aspects of semiconductor technology, such as device performance, or even to the long term prospects for the continuance of device density scaling itself New physical phenomena assert themselves as one approaches the limits of a physical system, as when device layers approach atomic dimensions, and thus, no extrapolation goes on indefinitely Technology density and performance trends, though individually constant over many years, are the result of an enormously complex interaction between a series of decisions made as to the layout of a given device, the physics behind its operation, manufacturability considerations, and its extensibility into the future This complexity poses a fundamental challenge to the device physics and engineering community, which must delve as far forward into the future as possible to understand when physical law precludes further progress down a given technology path The early identification of such impending technological discontinuities, thus providing time to ameliorate their consequences, is in fact vital to the health of the semiconductor industry Recently disrupted trends in CMOS microprocessor performance, where the ‘‘value’’ of processor operating frequency was suddenly subordinated to that of integration, demonstrate the challenges remaining in accurately assessing the behavior of future technologies However, current challenges faced in scaling deep submicron CMOS technology are far from unique in the history of semiconductors Bipolar junction transistor (BJT) technology, dominant in high end computing applications during the mid 1980s, was being aggressively scaled to provide the requisite performance for future systems By the virtue of bipolar transistors being vertical devices rather than lateral (as CMOS is), the length scale of bipolar transistors is set by the ability to control layer thicknesses rather than lateral dimensions This allowed the definition of critical device dimensions, such as base width, to values far below the limits of optical lithography of the day Although great strides in device performance had been made by 1985, with unity gain cutoff frequencies (fT ) in the range 20 30 GHz seemingly feasible, device scaling was approaching limits at which new physical phenomena became significant Highly scaled silicon BJTs, having base widths below 1000 A˚, demonstrated inordinately high reverse junction leakage This was due to the onset of band to band tunneling between heavily doped emitter and base regions, rendering such devices unreliable This and other observations presaged one of the seminal technology discontinuities of the past decade, silicon germanium (SiGe) heterojunction bipolar transistor (HBT) technology being the direct consequence Begun as a program to develop bipolar technology with performance capabilities well beyond those possible via the continued scaling of conventional Si BJTs, SiGe HBT technology has found a wealth of applications beyond the realm of computing A revolution in bipolar fabrication methodology, moving vii viii Foreword from device definition by implantation to device deposition and definition by epitaxy, accompanied by the exploitation of bandgap tailoring, took silicon based bipolar transistor performance to levels never anticipated It is now common to find SiGe HBTs with performance figures in excess of 300 GHz for both fT and fmax , and circuits operable at frequencies in excess of 100 GHz A key observation is that none of this progress occurred in a vacuum, other than perhaps in the field of materials deposition The creation of a generation of transistor technology having tenfold improved performance would of itself have produced far less ultimate value in the absence of an adequate eco system to enable its effective creation and utilization This text is meant to describe the eco system that developed around SiGe technology as context for the extraordinary achievement its commercial rollout represented Early SiGe materials, of excellent quality in the context of fundamental physical studies, proved near useless in later device endeavors, forcing dramatic improvements in layer control and quality to then enable further development Rapid device progress that followed drove silicon based technology (recall that SiGe technology is still a silicon based derivative) to unanticipated performance levels, demanding the development of new characterization and device modeling techniques As materials work was further proven SiGe applications expanded to leverage newly available structural and chemical control Devices employing ever more sophisticated extensions of SiGe HBT bandgap tailoring have emerged, utilizing band offsets and the tailoring thereof to create SiGe based HEMTs, tunneling devices, mobility enhanced CMOS, optical detectors, and more to come Progress in these diverse areas of device design is timely, as I have already noted the now asymptotic nature of performance gains to be had from continued classical device scaling, leading to a new industry focus on innovation rather than pure scaling Devices now emerging in SiGe are not only to be valued for their performance, but rather their variety of functionality, where, for example, optically active components open up the prospect of the seamless integration of broadband communication functionality at the chip level Access to high performance SiGe technology has spurred a rich diversity of exploratory and com mercial circuit applications, many elaborated in this text Communications applications have been most significantly impacted from a commercial perspective, leveraging the ability of SiGe technologies to produce extremely high performance circuits while using back level, and thus far less costly, fabricators than alternative materials such as InP, GaAs, or in some instances advanced CMOS These achievements did not occur without tremendous effort on the part of many workers in the field, and the chapters in this volume represent examples of such contributions In its transition from scientific curiosity to pervasive technology, SiGe based device work has matured greatly, and I hope you find this text illuminating as to the path that maturation followed Bernard S Meyerson IBM Systems and Technology Group Preface While the idea of cleverly using silicon germanium (SiGe) and silicon (Si) strained layer epitaxy to practice bandgap engineering of semiconductor devices in the highly manufacturable Si material system is an old one, only in the past decade has this concept become a practical reality The final success of creating novel Si heterostructure transistors with performance far superior to their Si only homojunction cousins, while maintaining strict compatibility with the massive economy of scale of conventional Si integrated circuit manufacturing, proved challenging and represents the sustained efforts of literally thousands of physicists, electrical engineers, material scientists, chemists, and technicians across the world In the electronics domain, the fruit of that global effort is SiGe heterojunction bipolar transistor (SiGe HBT) BiCMOS technology, and strained Si/SiGe CMOS technology, both of which are at present in commercial manufacturing worldwide and are rapidly finding a number of important circuit and system applications As with any new integrated circuit technology, the industry is still actively exploring device performance and scaling limits (at present well above 300 GHz in frequency response, and rising), new circuit applications and potential new markets, as well as a host of novel device and structural innovations This commercial success in the electronics arena is also spawning successful forays into the optoelectronics and even nanoelectronics fields The Si heterostructure field is both exciting and dynamic in its scope The implications of the Si heterostructure success story contained in this book are far ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of the twenty first century While several excellent books on specific aspects of the Si heterostructures field currently exist (for example, on SiGe HBTs), this is the first reference book of its kind that ‘‘brings it all together,’’ effectively presenting a comprehensive perspective by providing very broad topical coverage ranging from materials, to fabrication, to devices (HBT, FET, optoelectronic, and nanostructure), to CAD, to circuits, to applica tions Each chapter is written by a leading international expert, ensuring adequate depth of coverage, up to date research results, and a comprehensive list of seminal references A novel aspect of this book is that it also contains ‘‘snap shot’’ views of the industrial ‘‘state of the art,’’ for both devices and circuits, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global Si heterostructure industry This book is intended for a number of different audiences and venues It should prove to be a useful resource as: A hands on reference for practicing engineers and scientists working on various aspects of Si heterostructure integrated circuit technology (both HBT, FET, and optoelectronic), including materials, fabrication, device physics, transistor optimization, measurement, compact modeling and device simulation, circuit design, and applications A hands on research resource for graduate students in electrical and computer engineering, physics, or materials science who require information on cutting edge integrated circuit technologies ix rsu csu rth cth cjei0 vdei zei aljei cjep0 vdep zep aljep ceox cjci0 vdci zci vptci cjcx0 vdcx zcx vptcx ccox fbc cjs0 vds zs vpts t0 dt0h tbvl tef0 gtfe Substrate network Self-heating Base–emitter junction capacitance Base–collector junction capacitance Collector–substrate junction capacitance Diffusion capacitances/transit times — low currents High currents msc itss msf msr tsf (Continued) 40Â10À15 sec 1.0 2.6Â10À12 sec 0.9Â10À12 sec 0.7Â10À12 sec Low current forward transit time at Vcb ¼ V Time constant for base and BC space charge layer width modulation Time constant for modeling carrier jam at low Vce Neutral emitter storage time Exponent for current dependence of neutral emitter storage time 40Â10À15 F 0.6 V 0.3 1Â1010 V 7Â10À15 F 0.7 V 0.3 2.5 V 30Â10À15 F 0.73 V 0.4 100 V 2.5Â10À15 F 0.8 35Â10À15 F 1.0 V 0.32 2.0 5Â10À15 F 1.0 V 0.32 2.2 18Â10À15 F 700 K/W 350 pJ/K 50 V (layout dependent) 3Â10À18 F 2.5Â10À19 A 1 2Â10À12 sec Zero-bias CS depletion capacitance CS built-in voltage CS grading coefficient Punch-through voltage of CS junction Internal zero-bias BC depletion capacitance Internal BC built-in voltage Internal BC grading coefficient Punch-through voltage of internal BC junction External zero-bias BC depletion capacitance External BC built-in voltage External BC grading coefficient Punch-through voltage of external BC junction BC overlap capacitance Partitioning factor for cjcx and ccox over rbx Internal zero-bias BE depletion capacitance Internal BE built-in voltage Internal BE grading coefficient Maximum internal depletion capacitance divided by cjei0 Peripheral zero-bias BE depletion capacitance Peripheral BE built-in voltage Peripheral BE grading coefficient Maximum peripheral depletion capacitance divided by cjep0 Emitter oxide (overlap) capacitance Thermal resistance Thermal capacitance Substrate resistance Substrate capacitance CS diode non-ideality factor Transfer saturation current of substrate transistor Forward non-ideality factor of substrate transfer current Reverse non-ideality factor of substrate transfer current Transit time (forward operation) — substrate Sample SiGe HBT Compact Model Parameters A.4 kf af krbi tnom vgb alb alfav alqav zetaci alvs alces zetarbi zetarbx zetarcx zetare alt0 kt0 Noise parameters Temperature effect parameters Measurement temperature Bandgap voltage Temperature coefficient of current gain Temperature coefficient of favl Temperature coefficient of qavl Temperature coefficient for mobility in epi-collector (i.e., for collector resitance) Relative temperature coefficient of saturation drift velocity Relative temperature coefficient of vces Temperature coefficient for mobility in internal base (i.e., for internal base resistance) Temperature coefficient for mobility in extrinsic base (i.e., for extrinsic base resistance) Temperature coefficient for mobility in extrinsic collector (i.e., for extrinsic collector resistance) Temperature coefficient for emitter resistance First-order temperature coefficient of t0 Second-order temperature coefficient of t0 Flicker noise factor Flicker noise exponent factor Noise factor for internal base resistance Factor for additional delay time of minority charge Factor for additional delay time of transfer current Saturation time constant at high current densities Smoothing factor for current dependence of base and collector transit time Factor for partitioning this into base and collector portion Internal C-E saturation voltage Internal collector resistance at low electric field Voltage separating ohmic (low field) and saturation velocity (high field) regime Collector punch-through voltage Storage time for inverse operation thcs alhc fthc vces rci0 vlim vpt tr alqf alit Parameter Description Name Non-quasistatic effects Group TABLE A.4.1 HICUM (v 2.1) SiGe HBT Model Parameters (Continued) 25 C 1.17 V 6Â10À3 5Â10À5 KÀ1 2Â10À4 KÀ1 1.6 1Â10À3 KÀ1 0.4Â10À3 KÀ1 0.6 0.2 0.2 1Â10À3 KÀ1 1Â10À5 KÀ2 22Â10À6 2.5 0.125 0.45 25Â10À12 sec 0.53 0.6 0.1 V 20 V 0.7 V 15 V 20Â10À12 sec Value A.4 Measurement and Modeling of Silicon Heterostructure Devices Name is ik bf ibf mlf xibi bri ibr vlr xext ver vef wavl vavl sfh re rbc rbv rcc rcv scrcv ihc axi cje vde pe xcje cbeo cjc vdc pc xp Group Forward and reverse currents Early voltage Weak avalanche Resistances and quasisaturation Base–emitter junction capacitance Base–collector junction capacitance TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters Zero–bias collector–base depletion capacitance Collector–base diffusion voltage Colector–base grading coefficient Constant part of cjc Zero-bias emitter–base depletion capacitance Emitter–base diffusion voltage Emitter–base grading coefficient Fraction of the emitter–base depletion capacitance that belongs to the side-wall Emitter–base overlap capacitance Emitter resistance Constant part of the base resistance Zer-bias value of the bias-dependent base resistance Constant part of the collector resistance Resistance of the un-modulated epilayer Space charge resistance of the epilayer Critical current for velocity saturation in the epilayer Smoothness parameter for the onset of quasi-saturation Epilayer thickness used in weak-avalanche model Voltage determining curvature of avalanche current Current spreading factor of avalanche model (when exavl ¼ 1) Reverse Early voltage Forward Early voltage Transistor main saturation current Knee current for high-injection effects in the base Ideal forward current gain Saturation-current of the non-ideal forward base current Non-ideality factor of the non-ideal forward base current Sidewall component of ideal base current Ideal reverse current gain Saturation current of the non-ideal reverse base current Cross-over voltage of the non-ideal reverse base current Partitioning factor for the extrinsic region Parameter Description (Continued) 7Â10À15 F 0.75 V 0.28 1Â10À3 42Â10À15 F 0.9 V 0.23 18Â10À15 F 3.0 V 6V 20 V 17 V 52 V 54 V 3.56Â10À3 A 0.21 2.44Â10À7 M 0.63 V 1.7 4.8 V 65 V 5Â10À18 A 4.5Â10À2 A 95 2Â10À17 A 1.545 3.77 1.7Â10À15 A 1Â10À2 V 0.19 Value Sample SiGe HBT Compact Model Parameters A.4 deg xrec aqbo ae ab aepi aex ac as dvgbf dvgbr vgb vgc vgj dvgte af kf kfn iss iks rth cth HBT parameters Temperature coeffcients 1/f Noise Substrate transistor Self-heating network Diffusion capacitances/transit times Thermal resistance Thermal capacitance Base-substrate saturation current Base-substrate high-injection knee current Exponent of the flicker noise Flicker-noise coefficient of the ideal base current Flicker noise coefficient of the non-ideal base current Temperature coefficient of the zero-bias base charge Temperature coefficient of the resistivity of the emitter Temperature coefficient of the resistivity of the base Temperature coefficient of the resistivity of the epilayer Temperature coefficient of the resistivity of the extrinsic base Temperature coefficient of the resistivity of the buried layer Temperature coefficient for Iss and Iks (for a closed buried layer, as¼ac and for an open buried layer, as¼aepi) Bandgap voltage difference for forward current gain Bandgap voltage difference for reverse current gain Bandgap voltage of the base Bandgap voltage of the collector Bandgap voltage: recombination of the emitter–base junction Bandgap voltage difference of emitter stored charge Bandgap difference over the base Pre-factor of the recombination part of ideal base current Zero-bias collector–substrate depletion capacitance Collector–substrate diffusion voltage Collector–substrate grading coefficient Bandgap voltage of the substrate Non-ideality factor for the emitter stored charge Minimum transit time of stored emitter charge Transit time of stored base charge Transit time of stored epilayer charge Transit time of reverse extrinsic stored base charge Coefficient for the current modulation of the collector–base depletion capacitance Fraction of the collector–base depletion capacitance under the emitter Collector–base overlap capacitance mc xcjc cbco cjs vds ps vgs mtau taue taub tepi taur Parameter Description Name Collector–substrate junction capacitance Group TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters (Continued) 700 K/W 350 pJ/K 2.5Â10À19 A 50 A 2.5 22Â10À6 20Â10À12 0.34 1.22 1.88 8.7Â10À7 0.76 3.75Â10À2 V 4.38Â10À2 V 1.15 V 1.18 V 1.15V 0.236 V 0.03 eV 45Â10À15 F 0.6 V 0.3 1.17 V 0.388 52Â10À15 sec 1.44Â10À12 sec 14.4Â10À12 sec 20Â10À12 sec 0.5 8.7Â10À2 2.5Â10À15 F Value A.4 Measurement and Modeling of Silicon Heterostructure Devices Name is ibei iben ibci ibcn isp ibcip ibcnp ibeip ibenp nf nei nen nr nci ncn nfp ncip ncnp ikf ikr ikp avc1 avc2 rbi rbx rbp re rcx rs rth cth Group Saturation currents and ideality factors Knee currents Avalanche breakdown Series resistances Self-heating TABLE A.4.3 VBIC SiGe HBT Model Parameters Thermal resistance Thermal capacitance Intrinsic base resistance Extrinsic base resistance Parasitic base resistance Emitter resistance Extrinsic collector resistance Substrate resistance Base–collector weak avalanche parameter Base–collector weak avalanche parameter Forward knee current Reverse knee current Parasitic knee current Transport saturation current (collector) Ideal base–emitter saturation current Nonideal base–emitter saturation current Ideal base–collector saturation current Nonideal base–collector saturation current Parasitic transport saturation current Ideal parasitic base–collector saturation current Nonideal parasitic base–collector saturation current Ideal parasitic base–emitter saturation current Nonideal parasitic base–emitter saturation current Forward emission coefficient Ideal base–emitter emission coefficient Nonideal base–emitter emission coefficient Reverse emission coefficient Ideal base–collector emission coefficient Nonideal base–collector emission coefficient Parasitic forwad emission coefficent Ideal parasitic base–collector emission coefficient Nonideal parasitic base–collector emission coefficient Parameter Description (Continued) 700 K/W 350 pJ/W 20 V 6V 1V 3V 23 V 50 V 19.2 23.6 V 4.5Â10À2 A 4.8Â10À3 A 10 A 1Â10À40 A 2.52Â10À18 A 1Â10À28 A 1.0003 1.026 2.5 1.02 1.00 1.00 1.00 4.85Â10À18 A 7Â10À20 A 1Â10À15 A 1.5Â10À18 A 1Â10À34 A 3Â10À19 A Value Sample SiGe HBT Compact Model Parameters A.4 Name rci vo gamm hrcf qco vef ver cje me pe cbeo fc aje cjc mc pc cbco cjep ajc cjcp ms ps ccso ajs tf itf vtf qtf td ea eaie eaic eais eanc Group Quasi-saturation parameters Early effect parameters Base–emitter junction capacitance Base–collector junction capacitance Collector–substrate junction capacitance Transit times and their bias dependence Temperature effect parameters TABLE A.4.3 VBIC SiGe HBT Model Parameters (Continued) Activation energy Activation energy Activation energy Activation energy Activation energy for is for ibei for ibci and ibeip for ibcip for ibcn/ibenp Forward transit time Coefficient of tf dependence of ic Coefficient of tf dependence of Vbc Variation of tf with base-width modulation Forward excess-phase delay time Substrate–collector zero bias capacitance Substrate–collector grading coefficient Substrate–collector built-in potential Fixed collector–substrate capacitance Substrate–collector capacitance switching parameter Base–collector intrinsic zero-bias capacitance Base–collector grading coefficient Base–collector built-in potential Extrinsic base–collector overlap capacitance Base–collector extrinsic zero bias capacitance Base–collector capacitance switching parameter Base–emitter zero-bias capacitance Base–emitter grading coefficient Base–emitter built-in potential Extrinsic base–emitter overlap capacitance Forward bias depletion capacitance limit Base–emitter capacitance switching parameter Forward Early voltage Reverse Early voltage Intrinsic collector resistance Epi drift saturation voltage Epi doping parameter High-current RC factor Epi-charge parameter Parameter Description 1.17 V 1.17 V 1.17 V 1.17 V 1.17 V 2Â10À12 sec 0.32 23.7 0.7Â10À12 sec 40Â10À15 F 0.3 0.6 V 3eÀ18 F À0.9 7Â10À15 F 0.3 0.7 V 2.5Â10À15 F 30Â10À15 F À0.1 42 fF 1.0 0.3 V 18Â10À15 F 0.93 À0.1 65 V 5.5 V 40 V 1Â10À10 V 5Â10À13 V 1Â10À13 1.4Â10À15 Value A.4 Measurement and Modeling of Silicon Heterostructure Devices eane eans xii xin xis xre xrb xrc xrs xvo tavc Activation energy for iben Activation energy for ibcnp Temperature coefficient for ibei, ibci, ibeip, and ibcip Temperature coefficient for iben, ibcn, ibenp, and ibcnp Temperature coefficient for is Temperature coefficient for re Temperature coefficient for rbi Temperature coefficient for rc Temperature coefficient for rs Temperature coefficient for vo Temperature coefficient for avc2 1.17 V 1.17 V 2.0 2.0 1.9 0 0 250Â10À6 V Sample SiGe HBT Compact Model Parameters A.4 A.4 10 Measurement and Modeling of Silicon Heterostructure Devices References HICUM bipolar transistor model: http://www.iee.et.tu dresden.de/iee/eb/comp mod.html Mextram bipolar transistor model: http://www.semiconductors.phillips.com/acrobat/other/phillips models/NLUR2000811 7.pdf VBIC bipolar transistor model: http://www.designers guide.org/VBIC/references.html Index A AC device measurement techniques, AC extraction and calibration, AC measurement techniques, 4 10 calibration, instrumentation, 4 S parameter, 4 Activation energy, boron, 5 Atmospheric pressure CVD (AP CVD), Avalanche current and curvature voltage, 10 B Bandgap engineering, 4, 2 Base transit time, A.2 BC depletion capacitance, BC leakage diode, crossover voltage of, BE junction, base current, Bipolar complementary metal oxide semiconductor (BiCMOS) technology, Bipolar junction transistor (BJT), 4, current densities, DC and AC characteristics, geometry scaling equations for, 10 mextram equivalent circuit of, 7 structures, technologies, C Carrier mobilities, electrons and holes, Chemical mechanical polishing (CMP), 8 Chemical vapor deposition (CVD), Chip design assembly, 10 chip finishing, 11 electrostatic discharge (ESD), 10 phase shift mask (PSM), 11 Chip interconnects cross section dimensions of, 10 electrical interconnects, 10 Circuit parasitic noise effects, 9 10 Code division multiple access (CDMA), Collector resistance, lumped elements, Collector substrate region, distributed RC network, 6 Communication circuit design Communication circuit design, noise prediction, Computer aided design (CAD) tools, chemical mechanical polishing (CMP), circuit simulators and layout versus schematic (LVS) tools, design rule checking (DRC), electrical rule check (ERC), inductor layout in, physical layout, programmable cells and programmable devices, Constant base resistance, ohmic part of base region, 7 Conventional emitter doping (CED) transistors, A.3 Crossover voltage, VLR, Current modulation coefficient, MC, 12 D De embedding techniques improvements in, 11 11 noise, 11 11 open short, 11 OPEN test structure, 11 S parameters of, 8, 11 and structure, 10 on wafer, 10, 10 6, 11 Depletion capacitance parameters, 11 12 Depletion charge, Design for manufacturing (DFM) approach, Design rule checking (DRC), process layers, Device under test (DUT) four port error network, four port I V relation of, 11 12 frequency dependent behavior, 4 layout of, 11 network parameters, 8, 10 port y parameters, 11 reference plane, S parameters of, 3, 4 terminal characteristics of, test structure, de embedding process S parameters of, 11 7, 11 10 Y parameter of, 11 11 transmission lines, 4 two port networks, I1 I2 Measurement and Modeling of Silicon Heterostructure Devices Differential amplifier circuit, Diffusion charges, epilayer transit time TEPI, 13 Diode partition factor, XIBI, Direct conversion receiver, substrate coupling, Distributed and non quasi static charges, 14 Drift diffusion equation, one dimensional, Gummel Poon model integral charge, 2, 10 integral charge control relationship, 2, 4, 13 knee current parameter of, transfer current, H E EB recombination current prefactor, Electric field distribution, 10 Electron quasi Fermi potentials, 4, 3, 4, Electrostatic discharge (ESD), 10 Emitter diffusion charge coefficient, 13 out diffusion, 5 perimeter junction with BC junction, 6 transit time bandgap voltage difference, 13, 15 Emitter base interface, Emitter base spacer process, transient frequency of, 10 Emitter coupled logic (ECL) ring oscillator, Epilayer carrier concentrations distribution, current, 7 diffusion charge, 13 effective width, WAVL, 10 electron current density, permittivity of, 7 quasi Fermi potential, resistance, space charge resistance, 7 transfer current, 12 External base emitter region, 6 Extrinsic quasi neutral regions, 10 F Four port error network and DUT network(s), Four port method noise de embedding, 11 11 S parameter, 11 9, 11 10 G Ge content, valence and conduction bands, effective mass parameters, A.1 energy band structure, A.1 properties of, A.1 related parameter, 15 Generalized ICCR (GICCR), A.3 A.3 6, A.3 13 Geometry partitioning factors, depletion capacitances, 12 Global positioning systems (GPS), Global system for mobile communications (GSM), Ground signal ground (GSG) microwave probes, Gummel number, HBT breakdown simulation models, HBT devices characteristics geometry scaling equations for, 10 H parameters, forward Gummel curves, DC calibration, Heterojunction transistors, charge control relation, A.3 A.3 12 HICUM technology, base resistance, charge storage, collector current, frequency dependent current, 6 geometry scaling effects, high frequency transistor behavior, 11 internal transistor, material parameters, small signal model (SSM), 11 substrate transistor parameter, weak avalanche model, 6 HICUM (v 2.1) SiGe HBT model parameters, A.4 A.4 High electron mobility transistors (HEMTs), High injection parameters, extraction, 17 High injection therm gBH, High level design language (HDL), 10 High speed SiGe HBTs, Homojunction transistors, charge control relation, A.3 A.3 H parameters, 4 I Impedance mismatch, 4 Integral charge control relation (ICCR), A.3 hetereojunction transistors, A.3 A.3 12 homojunction transistors, A.3 A.3 Integrated circuit design analog and digital PRML, design simulation, phases of, process design kit (PDK), Interconnect extraction modeling, Interconnect parasitics inductance, modeling versus extracting, 9 Internal BE and BC depletion charges, 6 Intrinsic device y parameters, 11 Intrinsic transistor region, Isolation capacitance, I3 Index K Knee current (IK), Kroemer’s approach, A.2 L LEFT test structure, de embedding process S parameters of, 11 Y parameter, 11 11 Limited reaction processing CVD (LRP CVD), 22 24 Linear time invariant (LTI) system, Loop based inductance, Loss less transmission line, 3, 4 Low emitter concentration (LEC) transistors, A.3 Low Injection Parameters extraction, 17 Low noise amplifier (LNA), 8, 10 7, 10 10 circuit of, 10 10 microstrip lines of, 10 11 Low temperature epitaxial process, emitter polysilicon, Low temperature Si epi growth techniques, LRM/LRRM (Line Reflect Match, Line Reflect Reflect Match), calibration, M Metal interconnects design, 10 inductance estimation of, Metal stack, parasitic capacitance, 10 MEXTRAM 504 model parameters, A.4 A.4 Mextram model, SiGe HBTs avalanche current Iavl, 10 base diffusion charge, 12 BE and BC depletion charges, depletion capacitances, 11 equivalent circuit, high injection therm gBH, nodal biases, parameters, substrate current, 10 transfer current, Microstrip line interconnect RLCZ parameters, 10 S parameter, 10 10 Microstrip transmission line, constant capacitance, 10 Model parameters, SiGe HBTs carrier mobility temperature, 15 methodology for, 10 physics based model, 11 process specific parameters, 13 test structures, 11 15 VER and VEF, Moll Ross collector current density relation, A.2 Moll Ross relation assumptions for, A.2 generalized, A.2 Moore’s law, MOSFET layout cell representations for, 8 design practices, 8 parameters, N Network parameters, linear network, 4 4, 10 Noise current model correlation matrix, 12 equivalent circuit of, 11 11 four port parasitics, 12 Nonphysical parameters, passive elements, 4, N port networks, O One port S parameters, On wafer parasitics equivalent circuits of, 11 3, 11 OPEN test structure, 11 operating frequency, 11 two port networks, 11 Open and short circuit connections, passive elements of, Open test structure, de embedding process equivalent circuit of, 11 S parameters of, 11 7, 11 10 Y parameter, 11 2, 11 4, 11 11 Optical proximity correction (OPC), 11 P Parasitic extraction (PEX), 10 Parasitic inductance effects, Parasitic RLC tools, Parasitics model four port, 11 3, 11 I V characteristic of, 11 y parameters, 11 Partial equivalent electrical circuit (PEEC), Passive devices, parasitic effects, Pinch in effect, 6 PNP transistor saturation current, ISS, 10 Poisson Equation, 7 Polysilicon emitter, Power amplifier, 10 Predictive model extraction, TCAD process genetic algorithm (GA) model, 10 parameter optimization, 11 I4 Measurement and Modeling of Silicon Heterostructure Devices Q Quasi neutral base (QNB), SiGe HBTs, 1, BE space charge region, 7 boundaries, diffusion charges, 12 doping and bandgap distribution, electron current density Jn, Ge profile, Gummel number, modulation rate, non quasi static effects, 14 recombination in, transfer saturation current, width modulation, Quasi neutral emitter (QNE) diffusion charges, 12, 13 hole injection, 7 R Recombination currents, 7 Reference temperature, TREF, 15 16 Reverse base transit time, TAUR, 14 Reverse Gummel plot, 18 RF AMS IC design flow, RF custom libraries, RF MOSFET, model subcircuit, layout representation of, RIGHT test structure, de embedding process frequency behavior of, 10 S parameters of, 11 Y parameter, 11 11 S Saturation current, IBR, Semi automated S parameter measurement system, Shallow trench isolation, Shockley boundary condition, generelized, A.2 2, A.2 Shockley Read Hall (SRH) recombination, Short Open Load Reciprocal reciprocal standard, Thru standard, Short Open Load Thru, SHORT test structure, de embedding process S parameters of, 11 7, 11 10 Y parameter, 11 11 Si effective mass parameters, A.1 energy band structure, A.1 properties of, A.1 Si based high electron mobility transistors (HEMTs), 10 light emitters, 10 optoelectronic superchip, 10 transistor(s), 2, SiGe alloys, 4, device simulation AC extraction and calibration, DC calibration, RF simulations, epitaxial layer boron diffusion, diffusion coefficients, simulated B profiles, 5 fabrication facilities, ICs, applications, integrated circuits, process simulation, 5 wireless transceiver, SiGe BiCMOS technology, noise resistance versus frequency, 12 transit frequency fT versus collector current, 12 SiGe:C channel pMOSFET, HBT technology, silicidation of, 11 SiGe HBT BiCMOS technology, generations, 5, 10 SiGe HBTs current density, 11 10 cutoff frequency versus collector current, 18 19 development of, epitaxial base in, graded Ge base profile, A.2 high power, model parameters VER and VEF, performance of, self aligned emitter base structures, simulated fT and fmax characteristics, S parameter characteristics, 9, 11 static current gain versus collector current of, 17 technology generations, performance of, 10 temperature scaling parameters, 15 thermal phenomena, 14 16 transfer current, SiGe Si strained layer epitaxy, development, 2 SiGe strained Si FETs , development of, Silicon Germanium RF designs, Silicon heterostructures characterization of, 1, devices, output characteristics, 18 S parameters for, 10 Silicon process technology, SIMS profiles, 5 Single base transistor, Si SiGe bipolar transistor, Si strained layer epitaxy, SOLR, See Short Open Load Reciprocal I5 Index SOLT, See Short Open Load Thru Space charge layer, regions, current injection, S parameter measurement, device under test (DUT) calibration, C V measurement, 10 instrumentation, 4 linear network, load conditions in, 4 power level selection, 10 two port network, SPICE Gummel Poon model, 13 STI, See Shallow trench isolation Strained Si CMOS, 2, 6, 10, 11 Strained Si fabrication facilities, Strained Si nMOSFET, Substrate coupling, floor planning, 10 current, 10 11 isolation, chip floor plans, knee current, IKS, 10 Substrate noise components, DC and RF, 9 coupling, 9 guard ring structures, 9 injection, 9 modeling, 9 Switching functions, loading capacitance, 9 Synchronous optical network (SONET), network, 10 on chip interconnects, 10 skin depth, 10 S parameters, 10 structures coplanar waveguides, 10 1, 10 microstrip lines, 10 1, 10 technology, 10 TRL (Thru Reflect Line), Two port network, H parameters, U Ultrahigh vacuum chemical vapor deposition (UHV/CVD), V VBIC model, circuit design, 11 VBIC SiGe HBT model parameters, A.4 A.4 Vector network analyzer (VNA) four port error network, noise floor, 10 one port S parameters, S parameter, 4 voltage wave measurement, Voltage controlled oscillators (VCOs), Voltage wave, 3, 4, 5, W T Technology computer aided design (TCAD) numerical process and device simulation, peak device optimizations performance, 10 simulated test structures, Temperature scaling parameter, 16 TRADICA program, operation principle of, 11 Transfer current, 7 Transient ICCR (TICC), A.3 Transmission line characteristic impedance of, 3, 4 interconnect, Y parameters, 10 3, 10 measurements, 10 Wafer devices, Weak avalanche current, 10 effects, 7 Y Y elements modeling, 10 Y parameters, Z Z elements, modeling, 10 10 .. .Measurement and Modeling of Silicon Heterostructure Devices Measurement and Modeling of Silicon Heterostructure Devices Edited by John D Cressler Boca Raton London New York CRC Press is... examples of cool new devices that 16 Measurement and Modeling of Silicon Heterostructure Devices never made it past the pages of the IEDM digest! The ultimate test, then, is one of stamina And sweat... http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com 20070 30737 For the tireless efforts Of the many dedicated scientists and engineers Who helped create this field and make