MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES • • • • • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 220 µA at MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than µs 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations – Internal Frequencies up to 16 MHz With Four Calibrated Frequencies – Internal Very-Low-Power Low-Frequency (LF) Oscillator – 32-kHz Crystal – External Digital Clock Source One 16-Bit Timer_A With Three Capture/Compare Registers Up to 16 Touch-Sense Enabled I/O Pins • • • • • • • • • Universal Serial Interface (USI) Supporting SPI and I2C 10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan (MSP430G2x52 Only) On-Chip Comparator for Analog Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse On-Chip Emulation Logic With Spy-Bi-Wire Interface Family Members are Summarized in Table Package Options – TSSOP: 14 Pin, 20 Pin – PDIP: 20 Pin – QFN: 16 Pin For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide (SLAU144) DESCRIPTION The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than µs The MSP430G2x52 and MSP430G2x12 series of microcontrollers are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, and up to 16 I/O touch sense enabled pins and built-in communication capability using the universal serial communication interface and have a versatile analog comparator The MSP430G2x52 series have a 10-bit A/D converter For configuration details see Table Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright © 2010–2011, Texas Instruments Incorporated MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Table Available Options (1) Device EEM Flash (KB) RAM (B) Timer_A Comp_A Channel ADC10 Channel USI Clock MSP430G2452IN20 MSP430G2452IPW20 MSP430G2452IRSA16 256 1x TA3 8 LF, DCO, VLO I/O Package Type (2) 16 20-PDIP 16 20-TSSOP 10 16-QFN MSP430G2452IPW14 10 14-TSSOP MSP430G2352IN20 16 20-PDIP MSP430G2352IPW20 16 20-TSSOP 10 16-QFN MSP430G2352IPW14 10 14-TSSOP MSP430G2252IN20 16 20-PDIP MSP430G2252IPW20 16 20-TSSOP 10 16-QFN MSP430G2252IPW14 10 14-TSSOP MSP430G2152IN20 16 20-PDIP MSP430G2152IPW20 16 20-TSSOP MSP430G2352IRSA16 MSP430G2252IRSA16 MSP430G2152IRSA16 1 256 256 128 1x TA3 1x TA3 1x TA3 8 8 8 1 LF, DCO, VLO LF, DCO, VLO LF, DCO, VLO 10 16-QFN MSP430G2152IPW14 10 14-TSSOP MSP430G2412IN20 16 20-PDIP 16 20-TSSOP MSP430G2412IPW20 MSP430G2412IRSA16 256 1x TA3 - LF, DCO, VLO 10 16-QFN MSP430G2412IPW14 10 14-TSSOP MSP430G2312IN20 16 20-PDIP 16 20-TSSOP MSP430G2312IPW20 MSP430G2312IRSA16 256 1x TA3 - LF, DCO, VLO 10 16-QFN MSP430G2312IPW14 10 14-TSSOP MSP430G2212IN20 16 20-PDIP MSP430G2212IPW20 16 20-TSSOP 10 16-QFN MSP430G2212IPW14 10 14-TSSOP MSP430G2112IN20 16 20-PDIP MSP430G2112IPW20 16 20-TSSOP 10 16-QFN 10 14-TSSOP MSP430G2212IRSA16 MSP430G2112IRSA16 1 MSP430G2112IPW14 (1) (2) 256 128 1x TA3 1x TA3 8 - - 1 LF, DCO, VLO LF, DCO, VLO For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com Package drawings, thermal data, and symbolization are available at www.ti.com/packaging Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Device Pinout PW PACKAGE (TOP VIEW) DVCC P1.0/TA0CLK/ACLK/A0/CA0 P1.1/TA0.0/A1/CA1 P1.2/TA0.1/A2/CA2 P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA3 P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/CA4/TCK P1.5/TA0.0/SCLK/A5/CA5/TMS 14 13 12 11 10 DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDI P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLK NOTE: ADC10 pin functions are available only on MSP430G2x52 NOTE: The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = DVCC AVCC DVSS AVSS RSA PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.4/SMCLK/A4/VREF+/VEREF+/CA4/TCK P1.5/TA0.0/SCLK/A5/CA5/TMS P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLK P1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDI P1.0/TA0CLK/ACLK/A0/CA0 P1.1/TA0.0/A1/CA1 P1.2/TA0.1/A2/CA2 P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA3 NOTE: ADC10 pin functions are available only on MSP430G2x52 NOTE: The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = N OR PW PACKAGE (TOP VIEW) DVCC P1.0/TA0CLK/ACLK/A0/CA0 P1.1/TA0.0/A1/CA1 P1.2/TA0.1/A2/CA2 P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/CA4/TCK P1.5/TA0.0/SCLK/A5/CA5/TMS P2.0 P2.1 P2.2 10 20 19 18 17 16 15 14 13 12 11 DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDI P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLK P2.5 P2.4 P2.3 NOTE: ADC10 pin functions are available only on MSP430G2x52 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Functional Block Diagram, MSP430G2x52 XIN XOUT DVCC DVSS P2.x P1.x up to 8 ACLK Clock System Flash RAM ADC Port P1 Port P2 8KB 4KB 2KB 1KB 256B 256B 256B 128B 10-Bit Ch Autoscan ch DMA I/O Interrupt capability pullup/down resistors up to I/O Interrupt capability pullup/down resistors Comp_A+ Watchdog WDT+ Timer0_A3 SMCLK MCLK 16MHz CPU MAB MDB incl 16 Registers Emulation 2BP USI Brownout Protection JTAG Interface Channels 15-Bit CC Registers Spy-Bi Wire Universal Serial Interface SPI, I2C RST/NMI NOTE: Port P2 Two pins are available on the 14/16-pin package options Eight pins are available on the 20-pin package options Functional Block Diagram, MSP430G2x12 XIN XOUT DVCC DVSS P1.x P2.x up to 8 ACLK Clock System Flash SMCLK 8KB 4KB 2KB 1KB MCLK 16MHz CPU incl 16 Registers 256B Port P2 I/O Interrupt capability pullup/down resistors up to I/O Interrupt capability pullup/down resistors MAB MDB Emulation 2BP JTAG Interface RAM Port P1 USI Brownout Protection Spy-Bi Wire Comp_A+ Channels Watchdog WDT+ 15-Bit Timer0_A3 CC Registers Universal Serial Interface SPI, I2C RST/NMI NOTE: Port P2 Two pins are available on the 14/16-pin package options Eight pins are available on the 20-pin package options Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Table Terminal Functions TERMINAL NO NAME 14 PW 16 RSA I/O DESCRIPTION 20 N, PW P1.0/ General-purpose digital I/O pin TA0CLK/ Timer0_A, clock signal TACLK input ACLK/ 2 I/O ACLK signal output A0/ ADC10 analog input A0 (1) CA0 Comparator_A+, CA0 input P1.1/ General-purpose digital I/O pin TA0.0/ A1/ 3 I/O Timer0_A, capture: CCI0A input, compare: Out0 output ADC10 analog input A1 (1) CA1 Comparator_A+, CA1 input P1.2/ General-purpose digital I/O pin TA0.1/ A2/ 4 I/O Timer0_A, capture: CCI1A input, compare: Out1 output ADC10 analog input A2 (1) CA2 Comparator_A+, CA2 input P1.3/ General-purpose digital I/O pin ADC10CLK/ ADC10, conversion clock output (1) CAOUT/ A3/ 5 I/O Comparator_A+, output ADC10 analog input A3 (1) VREF-/VEREF/ ADC10 negative reference voltage (1) CA3 Comparator_A+, CA3 input P1.4/ General-purpose digital I/O pin SMCLK/ SMCLK signal output TA0.2/ Timer0_A, capture: CCI2A input, compare: Out2 output A4/ 6 I/O ADC10 analog input A4 (1) VREF+/VEREF+/ ADC10 positive reference voltage (1) CA4/ Comparator_A+, CA4 input TCK JTAG test clock, input terminal for device programming and test P1.5/ General-purpose digital I/O pin TA0.0/ Timer0_A, compare: Out0 output SCLK/ A5/ 7 I/O USI: clk input in I2C mode; clk in/output in SPI mode ADC10 analog input A5 (1) CA5/ Comparator_A+, CA5 input TMS JTAG test mode select, input terminal for device programming and test P1.6/ General-purpose digital I/O pin TA0.1/ Timer0_A, compare: Out1 output SDO/ USI: Data output in SPI mode SCL/ 14 I/O USI: I2C clock in I2C mode A6/ ADC10 analog input A6 (1) CA6/ Comparator_A+, CA6 input TDI/TCLK JTAG test data input or test clock input during programming and test (1) Available only on MSP430G2x52 devices Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Table Terminal Functions (continued) TERMINAL NO NAME 14 PW 16 RSA I/O DESCRIPTION 20 N, PW P1.7/ General-purpose digital I/O pin CAOUT/ Comparator_A+, output SDI/ USI: Data input in SPI mode SDA/ 15 I/O USI: I2C data in I2C mode A7/ ADC10 analog input A7 (1) CA7/ Comparator_A+, CA7 input TDO/TDI (2) JTAG test data output terminal or test data input during programming and test P2.0 - - I/O General-purpose digital I/O pin P2.1 - P2.2 - - I/O General-purpose digital I/O pin - 10 I/O P2.3 General-purpose digital I/O pin - - 11 I/O General-purpose digital I/O pin P2.4 - - 12 I/O General-purpose digital I/O pin P2.5 - - 13 I/O General-purpose digital I/O pin XIN/ Input terminal of crystal oscillator P2.6/ 13 12 19 I/O TA0.1 General-purpose digital I/O pin Timer0_A, compare: Out1 output XOUT/ P2.7 12 11 18 I/O 10 16 I RST/ Output terminal of crystal oscillator (3) General-purpose digital I/O pin Reset NMI/ SBWTDIO Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test TEST/ Selects test mode for JTAG pins on port The device protection fuse is connected to TEST 11 10 17 I 16 NA Supply voltage AVCC - 15 - NA Supply voltage DVSS 14 14 20 NA Ground reference AVSS - 13 - NA Ground reference NC - - - NA Not connected QFN Pad - Pad - NA QFN package pad connection to VSS recommended SBWTCK DVCC (2) (3) Spy-Bi-Wire test clock input during programming and test TDO or TDI is selected via JTAG instruction If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared This is due to the oscillator output driver connection to this pad after reset Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register The CPU is integrated with 16 registers that provide reduced instruction execution time The register-to-register operation execution time is one cycle of the CPU clock Constant Generator Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively The remaining registers are general-purpose registers Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range Each instruction can operate on word and byte data Instruction Set The instruction set consists of 51 instructions with three formats and seven address modes Each instruction can operate on word and byte data Table shows examples of the three types of instruction formats; Table shows the address modes CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table Instruction Word Formats FORMAT EXAMPLE OPERATION Dual operands, source-destination ADD R4,R5 R4 + R5 –-> R5 Single operands, destination only CALL R8 PC –>(TOS), R8–> PC JNE Jump-on-equal bit = Relative jump, un/conditional Table Address Mode Descriptions (1) S D SYNTAX EXAMPLE OPERATION Register ADDRESS MODE ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 – –> R11 Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) – –> M(6+R6) Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) – –> M(TONI) Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) – –> M(TCDAT) Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) – –> M(Tab+R6) Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 M(R10) – –> R11 R10 + 2– –> R10 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 – –> M(TONI) (1) S = source, D = destination Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active • Low-power mode (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled • Low-power mode (LPM1) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – DCO's dc generator is disabled if DCO not used in active mode • Low-power mode (LPM2) – CPU is disabled – MCLK and SMCLK are disabled – DCO's dc generator remains enabled – ACLK remains active • Low-power mode (LPM3) – CPU is disabled – MCLK and SMCLK are disabled – DCO's dc generator is disabled – ACLK remains active • Low-power mode (LPM4) – CPU is disabled – ACLK is disabled – MCLK and SMCLK are disabled – DCO's dc generator is disabled – Crystal oscillator is stopped Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the CPU goes into LPM4 immediately after power-up Table Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG Power-Up External Reset Watchdog Timer+ Flash key violation PC out-of-range (1) PORIFG RSTIFG WDTIFG KEYV (2) NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (2) (3) PRIORITY Reset 0FFFEh 31, highest (non)-maskable (non)-maskable (non)-maskable 0FFFCh 30 0FFFAh 29 0FFF8h 28 CAIFG (4) maskable 0FFF6h 27 Watchdog Timer+ WDTIFG maskable 0FFF4h 26 maskable 0FFF2h 25 maskable 0FFF0h 24 0FFEEh 23 0FFECh 22 Timer0_A3 ADC10 TACCR0 CCIFG (4) TACCR2 TACCR1 CCIFG TAIFG (2) (4) (5) ADC10IFG (4) (5) maskable 0FFEAh 21 USI USIIFG, USISTTIFG (2) (4) maskable 0FFE8h 20 I/O Port P2 (up to eight flags) P2IFG.0 to P2IFG.7 (2) (4) maskable 0FFE6h 19 I/O Port P1 (up to eight flags) (2) (4) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 0FFDEh to 0FFC0h 15 to 0, lowest See (2) (3) (4) (5) (6) WORD ADDRESS Comparator_A+ Timer0_A3 (1) SYSTEM INTERRUPT P1IFG.0 to P1IFG.7 (6) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges Multiple source flags (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot Interrupt flags are located in the module MSP430G2x52 only The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Special Function Registers (SFRs) Most interrupt and module enable bits are collected into the lowest address space Special function register bits not allocated to a functional purpose are not physically present in the device Simple software access is provided with this arrangement Legend rw: rw-0,1: rw-(0,1): Bit can be read and written Bit can be read and written It is reset or set by PUC Bit can be read and written It is reset or set by POR SFR bit is not present in device Table Interrupt Enable Register and Address 00h WDTIE OFIE NMIIE ACCVIE Address ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 Watchdog Timer interrupt enable Inactive if watchdog mode is selected Active if Watchdog Timer is configured in interval timer mode Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable 01h Table Interrupt Flag Register and Address 02h WDTIFG OFIFG PORIFG RSTIFG NMIIFG Address NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) Set on watchdog timer overflow (in watchdog mode) or security key violation Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode Flag set on oscillator fault Power-On Reset interrupt flag Set on VCC power-up External reset interrupt flag Set on a reset condition at RST/NMI pin in reset mode Reset on VCC power-up Set via RST/NMI pin 03h 10 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger XOUT/P2.7 LF off PxSEL.6 & PxSEL.7 PxSEL2.6 | PxSEL.7 BCSCTL3.LFXT1Sx = 11 LFXT1CLK PxSEL.y PxDIR.y Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 1 PxSEL2.y PxSEL.y PxOUT.y From Module DVSS DVCC 1 XIN/P2.6/TA0.1 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y EN Q Set PxIRQ.y PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select Table 19 Port P2 (P2.6) Pin Functions PIN NAME (P2.x) CONTROL BITS / SIGNALS (1) x FUNCTION XIN/ XIN P2.6/ P2.x (I/O) P2DIR.x P2SEL.6 P2SEL.7 P2SEL2.6 P2SEL2.7 X 1 0 I: 0; O: X 0 TA0.1/ Timer0_A3.TA1 1 0 Pin Osc Capacitive sensing X X X (1) 44 X = don't care Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger XIN LF off PxSEL.6 & PxSEL.7 PxSEL2.6 | PxSEL.7 BCSCTL3.LFXT1Sx = 11 LFXT1CLK from P2.6 PxSEL.y PxDIR.y Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 1 PxSEL2.y PxSEL.y PxOUT.y From Module DVSS DVCC 1 XOUT/P2.7 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y Q PxIFG.y EN Set Interrupt Edge Select PxSEL.y PxIES.y Table 20 Port P2 (P2.7) Pin Functions PIN NAME (P2.x) CONTROL BITS / SIGNALS (1) x XOUT/ P2.7/ XOUT Pin Osc (1) FUNCTION P2.x (I/O) Capacitive sensing P2DIR.x P2SEL.6 P2SEL.7 P2SEL2.6 P2SEL2.7 X 1 0 I: 0; O: X 0 X X X X = don't care Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 45 MSP430G2x52 MSP430G2x12 SLAS722B – DECEMBER 2010 – REVISED MARCH 2011 www.ti.com REVISION HISTORY REVISION SLAS722 46 DESCRIPTION Initial release SLAS722A Page 1, Changed Internal Frequencies up to 16 MHz With One Calibrated Frequency to Internal Frequencies up to 16 MHz With Four Calibrated Frequencies SLAS722B Added note concerning pulldown resistor to PW14 and RSA16 pinout drawings Added "N20, PW20" to Input Pin Number and Output Pin Number columns in Table 11 Corrected pin numbers for P1.0 to P1.3 for PW14 package in Table Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430G2112IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2112IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2112IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2112IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2112IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2112IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2112IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2152IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2152IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2152IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2152IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2152IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2152IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2152IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2212IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2212IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2212IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2212IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 26-Mar-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430G2212IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2212IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2212IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2252IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2252IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2252IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2252IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2252IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2252IRSA16R ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2252IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2312IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2312IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2312IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2312IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2312IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2312IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2312IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2352IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2352IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 26-Mar-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430G2352IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2352IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2352IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2352IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2352IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2412IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2412IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2412IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2412IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2412IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2412IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2412IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2452IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2452IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2452IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2452IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2452IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2452IRSA16 PREVIEW QFN RSA 16 MSP430G2452IRSA16R ACTIVE QFN RSA 16 TBD 3000 Green (RoHS & no Sb/Br) Addendum-Page Call TI Samples (Requires Login) Call TI CU NIPDAU Level-2-260C-1 YEAR PACKAGE OPTION ADDENDUM www.ti.com Orderable Device MSP430G2452IRSA16T 26-Mar-2011 Status (1) ACTIVE Package Type Package Drawing QFN RSA Pins 16 Package Qty 250 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect NRND: Not recommended for new designs Device is in production to support existing customers, but TI does not recommend using this part in a new design PREVIEW: Device has been announced but is not in production Samples may or may not be available OBSOLETE: TI has discontinued the production of the device (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details TBD: The Pb-Free/Green conversion plan has not been defined Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe The component is otherwise considered Pb-Free (RoHS compatible) as defined above Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis Addendum-Page PACKAGE MATERIALS INFORMATION www.ti.com 25-Mar-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430G2452IRSA16R Package Package Pins Type Drawing QFN RSA 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 4.25 B0 (mm) K0 (mm) P1 (mm) 4.25 1.15 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Mar-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430G2452IRSA16R QFN RSA 16 3000 346.0 346.0 29.0 Pack Materials-Page IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IF and ZigBee® Solutions www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated ... Channel ADC10 Channel USI Clock MSP430G2452IN20 MSP430G2452IPW20 MSP430G2452IRSA16 256 1x TA3 8 LF, DCO, VLO I/O Package Type (2) 16 20-PDIP 16 20-TSSOP 10 16-QFN MSP430G2452IPW14 10 14-TSSOP MSP430G2352IN20... Organization MSP430G2112 MSP430G2152 MSP430G2212 MSP430G2252 MSP430G2312 MSP430G2352 MSP430G2412 MSP430G2452 Size 1kB 2kB 4kB 8kB Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0