;******************************************************************************* ; MSP430F20x Demo - WDT+ Failsafe Clock, 32kHz ACLK ; ; Description; Allow WDT+ in watchdog to timeout sourced by ACLK LPM3 is ; entered, this example will demonstrate WDT+ feature by automatically ; re-enabling WDT+ clock source as DCO if external XTAL fails This can be ; seen as a continued, though faster as clocked by DCO, watchdog timeout ; which will toggle on P1.0 in main function ; ACLK = 32kHz, MCLK = SMCLK = default DCO ; ; MSP430F20xx ; ; /|\| XIN|; | | | 32kHz ; |RST XOUT|; | | ; | P1.0| >LED ; ; M.Buccini / L Westlund ; Texas Instruments, Inc ; October 2005 ; Built with IAR Embedded Workbench Version: 3.40A ;******************************************************************************* #include "msp430x20x3.h" ; ORG 0F800h ; Program Reset ; RESET mov.w #0280h,SP ; Initialize stackpointer SetupWDT mov.w #WDT_ARST_1000,&WDTCTL ; Set Watchdog Timer timeout 1s bis.b #001h,&P1DIR ; P1.0 output xor.b #001h,&P1OUT ; Toggle P1.0 bis.w #LPM3,SR ; Mainloop jmp $ ; ; Interrupt Vectors ; ORG 0FFFEh ; MSP430 RESET Vector DW RESET ; END