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msp430x20x3 usi 06

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;****************************************************************************** ; MSP430F20xx Demo - I2C Master Receiver, single byte ; ; Description: I2C Master communicates with I2C Slave using ; the USI Slave data should increment from 0x00 with each transmitted byte ; which is verified by the Master ; LED off for address or data Ack; LED on for address or data NAck ; ACLK = n/a, MCLK = SMCLK = Calibrated 1MHz ; ; ***THIS IS THE MASTER CODE*** ; ; Slave Master ; (msp430x20x3_usi_09.s43) ; MSP430F20x2/3 MSP430F20x2/3 ; ; /|\| XIN|/|\| XIN|; | | | | | | ; |RST XOUT| |RST XOUT|; | | | | ; LED LED ; | SDA/P1.7| ->|P1.7/SDA | ; | SCL/P1.6|< -|P1.6/SCL | ; ; Note: internal pull-ups are used in this example for SDA & SCL ; ; P Thanigai ; Texas Instruments Inc ; May 2007 ; Built with IAR Embedded Workbench Version: 3.42A ;****************************************************************************** #include "msp430x20x2.h" #define I2CState R4 #define slav_data R5 #define slav_add R6 ; RSEG CSTACK ; Define stack segment ; RSEG CODE ; Assemble to Flash memory EVEN ; RESET StopWDT CheckCal Trap Load SetupP1 SetupP2 SetupUSI mov.w mov.w cmp.b jeq cmp.b jne jmp mov.b mov.b mov.b bis.b mov.b mov.b mov.b mov.b mov.b mov.b bis.b bic.b #SFE(CSTACK),SP ; Initialize stackpointer #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog timer #0FFh,&CALBC1_1MHZ ; Calibration constants erased? Trap #0FFh,&CALDCO_1MHZ Load $ ; Trap CPU!! &CALBC1_1MHZ,&BCSCTL1 ; Set DCO to 1MHz &CALDCO_1MHZ,&DCOCTL #0xC0,&P1OUT ; P1.6&P1.7 Pullups #0xC0,&P1REN ; P1.6&P1.7 Pullups #0xFF,&P1DIR ; unused pins as output #0x00,&P2OUT #0xFF,&P2DIR #USIPE6+USIPE7+USIMST+USISWRST,&USICTL0 ;Port, I2C master #USIIE+USII2C,&USICTL1 ; Counter interrupt, enable I2C #USIDIV_3+USISSEL_2+USICKPL,&USICKCTL ; SCL=SMCLK/8(~120KHz) #USIIFGCC,&USICNT ; #USISWRST,&USICTL0 ; Enable USI Mainloop bic.b clr.w clr.b mov.b #USIIFG,&USICTL1 I2CState slav_data #0x91,slav_add ; Clear pending flag bis.b bis.w nop call #USIIFG,&USICTL1 #LPM0+GIE,SR ; ; ; ; #Delay Set flag and start communication Enter LPM0, enable interrupts Used for debugger Delay between commn cycles jmp Mainloop ; USI_ISR ; ; add.w I2CState,PC ; I2C State Machine jmp STATE0 jmp STATE2 jmp STATE4 jmp STATE6 jmp STATE8 jmp STATE10 STATE0 bis.b #0x01,&P1OUT ; LED on: sequence start clr.b &USISRL ; Generate start condition bis.b #USIGE+USIOE,&USICTL0 ; bic.b #USIGE,&USICTL0 ; & send address to slave mov.b slav_add,&USISRL ; and transmit address R/W =1 mov.b &USICNT,R8 ; Bit counter = 8, Tx adress and.b #0xE0,R8 add.b #0x08,R8 mov.b R8,&USICNT mov.w #2,I2CState ; Go to next state rx address (N)ACK bic.b #USIIFG,&USICTL1 ; clear pending flag reti STATE2 ; Receive Address Ack/Nack bit STATE4 Data_Rx STATE6 bic.b bis.b mov.w bic.b reti #USIOE,&USICTL0 #0x01,&USICNT #4,I2CState #USIIFG,&USICTL1 bit.b jnc bis.b clr.b bis.b mov.w bis.b bic.b reti #0x01,&USISRL Data_Rx #USIOE,&USICTL0 &USISRL #0x01,&USICNT #10,I2CState #0x01,&P1OUT #USIIFG,&USICTL1 bis.b mov.w bic.b bic.b reti #8,&USICNT #6,I2CState #0x1,&P1OUT #USIIFG,&USICTL1 bis.b cmp.b jnz clr.b #USIOE,&USICTL0 slav_data,&USISRL Data_NACK &USISRL ; SDA = input ; Bit counter = 1, rx (N)ACK ; Go to next state, chk (N)ACK ; Process Address (N)Ack & data Rx ; if NACK received ; else ACK received ; bit counter = 1, SCL high, SDA low ; Go to next state, generate stop ; Turn on LED : error ; bit counter = 8, Rx data ; goto next state: Test data, (N)ACK ; LED off ; ; ; ; ; Send Data (N)Ack bit SDA = output if data valid data invalid , goto NACK loop send ACK Data_NACK STATE6_Exit STATE8 STATE10 inc.b bic.b jmp slav_data #0x01,&P1OUT STATE6_Exit ; Increment slave data ; LED off mov.b bis.b #0xFF,&USISRL #0x1,&P1OUT ; Send NACK ; LED on:error bis.b mov.w bic.b reti #0x1,&USICNT #8,I2CState #USIIFG,&USICTL1 ; Bit counter = 1, send NACK bit ; goto next state, prep stop bis.b clr.b bis.b mov.w bic.b reti #USIOE,&USICTL0 &USISRL #0x01,&USICNT #10,I2CState #USIIFG,&USICTL1 ; Pre stop condition ; SDA =output ; Bit counter = 1, SCL high, SDA low ; Go to next state, generate stop ; Generate stop condition mov.b #0xFF,&USISRL ; USISRL=1 to release SDA bis.b #USIGE,&USICTL0 ; Transparent latch enabled bic.b #USIGE+USIOE,&USICTL0 ; Latch/SDA output disabled mov.w #0,I2CState ; Reset state machine for next Tx bic.w #LPM0,0(SP) ; Exit active for next transfer bic.b #USIIFG,&USICTL1 reti ; Delay ; Delay between communication cycles ; mov.w #0xFFFF,R7 DL1 dec.w R7 jnz DL1 ret ; ; Interrupt Vectors Used MSP430x2013 ; COMMON INTVEC ORG RESET_VECTOR ; MSP430 RESET Vector DW RESET ; ORG USI_VECTOR ; USICNT DW USI_ISR ; END

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