//****************************************************************************** // MSP430G2xx2 Demo - WDT+ Failsafe Clock, 32kHz ACLK // // Description; Allow WDT+ in watchdog to timeout sourced by ACLK LPM3 is // entered, this example will demonstrate WDT+ feature by automatically // re-enabling WDT+ clock source as DCO if external XTAL fails This can be // seen as a continued, though faster as clocked by DCO, watchdog timeout // which will toggle on P1.0 in main function // ACLK = 32kHz, MCLK = SMCLK = default DCO // // MSP430G2xx2 // // /|\| XIN|// | | | 32kHz // |RST XOUT|// | | // | P1.0| >LED // // D Dang // Texas Instruments, Inc // December 2010 // Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10 //****************************************************************************** #include void main(void) { WDTCTL = WDT_ARST_1000; P1DIR |= 0x01; P1OUT ^= 0x01; _BIS_SR(LPM3_bits); } // Set Watchdog Timer timeout 1s // Set P1.0 to output // Toggle P1.0