3958 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL 58, NO 9, SEPTEMBER 2011 An Optimized Discontinuous PWM Method to Minimize Switching Loss for Multilevel Inverters Nho-Van Nguyen, Member, IEEE, Bac-Xuan Nguyen, and Hong-Hee Lee, Member, IEEE Abstract—This paper presents a novel approach to analyze carrier-based discontinuous pulse width modulation (DPWM) method for multilevel inverters The separation of the offset into the main and additional components shows the use for analyzing PWM control characteristics of multilevel inverters The results are then applied to propose a novel minimized loss DPWM method by varying the offset depending on peak values of three-phase load currents As results of avoiding commutations at high currents, the switching loss can be reduced The proposed method is theoretically analyzed and verified by experimental results Index Terms—Discontinuous pulse width modulation (DPWM), multilevel inverter, switching losses I I NTRODUCTION I N RECENT YEARS, multilevel inverters have been intensively developed for the high-performance applications [1]–[4] Their main topologies, such as diode-clamped type, cascaded type, and capacitor-clamped type, are commonly used, as shown in Fig Three pulse width modulation (PWM) techniques, such as selective harmonic elimination PWM (SHE PWM), carrier-based PWM (CPWM), and space vector PWM (SVPWM), have been favorably used in practice Because of having a small number of switching, the SHE PWM method shows advantage for high-power applications Two remaining PWM techniques are commonly used in various fields because of their excellent PWM qualities The discontinuous PWM (DPWM) methods of two-level inverters have been studied for many years, and they are introduced as an approach to reduce the switching loss [5]–[11] DPWM methods can be realized using the SVPWM approach by eliminating one from the redundant zero vectors in the switching state sequence [6] or CPWM ones by adding offset to make some leg-voltage attain one of two dc-rail levels [7]–[10] Some studies were concentrated on analyzing the impacts of DPWM waveforms on the current ripple [5], [7] A space vector DPWM strategy for two-level inverter was proposed for minimizing the switching loss [6] The switching state sequence was selected in relation to the current vector position to avoid commutations at the peak current Its principle was further extended for the whole range Manuscript received August 1, 2009; revised January 12, 2010 and March 29, 2010; accepted May 14, 2010 Date of publication January 17, 2011; date of current version August 12, 2011 N.-V Nguyen and B.-X Nguyen are with the Department of Electrical Engineering, Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam (e-mail: nvnho@hcmut.edu.vn; nxbac@hcmut.edu.vn) H.-H Lee is with the Department of Electrical Engineering, University of Ulsan, Ulsan 680-749, South Korea (e-mail: hhlee@mail.ulsan.ac.kr) Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org Digital Object Identifier 10.1109/TIE.2010.2102312 Fig Circuit diagram of five-level neutral point-clamped (NPC) inverter of the load power factor, but with the CPWM approach, the offset is modified to make commutation instants disappear at the highest current amplitudes [9] The description of current situations for the extended range was not clear The drawback was that it was a need of a detector of current vector position, angular conversion, and rotation operation Regarding the load power factor, other offset proposal of the optimal general DPWM was also found in [8] It was proven that the switching loss can be reduced to about 50–63% of the conventional continuous PWM method Studying of the minimized switching loss PWM technique for two-level inverter was then applied for the active power filter [12] There have been recently several studies about DPWM methods for multilevel inverter [13]–[16] The multicarrier-based DPWM methods for multilevel inverters are being deduced, in principle, similar to that of a two-level inverter For two-level inverters, two zero redundant vectors did not cause any complication with offset control The relationship between offset and switching states was simply clarified in [7], [10] However, the obtained results have not extended enough for multilevel inverters It is due to the complication given by the existence of a larger number of redundant vectors, which offer a lot of possibilities for producing the DPWM offset function One of the typical DPWM methods was proposed for medium common mode [13], [14] Unfortunately, the described algorithm would be hardly applied to other DPWM cases The load current character and related DPWM algorithms for reducing switching loss have not been considered Obviously, to formulate a universal carrier-based DPWM technique like being attained in two-level inverters requires a comprehensive study 0278-0046/$26.00 © 2011 IEEE NGUYEN et al.: OPTIMIZED DISCONTINUOUS PWM METHOD TO MINIMIZE SWITCHING LOSS FOR MULTILEVEL INVERTERS 3959 Fig Explanation of voltage components in proposed model of multilevel inverter Normally, a CPWM method can be developed in two stages as follows: 1) producing fundamental reference and common mode voltages [4] and 2) modifying the common mode voltage to improve PWM performance Besides modifying in DPWM, the previously mentioned PWM method for attaining medium common mode voltage can be also modified in SVPWM [17] Flexibility of carrier PWM can be fully analyzed in a general carrier PWM approach with any reference common mode [16] To have a deep understanding of carrier PWM method in these stages, it should be brought out the impacts of the common mode components on the control characteristics of multilevel inverters In this paper, a novel universal approach of CPWM methods in multilevel inverters will be presented As an application, a DPWM algorithm to minimize switching loss with consideration on variable load currents will be proposed Fig Explanation of relationship between carrier PWM method and reference voltages II VOLTAGE M ODEL FOR M ULTILEVEL I NVERTER The relationship between voltage model and modulating signals in a Carrier Phase Disposition PWM method can be clarified in Fig The voltage quantity Vx , x = a, b, c, will be presented in relation to the control signal vx (Vdc is the voltage on one dc cell) as follows: Define reference inverter voltages between the output and dc-reference point “0,” consisting of active voltages Vx12 , x = a, b, c, and the reference common mode V0ref , as shown in Fig 2, as follows [16]: Vxref = Vx12 + V0ref V0M in , as follows: V0M in ≤ V0ref ≤ V0M ax V0M ax = (n − 1)Vdc − M AX V0M in = − M IN Define Vk , k = 0, 1, 2, , (n − 1) voltage levels on the dc side as follows: Vk = kVdc Va12 = Vref cos θ VL(x) ≤ Vxref ≤ VH(x) VH(x) = (VL(x) + Vdc ) Vx = vx Vdc (2) Define M AX and M IN as, respectively, the maximum and minimum values from three-phase active voltages as follows: M AX = M ax(Va12 , Vb12 , Vc12 ) (3a) M IN = M in(Va12 , Vb12 , Vc12 ) (3b) Reference common mode voltage V0ref is a zero-sequence component defined within the limited boundaries of V0M ax and (6) (7) The following quantities: vxref , vx12 , v0ref , and v0add correspond to reference inverter voltage, active voltage, reference common mode, and additional common mode voltages, respectively For them, their relationship is expressed in vector form as follows: Vb12 = Vref cos(θ − 2π/3) Vc12 = Vref cos(θ − 4π/3) (5) Among them, define VL(x) and VH(x) two active voltage levels closest to the reference voltage Vxref (Fig 2) (1) Active voltages: Vx12 can be determined from the amplitude Vref and phase angle θ of the voltage vector as follows: (4a) (4b) (4c) vref = v12 + v0ref I, I = [1, 1, 1]T vref = vref + v0add I (8a) (8b) vref = [varef , vbref , vcref ]T v12 = [va12 , vb12 , vc12 ]T (9) where In (8a) and (8b), the reference v0ref and additional common mode v0add are two components of a unified common mode voltage 3960 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL 58, NO 9, SEPTEMBER 2011 Fig Explanation of producing additional common mode Fig Switching diagram in normalized two-level inverter TABLE I NOMINAL SWITCHING STATES AND SWITCHING TIME DUTIES Fig (a) Reference vector in vector triangle, (b) Switching time diagram in active carrier waveforms in multicarrier PWM An inverter voltage is varied between the two active levels of VH(x) and VL(x) , where indexes L(x) and H(x) are deduced as two integer values closest to the reference signal vxref , x = a, b, c, which satisfies the conditions (Figs 3–5) according to n(x) n(x) − = L(x) + L(x) = H(x) if ≤ vxref < (n − 1) if vxref = (n − 1) (10) where n(x) = Int(vxref ); x = a, b, c (11) Nominal carrier waveform: a carrier waveform varying in the range of (0, 1) Nominal modulating signals ξx , ≤ ξx ≤ 1, are defined as subtractions of the following: ξx = vxref − L(x) ; x = a, b, c (12) Define maximum, medium, and minimum values of the three-phase nominal modulating signals as follows: max = M ax(ξa , ξb , ξc ) mid = M id(ξa , ξb , ξc ) = M in(ξa , ξb , ξc ) The vectors sM ax and sM id identify the relative position of nominal modulating signals in a nominal carrier waveform For instance, two vectors sM ax = [1, 0, 0]T and sM id = [0, 0, 1]T give ξa > ξc > ξb The intersections between the nominal carrier waveform and three-phase nominal modulating signals ξx will define switching state sequence s1 , s2 , s3 , and s4 , as shown in Fig Their corresponding switching time duties K1 , K2 , K3 , and K4 can be deduced in Table I The nominal switching states s1 and s4 are corresponding to two active zero redundant states in a virtual two-level inverter These nominal vectors s1 , s2 , s3 , and s4 and switching state sequence S1 , S2 , S3 , and S4 of multicarrier PWM method are closely related as follows: Sj = L + sj , (17) The vectors L, ξref , s1 , s2 , s3 , and s4 can be used to characterize switching behavior of multilevel inverters The switching process of multicarrier PWM method can be simply followed by a single-carrier PWM method of the virtual two-level inverter The transforming vector helps to define actual switching states Similar equations for SVPWM, multicarrier, and singlecarrier PWM can be deduced as follows: (13) Define sM ax and sM id vectors as T sM ax = [saM ax , sbM ax , scM ax ] sM id = [saM id , sbM id , scM id ]T j = 1, 2, 3, Vref = K1 V1 + K2 V2 + K3 V3 + K4 V4 (18) vref = K1 S1 + K2 S2 + K3 S3 + K4 S4 (19) ξref = K1 s1 + K2 s2 + K3 s3 + K4 s4 (20) (14) where where for x = a, b, c sxM ax = sxM id = 1 if max = ξx else if mid = ξx else (15) (16) Vj = Vdc Sj ξref = vref − L K1 + K2 + K3 + K4 = (21) (22) (23) NGUYEN et al.: OPTIMIZED DISCONTINUOUS PWM METHOD TO MINIMIZE SWITCHING LOSS FOR MULTILEVEL INVERTERS 3961 III M ODIFIED CPWM M ETHOD A DPWM Method Without Minimized Switching Loss A modified carrier PWM method is established based on adding an additional common mode voltage V0add to the reference inverter voltage Vxref (Fig 4) In carrier PWM implementation, the active components remain unchanged while an additional offset v0add can be set within defined limits The additional offset in multilevel inverter should avoid extra switching The modified voltages would attain one of some closest dc-levels with possibly a minimum move of leg voltages In the nominal switching diagram, this happens as adding an offset ξ0 to the references ξx The offset ξ0 = v0add is defined as follows: ξ0M in ≤ ξ0 ≤ ξ0M ax (24a) ξ0M ax = − max = K1 (24b) ξ0M in = − = −K4 (24c) Adding the offset ξ0 redistributes time duties as follows: K1 = K1 − ξ0 ; K2 = K2 ; K3 = K3 K4 = K4 + ξ0 (25) The control characteristics of a CPWM method in multilevel inverters can be described completely by (4), (24), and (25) The offset function v0ref makes carrier PWM in multilevel inverters different from that in two-level inverters The selected value of v0ref determines the active low leg voltage levels (L), which define the first one from the switching states involved in the commutation sequence Therefore, the selection of v0ref is decisive to switching state sequence For conventional twolevel inverter, this step is not significant because both two levels of the leg voltages and related switching state sequence in the considered hexagon sector are totally known Adjusting the second offset ξ0 enables to attain the PWM behaviors of multilevel inverters It is realized in a similar way as in two-level inverters [7], [10] Its value adjusts the time duty distribution of the involved redundant vectors that influence PWM quality Shortly, the first offset v0ref presents a particular solution of the carrier PWM control problem in multilevel inverters and defines switching state sequence The second offset ξ0 (and nominal signals) will give a common solution and define the time—duties It becomes a control variable of the universal CPWM method in multilevel inverters For DPWM with minimized offset error, the additional offset ξ0 can be deduced as follows: ξ0 = K1 −K4 for K1 < K4 for K4 < K1 If K1 = K4 for reducing the common mode voltage against the dc midpoint, it is set as follows: ξ0 = K1 −K4 (28) d1 = |v0ref + K1 − 0.5(n − 1)| d4 = ||v0ref − K4 | − 0.5(n − 1)| (29) For DPWM method with minimized offset error, the diagrams of reference modulating signal, the common mode, and the modified modulating signal for m = 0.9, are shown in Fig The corresponding offsets are set for minimum and medium common modes, respectively Their related offset components v0ref are defined as follows [16]: (26) v0ref (27) for d1 < d4 for d1 > d4 where v0ref = (v0M ax + v0M in )/2 The offset error is determined as follows: e0 = M in(K1 , K4 ) Fig Three-level NPC Inverter DPWM without optimized switching loss for m = 0.9 in (a) minimum and (b) medium common modes Diagrams of modulating signal varef —(8a) and modified modulating signal varef —(8b) ⎧ ⎨ v0M in = 0.5(n − 1) ⎩ v0M ax (30a) if 0.5(n − 1) < v0M in ≤ v0M ax if v0M in ≤ 0.5(n − 1) ≤ v0M ax if v0M in ≤ v0M ax < 0.5(n − 1) (30b) 3962 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL 58, NO 9, SEPTEMBER 2011 Fig (a) Algorithm diagram for producing reference modulating signals in the optimized DPWM method B Optimized DPWM for Variable Load Power Factor The principle is that an additional common mode will be adjusted for producing a DPWM mode, which avoids commutation for the phase of the absolute highest current If it does not happen, the phase of the second highest current value will be set for no commutation For variable load power factor, the idea of optimized switching loss in two-level inverters [6], [9] can be extended for multilevel inverters Some modifications are needed and with the help of the proposed carrier PWM method The proposed algorithm is shown in Fig From the original voltage reference vxref given by (8a) and (30), the three-phase nominal modulating signals ξa , ξb , and ξc can be deduced using (10)–(12), whose maximum and minimum values are determined as max and (13) Additional common mode is designed to limit resulting signals within the active carrier range First, an additional offset is proposed to avoid commutation at the phase of absolutely maximum current If not, an extra offset to avoid commutation at medium current will be selected As a result, commutations will be disappeared either in a phase of maximum peak current or a medium one The algorithm requires measuring load currents In the diagram, parameters Imax and Imid are, respectively, the largest and medium absolute values from three-phase load currents, i.e., Parameters xIM ax and xIM id are two indexes from three abc coordinates, corresponding to maximum and medium currents in (31) Because there is no need of the detector of current vector position, the proposed implementation is more advantageous than the algorithm in [9] An investigation on the effect of the proposed algorithm for various load power factors has been realized For demonstration, a simulation of the DPWM algorithm with medium common mode for m = 0.5 was implemented The simulation results are shown in Fig Three-phase load R − L was set as R = Ω and L = 0.08 H(PF = 0.125) Finding the exact DPWM offset functions v0ref for dc voltage balancing while attaining optimized switching loss is beyond the scope of this paper The three nearest vectors—NTV with a minimized number of switching could almost achieve dc voltage balance, by selecting the starting state (corresponding to the lowest levels of the leg voltages) of the sampling period [18], [19] The selected vector could give an equivalent v0ref , then the introduced algorithm can be applied for deducing ξ0 However, the previous algorithm which was presented makes the dc balancing slow down [18] To get a better response for balancing dc voltages, multiple-switching algorithms can be used, but they cause more switching loss [20] Generally, they have a different character from conventional CPWM techniques C Comparison of Switching Loss Imax = M ax (|ia |, |ib |, |ic |) Imid = M id (|ia |, |ib |, |ic |) (31) In conventional carrier PWM method, there is only one switch involved in sampling period during transient in each NGUYEN et al.: OPTIMIZED DISCONTINUOUS PWM METHOD TO MINIMIZE SWITCHING LOSS FOR MULTILEVEL INVERTERS 3963 Fig 10 Optimal DPWM SLF diagram deduced for two-level inverter Fig Three-level inverter: Optimized DPWM for modulation index of m = 0.5 Diagrams of optimized modulating signal A-phase, load currents, and trigger pulses to switching pairs of A-phase Load R = Ω and L = 0.08 H phase Let us suppose diodes to be ideal, the active switch would have to maintain 100% voltage during the current transition For n-level NPC inverter, the voltage across the switch is high as the current changes, equal to the off-state voltage Vof f as follows: Vof f = Vdc (32) A linear and rectangular commutation can be used to calculate the average value of the local switching loss over the fundamental cycle Ts of any phase as follows [8], [21]: 2π Pswave = Vof f (ton + tof f ) 2π 2Ts fi (θ)dθ (33) where fi (θ) = |ia |, 0, ξa = ∧ ξa = else (34) The switching loss function (SLF) is found as follows: SLF = P0 = Pswave P0 (35) Vof f (ton + tof f )Im πTs (36) where Im is the amplitude of the load phase current; and P0 is the switching loss value under continuous PWM condition In two-level inverter, the offset range is limited within the defined two dc rails As a result, the optimized SLF is easily deduced, dependent on only the load power factor Applying the proposed optimized algorithm for the two-level inverter, the diagram of the SLF function was drawn, as shown in Fig 10 The obtained SLF diagram is similar to that of the optimal PWM method in [8], but in comparison with its diagram, the Fig 11 Three-level NPC inverter Function SLF = f(m, ϕ) for medium common mode optimized DPWM SLF function of the proposed DPWM attains smaller values close to ±75◦ In the multilevel inverter, the reference three-phase voltages can appear differently among carrier bands Any change in the fundamental voltage or the offset may change relative positions of the three phases to the closest dc-levels The SLF function can be properly used to evaluate the effectiveness of the proposed DPWM method, which for given offset function, depends on the load power factor and modulation index To demonstrate it, the SLF of two popular cases as the minimum and medium common mode DPWM, has been calculated for three- and fivelevel inverters and shown in Figs 11–14, respectively For the three-level inverter, because of the small difference of the SLF function in two previously mentioned DPWM methods, only one of them is shown in Fig 11 Different behaviors from both DPWM methods appear obviously for the five-level inverter for modulation index range of m > 0.25 The influence of the load power factor on the SLF function of DPWM methods can be investigated For example, if ϕ = 0◦ , two DPWM methods have similar behaviors for m < 0.5, as shown in Fig 12 For 0.63 < m < 0.73 and 0.825 < m < 1, the SLF of the minimum common mode DPWM attains value less than 0.56 and 0.54, respectively, while the medium common mode DPWM introduces SLF values less than 0.54 and 0.57 for 0.5 < m < 0.63 and 0.73 < m < 0.825, respectively 3964 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL 58, NO 9, SEPTEMBER 2011 Fig 14 Five-level NPC inverter Function SLF = f(m, ϕ) for minimum common mode optimized DPWM Fig 12 Five-level inverter Functions SLF for (curve 1) minimum and (curve 2) medium common mode for (a) ϕ = 0◦ and (b) ϕ = 30◦ Fig 15 Experimental results: Modulation index of m = 0.5 Modulating signal corresponding to two switching pairs of A-phase and three-phase currents on DSPACE Control Desk Fig 13 Five-level NPC inverter Function SLF = f(m, ϕ) for medium common mode optimized DPWM As a result, if a combination of two DPWM methods is applied, the SLF function will attain a value less than 0.57 for the whole modulation index It is except the vicinity of m = 0.3, where SLF can reach a maximum value of 0.63 Similarly, for ϕ = 30◦ , the SLF can achieve values less than 0.57, as shown in Fig 12(b) The complete space diagrams to describe the SLF function of variables m and ϕ for the five-level inverter are drawn for medium and minimum common mode optimized DPWM methods, as shown in Figs 13 and 14, respectively IV E XPERIMENTAL R ESULTS The proposed algorithm was verified with the use of three-phase three-level NPC inverter Experimental hardware used power devices insulated-gate bipolar transistor FG60N100BNTD and the control kit DSPACE DS1104 Two dc voltages obtained from the output of a single-phase rectifier were then filtered out by two capacitors of 4700 μF They were measured utilizing the LEM LV25 NP; the load currents were Fig 16 Experimental results: Modulation index of m = 0.5 Two-phase load currents measured with the Hall sensors LEM LA 25NP via the lowpass filter, whose cutoff frequency was set at 500 Hz The resulting data were passed to the DS1104 processor Control parameters and diagrams, such as load currents and modulating signals, were also monitored and viewed on a DS1104 Control Desk Developer The frequency of the triangle carrier waveform was selected as kHz Parameters were set as Vc1 = 75 V, Vc2 = 75 V; fout = 50 Hz A 3-hp three-phase induction motor at a balanced load was used For demonstration, the PWM algorithm to optimize switching loss was implemented for m = 0.5 (Figs 15–18) For these experiments, the power factor of the NGUYEN et al.: OPTIMIZED DISCONTINUOUS PWM METHOD TO MINIMIZE SWITCHING LOSS FOR MULTILEVEL INVERTERS 3965 Fig 17 FFT diagram of A phase load current for m = 0.5 Fig 20 DC voltages measured on two capacitors for m = 0.5 Fig 18 FFT of A-phase load voltage for m = 0.5 Fig 21 DC voltages measured on two capacitors for m = 0.9 V C ONCLUSION Fig 19 Diagrams of three-phase load currents and A-phase modulating signals when modulation index changed abruptly from m = 0.2 to m = (R − L load, R = 10 Ω, L = 0.18 H) load was determined to be 0.125, the same as that in the previous simulation In these figures, the corresponding diagrams of modified modulating signal of two switching pairs of A-phase, two-phase load currents, and related fast Fourier transform (FFT) analysis are drawn A discontinuous commutation happened at the maximum current values, as shown in Fig 15 In other experiments with R − L load, R = 10 Ω and L = 0.18 H, the response of modulating signals in the proposed DPWM algorithm after a step change of modulation index from 0.2 to was followed in Fig 19 Finally, the dc neutral fluctuations for the continuous PWM and the proposed DPWM were tested for m = 0.5 and m = 0.9 were shown in Figs 20 and 21, respectively Their response was shown the same For limited pages, there were presented only the diagrams of the proposed DPWM method For small modulation index, the voltage fluctuation was negligible In this paper, a novel analysis of the multilevel inverter model has been proposed Two offset components have characterized entirely features of CPWM methods The proposed PWM method was then applied to optimize the switching loss by avoiding commutations at the peak load currents Being different from the two-level inverter, the optimized DPWM SLF function is dependent on the modulation index The two popular as the minimum and medium common mode-based optimized switching loss DPWM algorithms would properly give a beneficial reduction of switching loss Moreover, the method is advantageous for its simple algorithm The proposed method has been verified by the simulation and the experimental results R EFERENCES [1] J I Leon, S Vazquez, J A Sanchez, R Portillo, L G Franquelo, J M Carrasco, and E Dominguez, “Conventional space-vector modulation techniques versus the single-phase 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the sampled amplitudes of reference phase voltages,” Proc Inst Elect Eng.—Elect Power Appl., vol 152, no 2, pp 297–309, Mar 2005 [18] J Pou, R Pindado, and D Boroyevich, “Voltage-balance limits in fourlevel diode-clamped converters with passive front ends,” IEEE Trans Ind Electron., vol 52, no 1, pp 190–196, Feb 2005 [19] G Sinha and T A Lipo, “A four-level inverter based drive with a passive front end,” IEEE Trans Power Electron., vol 15, no 2, pp 285–294, Mar 2000 [20] K Yamanaka, A M Hava, H Kirino, Y Tanaka, N Koga, and T Kume, “A novel neutral point potential stabilization technique using the information of output current polarities and voltage vector,” IEEE Trans Ind Appl., vol 38, no 6, pp 1572–1580, Nov./Dec 2002 [21] P Krein, Fundamentals of Power Electronics, Textbook New York: Oxford, 1988 Nho-Van Nguyen (M’05) received the M.S and Ph.D degrees in electrical engineering from the University of West Bohemia, Pilsen, Czech Republic, in 1988 and 1991, respectively Since 2007, he has been an Associate Professor with the Faculty of Electrical and Electronics Engineering at Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam He did his postdoctoral research at the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2001 and was a Visiting Professor from 2003–2004 He was a Visiting Scholar at the Department of Electrical Engineering, University of Illinois at Urbana–Champaign, in 2009 His research interests include modeling and control of ac motors, active filters, and pulse width modulation techniques Bac-Xuan Nguyen received the M.S degree in automatic control engineering from the Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam, in 2009 He is a Lecturer in the Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology His research interests mainly include advanced control of electrical machines and power electronics Hong-Hee Lee (S’88–M’91) received the B.S., M.S., and Ph.D degrees in electrical engineering from Seoul National University, Seoul, South Korea, in 1980, 1982, and 1990, respectively From 1994 to 1995, he was a Visiting Professor at Texas A&M University, College Station Since 1985, he has been a Professor of electrical engineering at the University of Ulsan, Ulsan, South Korea He is also the Director of the Network-based Automation Research Center, which is sponsored by the Ministry of Knowledge Economy His research interests are power electronics, network-based motor control, and control networks Dr Lee is a member of the Korean Institute of Power Electronics, the Korean Institute of Electrical Engineers, and the Institute of Control, Robotics, and Systems ... al.: OPTIMIZED DISCONTINUOUS PWM METHOD TO MINIMIZE SWITCHING LOSS FOR MULTILEVEL INVERTERS 3959 Fig Explanation of voltage components in proposed model of multilevel inverter Normally, a CPWM method. .. DISCONTINUOUS PWM METHOD TO MINIMIZE SWITCHING LOSS FOR MULTILEVEL INVERTERS 3961 III M ODIFIED CPWM M ETHOD A DPWM Method Without Minimized Switching Loss A modified carrier PWM method is established... carrier PWM method, there is only one switch involved in sampling period during transient in each NGUYEN et al.: OPTIMIZED DISCONTINUOUS PWM METHOD TO MINIMIZE SWITCHING LOSS FOR MULTILEVEL INVERTERS