DSpace at VNU: Eliminated Common-Mode Voltage Pulsewidth Modulation to Reduce Output Current Ripple for Multilevel Inverters

DSpace at VNU: Eliminated Common-Mode Voltage Pulsewidth Modulation to Reduce Output Current Ripple for Multilevel Inver...

This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 Eliminated Common-Mode Voltage Pulsewidth Modulation to Reduce Output Current Ripple for Multilevel Inverters Tam-Khanh Tu Nguyen, Nho-Van Nguyen, Member, IEEE, and Nadipuram (Ram) R Prasad, Member, IEEE  complete CMV elimination can be found in [11-17] Abstract— The paper presents an analysis on the output current-ripple in zero Common Mode Voltage (ZCMV) PWM control of multilevel inverters The modulation strategy for Common Mode Voltage (CMV) elimination in multilevel inverters is based on the “three zero common mode vectors” principle The space vector diagram, which consists of vectors of zero common mode voltage, is fully explored by properly depicting the base voltage vectors and their corresponding active switching vectors The switching patterns are limited to those of three switching states each of which is symmetrically distributed Based on the PWM process simplified to that of a two-level inverter with three allowable switching states and the degree of freedom existing in the switching states arrangement, a novel carrier-based PWM method with optimized output current ripple is proposed Compared to the existing PWM methods which utilize the same kind of switching patterns, the proposed PWM method has reduced considerably the RMS current ripple and total harmonic distortion (THD) of the output-current in a wide region of the modulation index The effectiveness of the proposed method is validated by both simulation and experimental results SW1A Vdc SW2A AC motor C B N A O g g Vdc a) Vdc Vdc SW1A SW3A SW2A SW4A Vdc Vdc A AC motor O g Vdc Vdc B Multilevel Inverter, Common-mode voltage, Current-ripple, Harmonic distortion, Pulse Width Modulation (PWM), PWM inverters Index Terms— N g C I INTRODUCTION C ommon-mode voltages are associated with excessive bearing currents, which may cause premature motor bearing failure and electromagnetic interference [1-2] There are a number of approaches to cope with the CMV issue, including the use of extra hardware with passive and/or active devices [3-4] However, the extra hardware causes a significant increase in the system’s volume or creates much more complex methods of control The multi-level inverters [5-6], as shown in Fig.1, have a high number of switching states that can either reduce or eliminate the CMV Based on this advantage, many studies of CMV mitigation have been conducted using multi-level inverters [7-17] The PWM methods with partial CMV elimination are presented in [7-10] while PWM methods with Tam.-K.T Nguyen and Nho.-V Nguyen are with the Department of Electrical Engineering, Ho Chi Minh city University of Technology, Ho Chi Minh City, Viet Nam (e-mail: nkttam@hcmut.edu.vn; nvnho@hcmut.edu.vn) Nadipuram (Ram) R Prasad is with the Klipsch Scool of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, 88003-8001, USA (e-mail: ramprasad@msn.com) b) Fig Multilevel Inverter system: a) three-level NPC inverter; b) five-level cascaded inverter In previously reported works [11-12], the ZCMV PWM is applied to a three-level Neutral Point Clamped (NPC) Inverter In [13], the PWM strategies for CMV reduction/elimination are developed for a five-level NPC inverter Work reported in [14] proposes PWM strategies for partial and complete CMV elimination in cascaded multilevel inverters However, the degree of freedom in the switching states arrangement is not investigated in the mentioned works In [16], a PWM strategy that utilizes one nearest vector of ZCMV with respect to the desired output voltage vector during one carrier cycle is presented The method, however, is suitable for a high number of inverter levels at which the existing voltage error can be ignored A solution for ZCMV PWM in multilevel that takes into account the degree of freedom in the switching sequence arrangement is recently reported in [17] The work has proposed a simple carrier based PWM method for 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 multilevel inverter using the three ZCMV vectors principle The resultant switching patterns are limited to those of a minimum number of switching states, which helps to globally reduce the switching loss By using a proposed current-based mapping technique, the switching loss can be locally reduced up to 25% as compared to the non-optimized algorithms The current ripple reduction is significant in practice Reducing the current ripple can result in a lower torque pulsation of motor drive [24-25], reduction in motor acoustic noise [27], and also a reduction in motor heating The PWM techniques for a reduced current ripple are specifically useful for high power applications, where the switching frequency is quite low [25],[39] For these reasons, the current ripple has been the subject of extensive research for decades [18-39] The current ripple analysis of a two-level inverter can be found in many works [18-33] The work reported in [18] analyzed the impact of zero space vector distribution on the output current ripple In [19], the switching sequence arrangement of the space vector PWM (SVPWM) is considered for the purpose of reducing the output current ripple It has been shown in [20-21] that the discontinuous PWM strategy (DPWM) can be properly applied so that the output current ripple is reduced compared to PWM methods with the same average switching frequency In the work [24], the geometrical analysis of the current ripple vector corresponding to a conventional SVPWM pattern is presented and the CMV is utilized as a degree of freedom to minimize the RMS output-current The latter works [25-27] proposed a more generalized method of output current ripple analysis The switching patterns can be extended for division of active vector time [25],[27] and an effective hybrid PWM technique which combines multiple switching sequences to reduce the current ripple is further suggested [26] Recently, the output current ripple analysis and optimized control methods have been developed for the multi-phase two-level systems [28-31] Also, current ripple analysis in term of the peak-to-peak value has been reported in the works [32-33] The current ripple analysis is further extended to high level inverters as can be found in [33-37] The works [36-37] present investigations on the current ripple for the three-level operation based on dual two-level VSI The DPWM method is also employed in [37] to reduce the switching loss as well as the current ripple The work [34] introduces novel switching sequences of the three-level NPC inverter with corresponding current ripple investigations Based on [34], a hybrid PWM technique [35] is proposed that helps reduce the current ripple In ZCMV PWM control, greater distances between the three active vectors lead to increased current ripple and higher THD compared to the conventional PWM control [12],[22] Although the ZCMV PWM for multilevel inverters has been the main subject of many aforementioned works [12-17], no study has considered the ZCMV PWM technique for current ripple reduction thus far The Switching loss optimizing PWM [17] that considers using the degree of freedom in the switching states arrangement, however, results in higher output current ripple than other PWMs with non-optimized algorithms In this paper, an output current ripple analysis of multi-level inverters under condition of ZCMV is presented The designed switching patterns satisfy the “three ZCMV vectors” principle with a minimum number of commutations The current ripple is theoretically investigated using the notion of harmonic flux Based on the degree of freedom in the switching states arrangement, a PWM strategy is proposed to optimize output current ripple The rules to select the optimum switching sequence deduced from the current ripple analysis are simple for an online implementation Also, the proposed PWM method can be simply applied to a high level inverter without losing the generality The proposed ZCMV PWM method is developed and simulated for the three-level NPC inverter and the five-level cascaded inverter The harmonic flux characteristics obtained from simulated data of the proposed ZCMV PWM method and existing ZCMV PWM methods characterized by the same kind of patterns in [17] are presented to highlight the improved performance of the RMS current ripple Also, comparisons of the weighted total harmonic distortion (WTHD) factor characteristics of the line voltage are shown to demonstrate the improved THD of the proposed PWM method In experiment, the proposed PWM method is verified on a five-level cascaded inverter fed constant volt-per-hertz (V/f) drive Comparative results of the RMS current ripple characteristics as well as the current THD characteristics are shown for experimental validation II PWM METHOD TO ELIMINATE COMMON MODE VOLTAGE The ZCMV PWM in multi-level inverters has been analyzed in detail in the previous work [17] For the sake of clarity of the proposed PWM method development, the analytical method is briefly summarized in this section In the systems of multi-level inverter fed AC motor drive as described in Fig 1, the CMV is defined as the voltage difference between the stator winding neutral N and the midpoint O of the DC-link [13] The CMV in Fig can also be expressed in terms of the pole voltages (each of which measured from one output terminal to the mid-point O of the DC-link voltage) as: V  VBO  VCO (1) VCM  VNO  AO The condition of ZCMV defines the space vector diagram of a five-level inverter with 19 switching combinations of (VAO, VBO, VCO) of ZCMV as shown in Fig Assume that each DC-link voltage defined as Vdc in Fig is ideal DC voltage For a three phase n-level inverter, the modulation index can be defined as: v1 m (2) n 1 Vdc where v1 is the peak value of the fundamental component of the actual phase voltage and (n  1)Vdc / is the maximum 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 peak value of the fundamental voltage in linear control that the inverter can produce In linear modulation of ZCMV PWMs control, the maximum value of the modulation index defined by (2) is 0.866 [12-17]  axis b axis 040 041 043 044 031 032 033 122 024 014 013 004 213 204 301 302 303 203 103 411 400 integer value of v Xn The condition of zero average CMV leads to:  axis a axis F  FL  Fe  3(n  1) / 401 403 c axis Fig Five-level space vector diagram with zero CMV states (bold letters) The analytical process for the diode-clamped inverter and cascaded inverter is unified by a simple voltage modeling For an n-level inverter of the two topologies, the pole-voltage VXO ( X  A, B, C) can be generalized as: n 1 VXO  ( s jX j 1 )Vdc  n 1 Vdc (3) s1X  s2 X   sn  X s n 1X ; X  A, B,C (for the diode clamp inverter topology ) (4) where s1X, s3X,…, sn-1X represent the switching states of switches SW1X , SW2X ,…, SWn-1X which, for example, are designated in Fig for the A-phase of the two topologies; s1X is if SW1X is on, otherwise its value is n1 The component s jX (10) 402 404 304 (9) where, Int (v Xn ) denotes a function that returns a nearest lower 410 311 202 Normalized state of the base voltage vector 420 310 312 212 113 104 211 222  X  v Xn  LX ; X  A, B, C 430 320 321 221 112 114 330 Int (v Xn ) if v Xn  n  LX   ;0  LX  n  2; X  A, B, C n  if v Xn  n  (8) Normalized switching state of zero CMV 440 220 231 121 123 023 034 131 132 022 340 230 130 141 042 240 140 deduced as follow: ( X  A, B, C ) in (3) is called the j 1 normalized switching voltage which is denoted as V Xn : where, FL  LA  LB  LC and Fe   A   B   C The functions F , FL , Fe are termed the total switching voltage, total base voltage, and total active voltage, respectively The values of FL and Fe which are available for ZCMV PWM control, are limited to two specific cases as: -The case of FL  3(n  1) /  , Fe  , which is realized with three active switching states of (1,1,0), (0,1,1), and (1,0,1) in the active voltage hexagonal diagram as shown in Fig 3(a) - The case of FL  3(n  1) /  , Fe  , which is realized with three active switching states of (1,0,0), (0,1,0), and (0,0,1) in the active voltage hexagonal diagram as shown in Fig 3(b) 010 Medium triangle 110 011 100 101 001 FL  3(n  1) /  the area meets the condition of Fe =2 a) 010 Medium triangle 110 011 100 101 001 FL  3(n  1) /  the area meets the condition of Fe =1 b) Fig Medium triangle active voltage vector diagrams: a) active switching states for Fe  ( FL  3(n  1) /  ); b) active switching states for Fe  ( FL  3(n  1) /  ) n 1 V Xn  s jX ( X  A, B, C ) (5) j 1 V Xn can be decomposed into two components L X and s X : V Xn  LX  s X (6) where L X is a constant integer value that represents the base component of V Xn and s X is the active component of V Xn , which value can be or The average value of V Xn can be expressed in terms of  X - the average active component of s X in a carrier cycle as: v Xn  LX   X ; (0   X  1,  X  if v Xn  n  1) (7) The value of the base voltage and the active voltage can be In the space vector diagram with ZCMV of a five-level inverter as shown in Fig 2, considers for example the case when the tip of the reference voltage vector is enclosed by the medium triangle defined by tips of three vectors corresponding to normalized switching states of (3,2,1),(4,1,1),(4,2,0) The normalized state of the base voltage vector is determined as ( LA , LB , LC ) = (3,1,0) which yields FL  , and the medium triangle active voltage vector diagram is of the case in Fig 3(a) Using similar analysis, total 24 equilateral triangles defined by sets of three zero common mode vectors are obtained in Fig 2: twelve triangles meet the condition FL  FL1  (Fig 3(a)) and confine the light area; the others satisfy FL  FL1  (Fig 3(b)) and cover the shaded area 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 The PWM switching state sequence of the active voltage vectors in the ZCMV PWM control can be then grouped into two PWM patterns related to the total active voltage Fe as shown in Fig For three-phase outputs with the use of the two Patterns in Fig 4, Table I lists six possible mapping functions Different mapping functions result in different three-phase active switching sequences v*X (X  A, B, C) v*X n   Vdc v Xn  L X  int(vXn )  X  v Xn  LX Fe   A   B  C Fe   s1  s2  s1  s2 y Select Pattern I 0 s1 0 s2 d T1 T2 2 a) s1 11 11 0 s2 1 0 1 1 1 d T2 T1 2 T3 Active switching states and time diagram 0 Pattern I Fe   s1   s   d  T1 T2 2 b) T3 TABLE I POSSIBLE MAPPING FUNCTIONS AND MODULATING SIGNALS DETERMINATION Ad Ad A  s2 A  s1 A  s A  s1 Bd B  s2 B  s1 C  s2 C  s1 C  s2 C  s1 Cd Cd s1   B s2  C s1  C s2   B s1   A s1  C s2   A s1   A s1   B s2   A s2  C s2   B Since a commutation of the d-sequence in Fig happens simultaneously with one from both sequences s1 and s2 , it is sufficient to use two modulating voltages  s1,  s to deduce the switching time diagram of the proposed PWM method The modulating voltages 1 ,  are determined based on the mapping function as presented in Table I The switching time diagram can be derived accordingly by comparing 1 ,1   with a unit carrier as in Fig The duty cycles can be obtained as follows: T1   s Ts  T3   s1.Ts T  T  T  T s  and T1  (1   s1 ).Ts  T3  (1   s ).Ts T  T  T  T s  for Pattern I Pulse Generator III OUTPUT-CURRENT RIPPLE MINIMIZATION Fig Two Standardized virtual PWM patterns from the three zero common mode vectors Bd s A ,s B ,sC Fig Block diagram of the proposed PWM method to eliminate common-mode voltage Pattern II Fe   s1   s   d  B  s2 Select Pattern II Selected Mapping function T2 T1 2 B  s1 n Fe  (11) A Simplification of output current ripple analysis in multilevel inverter with ZCMV PWM control The approximate current ripples expression in the Nth carrier cycle can be described as follows [22]: ~ iX  L ( N 1) TS  (V XN  v *X )dt ; X  A, B, C (13) NT S where, V XN ( X  A, B, C ) is the output phase voltage measured from an output terminal to the load neutral N Under condition of zero CMV, the voltage VXN ( X  A, B, C) is identical to the pole voltage V XO and v *X ( X  A, B, C ) is equal to the average value of V XO which is denoted as v XO Equation (13) is further derived as: ~ iX  L ( N 1) TS  (V NT S XO  v XO )dt   X ; X  A, B, C L (14) The component  X in (14) is called the X-phase harmonic flux in the Nth carrier cycle Based on (3)-(7) as previously analyzed in Section II, V XO and v XO both consist of the same constant voltage component ( LX  (n  1) / 2)Vdc during a carrier cycle The Xphase harmonic flux can be then expressed in terms of the instantaneous active switching voltage Vdc s X and average active switching voltage Vdc  X as follows: for Pattern II (12) ( N 1) TS  X  Vdc  (s X   X )dt; X  A, B, C (15) NT S If we define v *X ( X  A, B, C ) as the reference load voltages, the proposed ZCMV PWM method is described as in Fig Eq (15) shows that the output-currents ripple analysis of a multilevel inverter under condition of ZCMV can be simplified to that of a two level inverter 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 Eq (15) can also be expressed in another form as: X  VdcN n 1 The normalized harmonic flux of the phase of double switching is described as follows: ( N 1) TS  (s X   X )dt; X  A, B, C (16) NT S where, VdcN  (n  1)Vdc It should be noted that inverters of equal maximum linear output voltage yield the same value of VdcN Based on the normalized (with VdcN ) value of  X in (16), comparative results of harmonic fluxes given by topologies of different levels are obtained B Proposed PWM strategy for reduced RMS output current ripple Vdc Vdc Vdc 0 dn ( d ).(t  t ( d )0 );  ( d ).(t ( d )1  t ( d )0 )  (1   d ).(t  t ( d )1 );   ( d ).(t  t ( d )3 ); (n  1)TS  ( d ).(t ( d )  t ( d )3 )  (1   d ).(t  t ( d ) ); ( ).(t  t ); ( d )6  d t ( d )0  t  t ( d )1 t ( d )1  t  t ( d ) t ( d )  t  t ( d ) (19) t ( d )  t  t ( d )5 t ( d )5  t  t ( d ) for pattern I, and: dn (1   d ).(t  t ( d )0 ); t ( d )0  t  t ( d )1  (1   d ).(t ( d )1  t ( d )0 )  ( d ).(t  t ( d )1 ); t ( d )1  t  t ( d )   t ( d )  t  t ( d ) (20) (1   d ).(t  t ( d )3 ); (n  1)TS  (1   d ).(t ( d )  t ( d )3 )  ( d ).(t  t ( d ) ); t ( d )  t  t ( d )5 (1   ).(t  t ); t ( d )5  t  t ( d ) d ( d )6  for pattern II t (s1)0 t (s1)1 t (s1)2 t (s1)3 t (s1)4 t (s2)0 t (s2)1 The mean-square values of the harmonic fluxes (over one carrier cycle) corresponding to the s1 , s2 , d sequences are determined as: t (s2)3 t (s2)4 b) a) Vdc Vdc Vdc t (s2)2 0 Vdc Vdc 2s1nrms   t (d)0 t (d)1 t (d)2 t (d)3 c) t (d)4 t (d)5 t (d)6 t (d)0 t (d)1 t (d)2 t (d)3 s n  rms t (d)4 t (d)5 t (d)6 Considering the generalized PWM patterns described in Fig 4, four types of active switching voltage waveform with their corresponding harmonic fluxes can be classified as in Fig For both cases of the generalized switching pattern in Fig 4, the active switching voltage waveform corresponding to the output phase which is mapped to the s1 sequence is shown in Fig 6(a) Since the switching frequency is much higher than the reference, the average switching voltages during one carrier cycle can be assumed to be constants Solving (16), the normalized (with VdcN Ts ) harmonic fluxes corresponding to the s1 , s sequences are described, respectively, as: s n  TS t( s1) TS  s 1n 2dnrms  TS dt (21) dt (22) t( s1) t( s ) TS  s 2n t( s ) d) Fig Harmonic flux trajectories corresponding to phase of a) s 1- sequence b) s2- sequence c) d -sequence (Pattern I) and d) d -sequence (Pattern II) s1n TS t( d ) TS  dn (23) dt t( d ) Using (21)-(22) with s1n , s n expressed in (17)-(18) , and Fig taken into account, 2s1nrms , 2s nrms can be obtained as: 2s1nrms  12(n  1) 2s 2n  rms   s21.(1   s1 ) 12(n  1)  s22 (1   s ) (24) (25) Similarly, the value of  dnrms for pattern I and pattern II can be determined, respectively, by substituting  d n deduced from (19) and (20) into (23) The simple form of 2dnrms is finally obtained as: ( s1 ).(t  t( s1) ); t( s1)  t  t( s1)1   (1  1 ).(t  t( s1) ); t( s1)1  t  t( s1) (n  1)TS   s1.(t  t( s1) ); t( s1)  t  t( s1)  (17) (1   s ).(t  t( s ) ); t( s )  t  t( s )1    ( ).(t  t( s1) ); t( s )1  t  t( s ) (n  1)TS  (1   s ).(t  t( s ) ); t( s )  t  t( s ) (18) 2dnrms  2dnrms   ( s21   s22   s1. s ) d 12(n  1) 12(n  1) for Pattern I (26) (1   d ) ((1   s1 )  (1   s )  (1   s1 ).(1   s )) 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information for Pattern II (27) This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 The mean-squared normalized harmonic flux of X phase (X=A,B,C) is defined as follows: 2s1nrms if X  s1  FX  2s nrms if X  s2 ; X  A, B, C 2  dnrms if X  d (3  2.( A   C )   A  C ) in (34) are always be negative As a result, the conditions expressed in (34) are further reduced to the simplest form as:  A  Max( A ,  B , C ) (28) For the pattern II, the condition expressed in (33) leads to: The total mean-squared normalized harmonic flux of three phases (over one carrier cycle) is expressed based on (28) as: F  FA  FB  FC (29)  A  Min( A , B ,C ) where the role of sequences s1 , s are altered Therefore, the RMS current ripple can be minimized by selecting a phase of double pulses switching so that the resulting F is at a minimum define F ( Ad ) , F ( Bd ) and F ( Cd ) the values of F corresponding to three cases of A  d , B  d and C  d , respectively By using (24)-(29) and Table I, the values of F ( X d ) , X  A, B, C for Pattern I are obtained as: F ( Ad )  12(n  1) ( B2 (1   B )   C2 (1   C )   A2 ( B2   C2   B  C )) (30) F ( Bd )  ( A2 (1   A )2  C2 (1  C )2   B2 ( A2  C2   A.C )) 12(n  1)2 (31) F (C d )  12(n  1) ( A2 (1   A )   B2 (1   B )   C2 ( A2   B2   A  B )) (32) The mapping rule ( A  d ) is selected when the value of (36) Similarly, the conditions of using the mapping rules ( B  d ) ,( C  d ) are derived, respectively, as: The problem of output current ripple minimization can be solved by finding an available three-phase switching sequence that is corresponding to the minimum value of the function F in (29) in each carrier cycle As described in Table I, there are six possible mapping functions that decide the three-phase switching sequence However, it can be concluded from (24) and (25) that the sum ( 2s1nrms  2s nrms ) is the same in the case We (35)  B  Max ( A , B ,C ) for Pattern I   B  Min( A , B ,C ) for Pattern II  C  Max ( A , B , C ) for Pattern I   C  Min( A , B , C ) for Pattern II (37) (38) The conditions expressed in (35)-(38) divide the two medium triangles in Fig into three separate regions each of which is designed with a different mapping function As previously described in (16), the ripple analysis of the PWM method using three nearest ZCMV vectors can be simplified to the ripple analysis of a two-level inverter defined by the two medium triangles in Fig Thus, the mapping algorithm designed for the whole vector diagram of the multilevel inverter can be derived based on Fig For example, the space vector diagram with the proposed mapping technique for minimizing the output current ripple of a five-level inverter is shown in Fig It should be noted that each separate region in the medium triangle defines the phase of double pulse distribution and the two other phases each of which can be set arbitrarily to the s1 or s2 sequence If one mapping rule in Table I is utilized during active time of one region, there is no additional commutations between two subsequent carrier cycles However, at the transition between two separate regions when the phase of double pulse is changed, additional commutations may arise The s1 or s2 sequence design is then constrained to the condition of minimized additional commutations caused by region transitions F ( Ad ) satisfies: F ( Ad )  min(F ( X d ) ); X  A, B, C (33) Ad B 010 By mean of (30)-(32), solving (33) leads to the following conditions: ( A   B ).(3  2.( A   B )   A  B )  (34)  ( A   C ).(3  2.( A   C )   A  C )  110 the components (3  2.( A   B )   A  B ) and 010 Bd 110 Cd 100 011 101 001 A Cd A 011 100 101 001 C C Since   X ( X  A, B, C)  and  A   B   C  for Pattern I, Ad B Bd FL  3(n  1) /  a) FL  3(n  1) /  b) Fig Proposed double pulse mapping regions for reducing output current ripple for a) Pattern I, and b) Pattern II 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1  A ,  B , C b axis 040 042 044 033 132 013 024 014 004 203 103 104 303 204 yes no Pattern I yes  A  MX Ad Ad  axis 411 400 a axis 401 402 302 yes  A  MN 410 301 312 Pattern II 420 311 202  A   B  C  310 321 212 213 430 320 211 222 113 114 220 221 112 440 330 230 121 123 340 231 122 022 023 034 131 031 032 043 130 141 MN  Min( A ,  B , C ) MX  Max( A ,  B , C ) 240 140 041  axis no no yes  B  MN yes  B  MX Bd Bd no no C  MN C  MX Cd Cd 403 a) determination of phase of double pulses 304 404 c axis Fig Illustration of the proposed double pulse mapping algorithm applied to the whole space vector diagram the five-level inverter  new zone( A  d ) sB  yes no Based on (35)-(38) and Figs.7 and 8, a simple mapping algorithm for ZCMV PWM with minimized output current ripple is proposed as shown in Fig The flow diagram in Fig 9(a) is utilized to determine the active regions of the medium triangles in Fig Figure 9(b) specifically describes the control algorithm to minimize the additional commutations at the instant of transition to the new active region of ( A  d ) The design of the s1 and s2 sequence is based on information of the current normalized state of the three-phase active voltages (sA,sB,sC) and phase of double pulses in the old region The rule is set as ( B  s2 , C  s1 ) and ( B  s1 , C  s2 ) when the active voltages are (sB=1, sC=0) and ( sB=0, sC=1), respectively; in this case, no additional commutations are required However, when the active voltages are (sB=0, sC=0) or ( sB=1, sC=1), an additional commutation is required regardless of the s1 and s2 sequence design; in this case, the phase of double pulse in the previous region is selected for non-commutation in order to distribute the switching stress between the two phases In cases with the transitions to the new regions of B  d and C  d , s1,s2 sequences are designed in a similar way as for the case of transition to the new region A  d The proposed ZCMV PWM scheme with reduced output current ripple is obtained by utilizing mapping results in Fig as inputs to the block diagram of ZCMV PWM in Fig The online algorithm is simple and can be implemented on a realtime microprocessor with small computational burden The maximum computations needed for implementation of the proposed algorithm are multiplications, additions, subtractions, int() operations and 16 comparisons The measured execution time of the algorithm implemented on a DSP28335 processor is less than 10 s sC  yes old zone : B  d sC  B  s2 , C  s1 no yes B  s1 , C  s2 no yes old zone : B  d no yes no B  s1 , C  s2 B  s2 , C  s1 b) s1 and s2 sequence design in case the transition to new zone of ( A  d ) Fig Block diagram of the proposed mapping algorithm for reduced RMS current ripple C Normalized harmonic flux evaluation In theoretical analysis, the normalized harmonic flux over the full fundamental cycle (of A-phase, for example) is evaluated as follows:  An  rmsF     F ( )d A (39) where,   2f ot , f o is the output fundamental frequency The function FA ( ) in (39) is calculated using (28) It can be seen that FA ( ) is dependent on the mapping algorithm of each PWM method For the proposed ZCMV PWM method, the designed mapping algorithm is determined as in Fig The normalized harmonic flux in (39) is evaluated over the entire range of the modulation index for the proposed PWM method and two existing PWM methods that are based on the same standardized patterns [17] These two existing ZCMV PWM methods include the Switching loss optimizing PWM (SLO PWM) and the Voltage-Based Mapping PWM (VBM PWM) It has been shown in [17] that characteristic of the SLO PWM corresponding to   is identical to one obtained by the VBM PWM In this paper, comparative results of the evaluated normalized harmonic flux with those PWM methods would be shown to highlight the improved performance of the proposed PWM in RMS current ripple reduction 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 a) Three-level NPC inverter a) Three-level NPC inverter b) Five-level cascaded inverter b) Five-level cascaded inverter Fig 10 Normalized RMS harmonic flux with the SLO PWM method of the three-level NPC inverter and the five-level cascaded inverter For a given n-level inverter, the normalized harmonic flux with the proposed PWM method is only dependent on the modulation index m, while one with the SLO PWM is dependent on both m and  The characteristics of the normalized RMS harmonic flux with SLO PWM method, corresponding to the three-level inverter and the five-level inverter, are illustrated in Fig 10 (a) and Fig 10(b), respectively The normalized RMS harmonic flux characteristic of the proposed PWM and some slices of the characteristic with the SLO PWM in Fig 10(a) are shown in Fig 11(a), for the three-level inverter A similar comparison is shown in Fig 11(b) for the five-level inverter As observed from each comparison, the normalized harmonic flux characteristic of the SLO PWM corresponding to   0o is identical to one obtained by the VBM PWM method It can be seen that the proposed PWM yields the optimum curves in both comparisons For the three-level inverter, the normalized harmonic flux characteristic of the proposed PWM is nearly identical to one obtained by the SLO PWM at   90o in the region of (0 - 0.5) of the modulation index In the region of m higher than 0.5, the proposed PWM method yields better performance in the RMS harmonic flux, as compared to the SLO PWM pertaining to all selected slices For the five-level inverter, the normalized RMS harmonic flux characteristic of the proposed PWM method is nearly identical to the slices of   0o and   90o , respectively, in the regions of (0.45 - 0.53) and (0 - 0.25, 0.63 -0.69) of the modulation index, while is significantly lower than all selected slices in other regions Fig 11 The Normalized RMS harmonic flux characteristics with the VBM PWM method (1), the SLO PWM method pertaining to different phase displacements (2) and the proposed PWM method (3) of the threelevel NPC inverter and the five-level cascaded inverter D Switching loss In [20], the average value of the local (per carrier cycle) switching loss over the fundamental (for instance, for phase A) can be calculated: Pswave  Vdc (ton  toff ) 2 2Ts 2 f iA ( )d (40) where, t on and t o ff represent the turn-on and turn-off times of the switching devices, respectively, and f iA ( ) is the switching current function, the instantaneous value of which is defined as a product of the number of commutations on the Aphase in a switching period and the absolute value of its corresponding current i A ( ) 2 if A  d f iA ( )  k i A ( ) ; k   1 else (41) The switching loss function (SLF) is defined as: SLF  Pswave P0 (42) where, P0 is the maximum value of the switching loss attainable for the defined load currents The Switching Loss Function (SLF) of the proposed PWM is dependent on both the modulation index and the phase 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 displacement The SLF surfaces of the proposed PWM method for the three-level inverter and the five-level inverter are shown in Fig 12(a) and Fig 12(b), respectively Comparisons of several slices of the SLF with the proposed PWM and the two SLF characteristics pertaining to the VBM PWM and the SLO PWM, are shown in Fig 13(a) and Fig 13(b) for the three-level inverter and the five-level inverter, respectively In both comparisons, the SLF corresponding to the SLO PWM is a minimum constant value of 0.756 [17], while the characteristic corresponding to the VBM PWM and those pertaining to the proposed PWM with different displacements are varied in the range (0.756 - 1) depending on the modulation index IV SIMULATION AND EXPERIMENTAL RESULTS A SIMULATION RESULTS In order to confirm the analytical evaluation obtained for the normalized RMS harmonic flux of the proposed PWM method as well as of other existing PWM methods in [17], numerical evaluation based on the simulated data is performed The output frequency is kept at 50 Hz while the modulation index is increased from with step size of 0.05 The switching frequency is set to kHz The DC-link voltages are set to Vdc =311 V for the three-level NPC inverter, and to Vdc =155.5 V for the five-level cascaded inverter, so that the maximum output line voltage of both topologies in the linear range of the ZCMV PWM control is 380V RMS Figs 14(a) and 14(b) present the normalized RMS harmonic flux characteristics pertaining to the three ZCMV PWMs of the three-level NPC inverter and the five-level cascaded inverter, respectively The comparisons show good agreement between the numerical results and the analytical results evaluated in Fig 11 a) Three-level NPC inverter a) Three-level NPC inverter b) Five-level cascaded inverter Fig 12 SLF characteristic of the proposed PWM method of the threelevel NPC inverter and the five-level cascaded inverter a) Three-level NPC inverter b) Five-level cascaded inverter Fig 13 Slices of the SLF function of the proposed PWM method (3) versus SLF characteristics of the VBM PWM method (1) and SLO PWM method (2) of the three-level NPC inverter and the five-level cascaded inverter THDvL  142.33% WTHDvL  1.18% a) VBM PWM b) Five-level cascaded inverter Fig 14 The normalized RMS harmonic flux characteristics pertaining to the VBM PWM method (1), the SLO PWM method with different phase displacements (2) and the proposed PWM method (3) of the three-level NPC inverter and the five-level cascaded inverter THDvL  142.03% THDvL  142.07% WTHDvL  1.02% WTHDvL  1.03% b) SLO PWM (  82 o ) c) Proposed PWM Fig 15 Output line voltage spectra of the three-level NPC inverter with the three ZCMV PWM methods for m = 0.346 at 20Hz 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 THDvL 10  49.92% WTHDvL  1.02% THDvL  50.18% THDvL WTHDvL  1.03%  50.03% WTHDvL  0.97% a) VBM PWM b) SLO PWM (  82 o ) c) Proposed PWM Fig 16 Output line voltage spectra of the three-level NPC inverter with the three ZCMV PWM methods for m = 0.866 at 50Hz THDvL  74.21% WTHDvL  0.59% THDvL  74.11% THDvL  74.15% WTHDvL  0.52% WTHDvL  0.58% a) VBM PWM b) SLO PWM (  82 o ) c) Proposed PWM Fig 17 Output line voltage spectra of the five-level cascaded inverter with the three ZCMV PWM methods for m = 0.346 at 20Hz THDvL  26.06% WTHDvL  0.51% THDvL  26.12% THDvL  26.08% WTHDvL  0.48% WTHDvL  0.53% a) VBM PWM c) Proposed PWM b) SLO PWM (  82 o ) Fig 18 Output line voltage spectra of the five-level cascaded inverter with the three ZCMV PWM methods for m = 0.866 at 50Hz Fig 15 and Fig 16 show the line voltage spectra of the three-level NPC inverter with the three ZCMV PWMs, corresponding to cases of (m=0.346, fo= 20Hz) and (m=0.866, fo= 50Hz) The designed phase displacements for the SLO PWM control are set at 82 o and 84o , respectively, in cases of fo = 20Hz and fo =50Hz, similar to the measured phase displacements in the later experiment of V/f induction motor control As seen from the line voltage harmonic spectra in Figs 15(a)-15(c) of the three-level NPC inverter, the harmonic component magnitudes in the sideband harmonics around kHz with the proposed PWM are slightly lower than those with the SLO PWM, while are significantly reduced as compared to those with the VBM PWM Figs 16(a)-16(c) shows reduced harmonic component magnitudes of around kHz with the proposed PWM over both of the VBM PWM and SLO PWM Similar comparisons are performed for a fivelevel cascaded inverter as shown in Figs 17-18 Similar to the case of the three-level NPC inverter, the harmonic component magnitudes around kHz with the proposed PWM method are substantially lower than those of the two other ZCMV PWM methods in both comparisons The THD and WTHD values of the output line voltage are defined, respectively, as in [25]: THDVL  WTHDVL  VLfund VLfund  V Ln (43) n2  ( n2 VLn ) n (44) where VLfu n d and VLn are, respectively, the RMS value of the fundamental component and the RMS value of the n th harmonic component of the output line voltage In order to analyze the THD of the current with no dependence on the load parameters, the WTHD factor of the output line voltage in (44) can be utilized In Figs 15-18, THDs and WTHDs of the output line voltage of the three-level NPC inverter and five-level cascaded inverter with the three 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 ZCMV PWM methods are also provided All THDs and WTHDs are analyzed up to the frequency of 20 kHz It is seen that, while differences between the THDs pertaining to the three ZCMV PWM methods are almost negligible in each comparison, there has been considerable improvement in the WTHD performance with the proposed PWM over the two ZCMV PWM methods in [17] 11 V EXPERIMENTAL VERIFICATION The proposed ZCMV PWM method is validated on a KVA five-level cascaded inverter topology fed HP 380 V-50 Hz delta-connected induction motor Each H-Bridge is made up of IGBTs using FGL-60N100-BNTD The DC voltage on each H-Bridge is held constant at 155.5 V so that the maximum output line voltage of the ZCMV PWM is 380V (RMS) The rating of each DC-link capacitor used for the experimental setup is 6800 µF In the algorithm for switching loss optimization, three additional Hall sensors LA55-P are used to measure the output currents All three PWM control methods are implemented on the TMS320F28335 DSP microcontroller A three-phase induction motor with the following parameters: stator resistance RS  8.68 , rotor resistance Rr  8.3 , stator leakage inductance Lls  17.5mH , rotor leakage inductance Llr  17.5mH , and magnetizing a) Three-level NPC inverter inductance Lm  0.862H has been used The switching frequency is kHz and the induction motor is operated with constant V/f control The V/f ratio is fixed so that the rated line voltage of 380V (RMS) is corresponding to the rated frequency of 50 Hz (V) CMV 50 25 -25 -50 FFT of CMV b) Five-level cascaded inverter 1.5 0.5 0 15 20 10 25 30 35 15 40 (kHz) 25 (ms) 20 a) m = 0.346, f o  20Hz Fig 19 The WTHD factor characteristics pertaining to the VBM PWM method (1), the SLO PWM method with different phase displacements (2) and the proposed PWM method (3) of the three-level NPC inverter and the five-level cascaded inverter CMV (V) 50 25 -25 -50 FFT of CMV Fig 19(a) presents the WTHD factor characteristics of the output line voltage obtained from simulated data of the threelevel NPC inverter due to the VBM PWM method, the SLO PWM method corresponding to different phase displacements, and the proposed PWM method The WTHD factor characteristics are analyzed to the maximum modulation index of 0.866, at an output frequency of 50 Hz Similar comparisons of the WTHD factor with the three PWM methods of the five-level cascaded inverter are shown in Fig 19(b) For better illustration, regions of the remarkable improvements ((0.5-0.866) for the three-level NPC inverter and (0.25-0.45) for the five-level cascaded inverter) are magnified In both comparisons, it is seen that the proposed PWM leads to improved line voltage WTHD characteristics over the VBM PWM and SLO PWM in almost the entire region of the modulation index 10 1.5 0.5 0 5 10 15 10 20 25 30 35 15 20 40 (kHz) 25 (ms) b) m = 0.866, f o  50Hz Fig 20 Experimental CMV waveforms and CMV harmonic spectra with the proposed ZCMV PWM method for two cases of a) m = 0.346, f o  20Hz and b) m = 0.866, f o  50Hz Fig 20(a) presents the CMV waveform and its corresponding harmonic spectrum with the proposed ZCMV PWM method, at modulation index of 0.346 and output frequency of 20 Hz The same quantities are given in Fig 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 12 20(b) corresponding to the rated output frequency of the induction motor It is seen that the CMV with the proposed ZCMV PWM is reduced considerably, compared to those with conventional PWM methods [5],[6] The spikes in CMV waveforms, as observed from Fig 20, are due to the effect of double switching which has been referred in [23],[38] These high frequency spikes are still the cause of EMI and bearing current issues as proved in [2-3],[23],[38] There have been some feasible approaches to reduce these CMV spikes that may be taken into consideration [13], [15] The techniques include shifting dead-time of switching devices in different phases [13], and incorporating hysteresis current controllers into the control algorithm [15] Fig 21(a) shows the experimental waveform of the line voltage with the proposed PWM method when the motor operates at (m  0.346, f o  20Hz ) The same quantity is shown in Fig 21(b) when the motor operates at (m  0.866, f o  50Hz ) 225 200 225 200 175 175 175 150 150 150 125 125 125 100 75 50 Voltage (V) 225 200 Voltage (V) Voltage (V) a) m = 0.346 at 20 Hz b) m = 0.866 at 50 Hz Fig 21 Experimental waveforms of the line voltage with proposed PWM method (X axis: 10 ms/div, Y axis: 200 V/div) Comparative harmonic spectra of the line voltage with the VBM PWM method, the SLO PWM method and the proposed PWM method are shown in Fig 22 and Fig 23 for the cases of (m  0.346, f o  20Hz ) and (m  0.866, f o  50Hz ) ,respectively It can be observed that the experimental harmonic spectra in Figs 22-23 are in close agreement with the corresponding spectra, obtained by simulation of the five-level cascaded inverter, shown in Figs 17-18 Fig 24(a) shows the experimental phase current with the VBM PWM method for modulation index of 0.346 and output frequency of 20 Hz The instantaneous current ripple is obtained by subtracting the fundamental current component from the stator current A low pass filter, which cut-off frequency of 30 kHz, is applied in post-processing of the current ripple waveform in order to remove the switching noises The current ripple waveform is then shown in Fig 24(b) For comparison, the phase current and phase current ripple with the SLO PWM method and those with the proposed PWM method are shown in Figs 25 and 26, respectively The RMS current ripple values over a fundamental period can be calculated based on the obtained current ripple waveforms Fig 27 presents the RMS current ripple characteristics of the measured stator current corresponding to the VBM PWM, SLO PWM and the proposed PWM The motor is operated with constant V/f ratio and step frequency of Hz It can be seen that the proposed PWM method leads to a great improvement of the RMS current ripple over the two other PWM methods in a wide range of the output frequency 100 75 50 100 75 50 25 25 25 0 0 Frequency (kHz) Frequency (kHz) Frequency (kHz) 675 600 675 600 525 525 525 450 450 450 375 375 375 300 225 150 Voltage (V) 675 600 Voltage (V) Voltage (V) a) VBM PWM b) SLO PWM (  82 o ) c) Proposed PWM Fig 22 Experimental output line voltage harmonic spectra of the five-level cascaded inverter with the three ZCMV PWM methods for m = 0.346 at 20Hz 300 225 150 300 225 150 75 75 75 0 0 Frequency (kHz) Frequency (kHz) Frequency (kHz) a) VBM PWM b) SLO PWM (  82 o ) c) Proposed PWM Fig 23 Experimental output line voltage harmonic spectra of the five-level cascaded inverter with the three ZCMV PWM methods for m = 0.866 at 50Hz 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 13 a) Phase current ( Y axis: 1A/div, X axis: 10ms/div) Fig 27 Experimental RMS current ripple characteristics corresponding to the VBM PWM (1), the SLO PWM (2) and the proposed PWM method (3) (the motor operated with constant V/f ratio) b) Phase current ripple (RMS current ripple  Irms = 0.127A) Fig 24 Experimental waveforms of phase current and phase current ripple with the VBM PWM for m= 0.346 at 20 Hz a) Phase current (Y axis: 1A/div, X axis: 10ms/div) b) Phase current ripple (RMS current ripple In Section IV-B, the WTHD has been used as a loadindependent factor to present the THD factor of the current In the experiment of a constant V/f induction motor drive, the THD factor can be obtained directly from the measured stator current Fig 28 presents the experimental current THD characteristics pertaining to the three ZCMV PWM methods It is observed that there is a close agreement between the experimental THD factor characteristics and RMS current ripple characteristics obtained in Fig 27 The current THD due to the proposed ZCMV PWM is substantially lower than those due to the VBM PWM and SLO PWM over a wide frequency range The best reduction in the THD is from 12.61% with the SLO PWM method to 10.62% with the proposed PWM method at output frequency of 30 Hz The values of the RMS current ripple and the current THD pertaining to the three ZCMV PWM methods at some specific frequencies are also given in Table II to highlight the superior performance in both RMS current ripple and current THD of the proposed PWM method  Irms = 0.126A) Fig 25 Experimental waveforms of phase current and phase current ripple with the SLO PWM for m= 0.346 at 20 Hz Fig 28 Experimental current THD characteristics corresponding to the VBM PWM (1), the SLO PWM (2) and the proposed PWM method (3) (the motor operated with constant V/f ratio) a) Phase current (Y axis: 1A/div, X axis: 10ms/div) TABLE II EXPERIMENTAL CURRENT RIPPLE AND CURRENT THD COMPARISONS BETWEEN THE VBM PWM, THE SLO PWM AND THE PROPOSED PWM FOR A V/f CONTROLLED INDUCTION MOTOR DRIVE FED BY A FIVE-LEVEL CASCADED INVERTER fo b) Phase current ripple (RMS current ripple  Irms = 0.11A) Fig 26 Experimental waveforms of phase current and phase current ripple with the proposed PWM for m= 0.346 at 20 Hz RMS current ripple [A] THD [%] [Hz] 10 20 30 40 50 VBM PWM 0.123 0.127 0.088 0.125 0.108 SLO PWM 0.111 0.126 0.103 0.118 0.109 Proposed PWM 0.11 0.11 0.087 0.117 0.1 VBM PWM 16.19 15.79 10.82 15.11 13.16 SLO PWM 14.41 15.52 12.61 14.3 13.17 Proposed PWM 14.25 13.83 10.62 14.3 12.12 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information This article has been accepted for publication in a future issue of this journal, but has not been fully edited Content may change prior to final publication Citation information: DOI 10.1109/TPEL.2015.2489560, IEEE Transactions on Power Electronics TPEL-Reg-2015-04-0539.R1 The proposed PWM method is investigated under condition of balanced DC voltage sources It is applicable for cascaded H-bridge inverters [14-17] or NPC inverters with modified structures as in [6],[11] For the cascaded inverters, owing to the advantage of the modulator structure in which each DC voltage is supplied by one rectifier through an isolated transformer, variation of each DC-link voltage is negligible For the NPC topologies, for example, the three-level NPC inverter, the utilization of two isolated DC voltage sources fed by two diode rectifier front-ends [6] or of an additional circuitry as in [11] would help solve the problem of neutral point voltage fluctuations For other multilevel NPC inverter structures, if the DC voltage imbalance is problematical, the ZCMV PWM to reduce current ripple should take into account the DC voltage balancing as well The investigation, however, requires further study and analysis VI CONCLUSION This paper proposes a novel carrier-based ZCMV PWM strategy for multi-level inverters using the principle of the three zero common mode vectors The resultant PWM patterns made up of switching states of the three zero common mode vectors have a minimum number of commutations It has been shown in this paper that the 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Vietnam, in 1964 He received the M.S and PhD degrees in electrical engineering from University of West Bohemia, the Czech Republic in 1988 and 1991, respectively Since 1992, he has been with Department of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology, Vietnam, where he is currently an associate professor He was with KAIST as a post-doc fellow for six months in 2001 and a visiting professor for a year in 20032004 His research interests include modeling and control of switching power supplies, ac motor drives, active power filters, and PWM techniques for power converters He is a member of the Institute of Electrical and Electronics Engineers (IEEE) Nadipuram (Ram) R Prasad is a tenured, Associate Professor in the Klipsch School of Electrical and Computer Engineering Department at New Mexico State University He is also the Director of the Rio Grande Institute for Soft Computing (RioSoft) at New Mexico State University and RioRoboLab, a NASA Ames funded Advanced Robotics Laboratory He is a Senior Research Fellow for SPAWAR Systems Center of the Office of Naval Research, and is a recipient of several NASA fellowships including the prestigious NASA Administrator’s Fellowship in 2001-2002 More recently, his contributions are in energy harvesting, specifically in the area of low-head hydropower generation Dr Prasad’s research interests are in neural networks, fuzzy logic based systems, and evolutionary computation platforms Dr Prasad has authored and co-authored over 150 research publications in journals and conference proceedings and is the co-author of three books on fuzzy and neural control 0885-8993 (c) 2015 IEEE Personal use is permitted, but republication/redistribution requires IEEE permission See http://www.ieee.org/publications_standards/publications/rights/index.html for more information  ... Space Vector Modulation to Reduce Common-Mode Voltage for Multilevel Inverter ‘, IEEE Trans On Industrial Electronics, 2010 A K Gupta and A M Khambadkone, “A space vector modulation scheme to reduce. .. post-processing of the current ripple waveform in order to remove the switching noises The current ripple waveform is then shown in Fig 24(b) For comparison, the phase current and phase current ripple with... Experimental waveforms of phase current and phase current ripple with the VBM PWM for m= 0.346 at 20 Hz a) Phase current (Y axis: 1A/div, X axis: 10ms/div) b) Phase current ripple (RMS current ripple In