A Reduced Switching Loss PWM Strategy to Eliminate Common Mode Voltage In Multilevel Inverters Nho-Van Ng., Tam Ng Khanh Tu, Hai Quach Thanh Hong-Hee Lee Department of Electrical and Electronics Engineering Hochiminh City University of Technology Hochiminh City, Vietnam nvnho@hcmut.edu.vn Department of Electrical Engineering University of Ulsan Ulsan, Korea hhlee@ulsan.mail.ac.kr conventional Discontinuous PWM technique (DPWM) [9] In order to attain reduced common mode voltage at a high modulation index, a new DPWM pattern from three nonnearest vectors was proposed [10] In another work, a tradeoff in the THD factor and switching loss for reducing the number of common mode current pulses (dv/dt) could be managed with a change in sequence of the non-nearest vectors [11] Abstract— This paper introduces a novel PWM technique to eliminate common mode voltage (CMV) in multilevel inverters using the three zero common mode vectors Similarly, as in conventional PWM for multilevel inverters, this PWM can be properly depicted in an active two-level voltage inverter With the help of two standardized PWM patterns, the characteristics of the PWM process, as a switching time diagram and switching state sequence, can be fully explored in that active inverter Due to the existence of an unequal number of commutations of three-phases in each sampling period, the optimization of the switching loss is achieved by a proposed current mapping algorithm The switching loss reduction can be up to 25% as compared to the same PWM technique with non-optimized algorithms The theoretical analysis is verified by simulation and experimental results I In order to avoid the common mode influence, in another trend, researchers have tried to fully eliminate the common mode voltage The idea of complete CMV elimination that restricts the inverter switching states to those states of zero CMV was first proposed by K Ratnayake and Y Murai in [12] for a three level NPC inverter In [13], the modulation of selected zero CMV states has been applied to the three level NPC using both carrier based and space vector modulation scheme Similar to [12], the method utilizes three zero CMV vectors in three level NPC inverter to synthesize the reference output voltages However, the rule of distribution of these vectors in each switching sequence is not mentioned Furthermore, the symmetrical double sided pattern which consists up to twelve commutations causes a considerable switching loss INTRODUCTION In recent year, great progress has been made in the development of multilevel inverters in electric drives and other applications Two basic circuits are commonly used in practice: diode clamped multilevel inverters, cascaded multilevel inverters as shown in Fig Three main PWM schemes are commonly used are the space vector PWM, the carrier-based PWM, and the selective harmonic elimination PWM techniques [1-3] It has been well-known that the common-mode voltages are associated to the excessive bearing currents which may cause premature motor bearing failure and electromagnetic interference [4-6] There have been a number of approaches to cope with the CMV issue including the use of extra hardware with passive and/or active devices However, the extra hardware utilization causes a significant increase in the system’s volume or much more complex control methods The multi-level inverters have high a number of switching states that can either reduce or eliminate the CMV Based on this advantage, many researches for the CMV mitigation have been made using multi-level inverters [7-8] C SW2A SW1A vdc vdc SW3 A SW4 A O A vdc vdc vdc vdc SW2A B C vdc SW3A vdc vdc SW4 A O Fig Multilevel Inverter circuits: a) five-level Diode clamped inverter and b) five-level cascade inverter In partial PWM methods to eliminate common mode voltage, the output voltage can be obtained normally by a 978-1-4799-5776-7/14/$31.00 ©2014 IEEE B A SW1A vdc 219 and In this paper, a simple carrier based method to cope with this problem is presented Its main contributions are clarified in the following points: s1X ≤ s 2X ≤ ≤ s n−2X ≤ s n−1X ,X=A,B,C ( for diode clamp inverter topology) - As a general principle for an n-level inverter, all switching sequences and corresponding switching time diagrams will be derived from two generalized PWM patterns The two patterns represent switching state sequence of corresponding active two level inverter The algorithm to select the PWM pattern can be applied to arbitrary number of levels without losing the generality n −1 The component (∑ s jX )Vdc (X=A,B,C) in (3) is called j=1 n −1 the switching voltages We define VXn = ∑ s jX (*) as the j=1 normalized switching voltage which, for further analysis, can be used to represent VXO Relationship between VXn and VXO is described as - The number of commutations per sampling period are reduced to eight Besides, the switching state sequence is locally optimized within the standardized PWM patterns, which helps to reduce switching loss VXn = The experimental results obtained with five-level cascaded inverter are used for verifying the performance of the proposed PWM strategy II decomposed into VXn = LX + s X (5) two (6) components LX and sX : During a sampling period, L X is a constant integer A Voltage modeling of multilevel inverter and offset condition for eliminating common mode voltage value which represents the base component of VXn and s X is the active component of VXn which can be changed between and during a sampling time period Taking (5) and (6) into account, the equivalent circuit of the instantaneous voltage of VXO is derived as in Fig 2(a) ( LA , LB , LC ) is named as the normalized three phase base Due to the difference in structure of the diode clamped inverter and cascade inverter, as illustrated in Fig for five-level inverter, established rules of switching combinations for a same reference output voltage are completely different In this paper, the analytical process for the two topologies can be unified by a simple voltage modeling With selected neutral point ‘O’ and designated switches of A-phase represented as SW1A ,SW2A ,SW3A ,SW4A for the two topologies in Fig 1, the pole voltage vAO is generally determined as voltages and (s A ,s B ,sC ) the normalized three phase active voltages in Fig 2a If ξX is defined as the average active component of s X in a sampling period, the average value of VXn defined as v Xn can be derived as follows: (1) where s1A ,s 2A ,s3A ,s 4A represent the switching states of v Xn = LX + ξ X SW1A ,SW2A ,SW3A ,SW4A respectively, s1A is ‘1’ if SW1A is on otherwise its value is ‘0’ ; ≤ ξ X ≤ (7) and the equivalent circuit of the average voltage of VXO can now be described as in Fig 2(b) It should be noting that s1A ,s 2A ,s3A ,s 4A can be selected randomly in the five level cascaded inverter while are further restricted in five level diode clamp inverter due to the limit of its switching combinations The constraint is simply expressed as s1A ≤ s 2A ≤ s3A ≤ s 4A VXO n −1 + Vdc The normalized switching voltage VXn (*) can be PROPOSED PWM METHOD TO ELIMINATE COMMON MODE VOLTAGE VAO = (s1A + s 2A + s3A + s 4A ) Vdc − 2Vdc (4) Let define v*X (X=A,B,C) the reference output fundamental voltages, v Xn in (6) can also be expressed as v Xn = (2) v*X * + voff Vdc (8) * For an n-level inverter of the two topologies, (1) and (2) can be generalized as, X=A,B,C : (n−1) VXO = (s1X +s2X + +sn−2X +sn−1X )Vdc − Vdc (3) n−1 (n−1) = (∑sjX )Vdc − Vdc j=1 The offset voltage v off of the circuit in Fig 2(c), for any PWM method can be designed to have any value in the limits as: v0min = − 220 MIN MAX * ≤ voff ≤ v0max = (n −1) − Vdc Vdc (9) where MAX and MIN are the highest and the smallest of the three fundamental voltages (v*A1 , v*B1 , vC* ) and n is the number of levels It can be seen from (11) that under the condition of the eliminating CMV PWM control: f n = f ZCMV = 3(n − 1) / The equivalent circuit of the average voltage of VXO following (5),(8) is described in Fig 2c (13) For example, considering the cascaded five level inverter in Fig 3, among 125 possible combinations, there are 19 switching combinations which produce zero CMV All zero CMV vectors satisfy (13) with f n = With a normalized switching state of ZCMV described as (VAn ,VBn ,VCn ) = (4,1,1), for example, the pole leg voltages are derived using (5) as VAO = 2Vdc , VBO = − Vdc , VCO = −Vdc Fig a) Equivalent circuit of instantaneous three-leg voltages of nlevel voltage source inverter; b) Average voltages modeling of three-leg voltages; c) Average voltages modeling from reference fundamental voltage and offset voltage components; d) Total switching voltage and its components ( Fe = ξ A + ξ B + ξ C , FL = LA + LB + LC ) Fig Five-level space vector diagram with zero CMV state (bold letters) In case of the equivalent circuits described in terms of average voltages in a sampling period as shown in Fig 2(b) and Fig 2(c), with a note that (v*A1 + v*B1 + vC* ) = , the condition of zero average CMV results in: The offset for eliminating CMV v0 ff , ZCMV * v off = v off , ZCMV = ( n − 1) / The common mode voltage defined for n-level inverter in Fig is described as : Vcm V + VBO + VCO = AO Vcm = and the sum of the average values of VXn (X=A,B,C) defined as F = v An + vBn + vCn is obtained with the following value: (10) The instantaneous value of Vcm following derived as (VAn + VBn + VCn − 3(n −1) / 2).Vdc Fig 2(a) is F = FZCMV = FL + Fe = 3(n − 1) / (15) where FL and Fe are determined respectively as: (11) FL = L A + LB + LC Fe = ξ A + ξ B + ξ C ;; ≤ Fe ≤ The combinations of (VAO ,VBO ,VCO ) which not contribute any common-mode voltage, represent the zero CMV vectors in the vector diagram of n-level inverter which result in zero value of Vcm (16) (17) The functions F , FL , Fe determine respectively the total switching voltage, total base voltage and total active voltage as described in Fig 2(d) We define f n as f n = VAn + VBn + VCn ( 14) (12) 221 B Medium Triangle active voltage vector diagram of the Two-level active voltage Inverter under eliminating common mode voltage PWM control In space vector diagram of a multi-level inverter, a discrete vector can be decomposed into two components as follows: G G G VS = L+ s (18) G where L is the pointing vector formed by the three G phase base voltages and s is the active vector formed by the three phase active voltages in Fig 2(a) Following (18), any discrete vector in the space vector diagram of an n-level G JJG inverter can be represented by (L,s) Its worth noting that the three zero common mode vectors (ZCMV) in the space G vector diagram have the same base voltage vector L which tip locates at center of the equilateral medium triangle formed by tips of the three vectors A simple carrier based ZCMV PWM control method is established under the consideration of (6), (13) for instantaneous voltage modeling in Fig 2(a) and (7), (8), (14)-(17) for average voltage modeling in Fig 2(b), 2(c), 2(d) It has been shown that the function FL in (16) is determined by the base voltage vector which tip is located at the center of the active triangle and the function Fe is related to the active voltage vectors of the medium triangle vector diagram as illustrated in Fig A general analysis has been shown that, for an n-level inverter, the ZCMV condition confines the possible values of FL , Fe to those expressed as: FL = 3(n −1) / − 2; Fe = FL = 3(n −1) / −1; Fe = FL = 3(n −1) / ; Fe = (a) (b) (c) Fig.4: Medium triangle active voltage vector diagrams: a) switching states for Fe = 2(FL = 3(n−1) / − 2) and b) switching states for Fe =1(FL = 3(n−1) / −1) For space vector diagram with ZCMV of a five-level inverter as shown in Fig 3, 24 equilateral medium triangles defined by three zero common mode vectors can be found: twelve triangles, which corresponding base vectors meet the condition FL = FL1 = , confine the light area; the others, satisfy FL = FL2 = , cover the shaded area The value of the base voltage and the active voltage can be deduced from (20), (21): ⎧⎪ Int (vXn ) if if ⎩⎪ n − LX = ⎨ (ξ A , ξB , ξC ) = (v An − LA , vBn − LB , vCn − LC ) (20) (21) The values v Xn under the conditions of ZCMV are defined by (8) and (14) and Int (v Xn ) denotes a function that returns a nearest lower integer value of v Xn (19) C ZCMV PWM patterns and ZCMV PWM control algorithm The proposed CMV elimination PWM in multi-level inverters can be obtained by solving (19) With exception of case (19.c) related to several pivot vectors, the two remaining available values of FL , Fe are further limited to (19.a), (19.b) Based on the medium triangle active vector diagrams generalized for an n-level inverter as described in Fig 4, the PWM switching state sequence of the active voltage vectors in the ZCMV PWM control can be grouped into two PWM patterns related to the Fe values Fe = (19.a), the condition of Fe = will be realized with three active switching states as (1,1,0), (0,1,1) and (1,0,1) in the active voltage hexagonal diagram as illustrated in Fig 4(a) In case v Xn < n − ; ≤ LX ≤ n − v Xn = n − FL = 3(n − 1) / − and In case Fe = , the active switching state sequence forms PWM pattern as described in Fig 5(a) Two from three ABC phases are mapped to s1 and s2 that the s1 -level varies as 0-1-0 in a sampling period and the s2 -level varies as 1-0-1 in a sampling time period All of them have a single pulse waveform The remaining phase is mapped to the d-phase that the d-level will vary as 0-1-0-1-0 and has a double pulse waveform in a sampling time period Similar to the previous case, in case F = FL = 3(n −1) / −1 and (19.b), the condition of e Fe = will be realized with three active switching states as (1,0,0), (0,1,0) and (0,0,1) in the active voltage hexagonal diagram as in Fig 4(b) In case Fe = , the active switching state sequence corresponds to PWM pattern as described in Fig 5(b) Two from ABC phases are mapped to s1 and s2 that the s1 - 222 level varies as 0-1-0 in a sampling period and the s2 -level varies as 1-0-1 in a sampling time period All of them have a single pulse waveform The remaining phase is mapped to the d-phase that the d-level will vary as 1-0-1-0-1 and has a double pulse waveform in a sampling time period where ton and toff represent the turn-on and turn-off time of the switching devices respectively, and fiA (θ) is the switching current function which instantaneous value is defined as product of the number of commutations on Aphase in a switching period and the absolute value of its corresponding current i A (θ ) 1 ξ s1 − ξs ξ s1 (23) f iA (θ ) = k i A (θ ) − ξs The switching loss function (SLF) is defined as: 0 s1 0 s2 d s1 1 1 0 s2 1 0 1 d 1 1 T1 T2 2 a) 0 T1 T2 2 T2 T1 2 T3 Pattern I Fe = ξ s1 + ξ s + ξ d = b) SLF = When using the proposed PWM method with two standardized PWM patterns in Fig 5, the distribution of commutations in a switching period is unequal on each phase It can be seen that the d-sequence contains a double number of commutations compared to the other s1 ,s2 sequences The factor k is thus determined as follows: Pattern II Fe = ξ s1 + ξ s + ξ d = Fig 5: Two Standardized virtual PWM patterns from three-nearest vectors of zero common mode voltage Table I: Possible Mapping functions and modulating signals determination A→d A→d A → s1 A → s2 A → s1 A → s2 B → s1 B → s2 B→d B→d B → s2 B → s1 C → s2 C → s1 C → s2 C → s1 C→d C→d ξs1 = ξB ξs2 = ξC ξs1 = ξC ξs2 = ξ B ξs1 = ξ A ξs1 = ξC ξs1 = ξ A ξs2 = ξC ξs2 = ξ A ξs2 = ξ B ξs1 = ξ B ξs2 = ξA ⎧ ⎪2 if A → d k = ⎪⎨ ⎪ ⎪ ⎪ ⎩1 else The Mapping function, as described in Table I, can be altered between six possible cases so that an arbitrary output phase can be mapped into the d-sequence If all the selected Mapping functions satisfy the constraint that only output phase of minimum absolute current is mapped to the dsequence, the switching current function described in (23) will always be obtained with minimized value Hereby, the switching loss function in (24) can be optimized Based on this idea, a current-based Mapping PWM algorithm which optimizes the switching loss is proposed s1,s2 ,d three phases A,B,C will be mapped to sequence respectively Hence the three-phase active (s A,s B ,sC ) is switching sequence expressed as (0,0,1) → (1,0,0) → (0,1,0) → (1,0,0) → (0,0,1) If the mapping function, in another example, is selected as (A → s1,B → s2 ,C → d ) , the three-phase active switching will be (25) By substituting (25) into (23), it can be concluded that fiA (θ) equals double the absolute value of the corresponding phase current in the interval that the A-phase is mapped into the d-sequence (A → d) and equals the absolute value of the current in other cases For three phase outputs with the use of the two Patterns in Fig 5, six possible Mapping functions are listed in Table I Different Mapping functions result in different three phase active switching sequences For example, when using the Mapping function (A → d ,B → s1,C → s2 ) for the Pattern I, sequence → (0,1,0) (24) where P0 is the maximum value of the switching loss attainable for the defined load currents T2 T1 2 T3 Pswave P0 i A i B iC (0,1,0) → (0,0,1) → (1,0,0) → (0,0,1) k X = iX ; X = A, B,C mx = max( k A , k B , k C ) III md = mid( k A , k B , k C ) SWITCHING LOSSES OPTIMIZATION mn = min( k A , k B , k C ) The switching losses linearly increase with the magnitude of the commutating phase current The average value of the local (per carrier cycle) switching loss over the fundamental (for instance, for the phase A) can be calculated as [14]: k A = mn k B = mn y kB > k C y n kA > kC y kA > kB n (22) A → s1, B → d,C → s Selected Mapping function A → s , B → d,C → s1 n kC = mn A → d, B → s1,C → s A → d,B → s ,C → s1 n 2π Vdc (t on + t off ) Pswave = ∫ fiA (θ)d θ 2π 2Ts y n y A → s1, B → s2 ,C → d A → s2 ,B → s1 ,C → d Fig.5b- Block diagram of the proposed Current-Based Mapping PWM algorithm to optimize the switching loss 223 d s1 s2 s2 s1 d iABC d s1 s2 iA Im Im a) s1 d s2 s2 s1 d i s2 d s1 B d s2 s1 i s1 s2 d is necessary to determine the range of the switching loss function This can be done by an analysis of a so-called voltage-based mapping algorithm under different phase displacement factors The voltage-based mapping algorithm can be simply implemented by replacing iX (X = A,B,C) A B C C 00 with the reference output voltages v* X 1(X = A,B,C) as inputs of the flow diagram in Fig.5b mx, md , mn are then, respectively, the maximum, medium and minimum of the absolute values of v* X 1(X = A,B,C) The voltage-based mapping algorithm which operation following the waveforms of the reference output voltages is illustrated in Fig 7(a) Since the rule of switches distribution of the voltage-based mapping PWM is based on information of reference voltage (offline), the waveform of fiA (θ) is changed differently depending on the current phase displacement angle ϕ For example, three cases of phase displacement angle: ϕ= , ϕ = π / , ϕ = π / in Fig 7(b), 7(c), 7(d) will result in three different waveforms of fiA (θ) as shown in Fig 8(a),8(b),8(c) ωt -Im -Im π/6 fiA π/2 5π/6 7π/6 3π/2 11π/6 13π/6 15π/6 Im Im b) 00 ωt fiB Im Im 00 ωt fiC c) Im Im 00 ωt Fig 6: Current-based mapping PWM method (a) and switching current functions of three phase: (b) fiA (θ) (c) fiB (θ) (d) fiC (θ) In the proposed Mapping PWM algorithm with optimized switching loss, the feedback currents iA,iB ,iC are d v* X1(X=A,B,C) s2 s1 Vm utilized as inputs of the flow diagrams kX = iX (X = A,B,C) mx, md , mn are determined, respectively, as the maximum, medium and minimum of the absolute values of iA,iB ,iC The Mapping function is chosen so that the phase with minimum absolute current is mapped to the d-sequence The selected Mapping function is then utilized to complete the proposed PWM scheme of zero CMV a) s1 d s2 d s1 s2 v* B1 s2 s1 d s2 d d s2 s1 s1 v* C1 A B C s1 s2 d iA(ϕ=0) ωt π/6 π/2 5π/6 7π/6 3π/2 11π/6 13π/6 15π/6 Im b) -Im ωt ϕ=0 iA(ϕ=π/6) Im c) ωt -Im ϕ=π/6 iA(ϕ=π/2) Im d) ωt -Im ϕ=π/2 Fig 7: Voltage-based mapping PWM method with different current phase displacement b ϕ = c ϕ = π / d ϕ = π / π/6 f iA(ϕ = 0) a) the switching loss Pswave defined by (22): Vdc I m (ton + toff ) AOpt Ts 4π v* A1 -Vm Figure 6(a) illustrates the operation of the proposed current-based mapping method in Fig.5b following the feedback waveforms of the output currents By using (23), (25), the A-phase switching current function waveform fiA (θ) is derived as illustrated in Fig 6(b) Since the Aphase is set to the d-sequence during the interval that its current attains a minimum absolute value, the waveform of fiA (θ) always confines a minimized Ampere-second area regardless of the load displacement factor Hence the waveform fiA (θ) corresponds to a minimum value PswOpt of PswOpt = s1 s2 d 5π/6 7π/6 11π/6 13π/6 ωt ImIm 0 ωt f iA(ϕ=π/6) 2Im 2Im b) (26) Im Im 0 ωt f iA(ϕ=π/2) 2Im 2Im Aopt = − = 4.5359 c) Im Im 0 ωt Similarly, the optimized waveforms of the B and Cphase switching current functions are shown in Fig 6(c) and 6(d) respectively Fig 8: Waveforms of switching current function using voltage-based PWM method a ϕ = b ϕ = π / c ϕ = π / To evaluate the improvement of the switching loss when using the proposed Current-based Mapping PWM, it In the case ϕ= , the A-phase output current, as illustrated in Fig 7(b), is in phase with its corresponding 224 reference voltage v*A1 As can be seen from Fig 8(a), the waveform of the A-phase switching current function is identical to one obtained by using the Current-based Mapping algorithm in Fig 6(b) The switching loss Pswave is thus corresponding to the minimum value PswOpt frequency f o is selected as 50 Hz The frequency of the triangle carrier waveform f s is 2.31 kHz In online algorithm for switching loss optimization, two additional Hall sensors LA55-P are used to measure two output currents Since the three phase load is balanced, the third current can be deduced from the two measured currents For comparison, the conventional sinusoidal PWM method is also realized expressed in (26) A general evaluation using (22), (23), (25) has been shown that the switching loss Pswave increases from its optimum value PswOpt to its maximum Figure 10 depicts the obtained waveforms and FFT analysis of phase voltage vAN (N is the load neutral), phase current iA and CMV vNO of the conventional sinusoidal PWM method As a comparison, the same quantities are given in Fig 11 for the proposed PWM method with CMV elimination and switching loss optimization There are different of levels of line-to-line voltage when the inverter operates with and without CMV elimination scheme, as shown in Fig 10(a) and Fig 11(a) Also, it can be noted from the FFT analysis in Fig 10(d), 10(e) and Fig 11(d), 11(e) that the conventional method yields better results of output voltage and current THD These difference can be explained based on the limited number of switching states under condition of zero CMV compared to the conventional PWM method value P0 attainable for the defined load current if the phase displacement ϕ increases from to π / As can be seen from Fig 7(d), at ϕ = π / , the A-phase is set to the dsequence of double commutations during the interval its current attains maximum absolute value P0 can be computed as: V I m (ton + toff ) P0 = dc AMax ; AMax = 2π 2Ts (27) As a result, the SLF characteristics of the Voltage-based mapping algorithm along with the Current-based mapping algorithm (optimizing algorithm) analyzed in the region 0≤ϕ≤π are illustrated in Fig SLF(ϕ) (1) 0.9 (2) 0.756 0 π /6 π /3 π /2 ϕ 2π/3 5π/6 π Fig 9: Characteristic of Switching Loss Function SLF(ϕ) of the Voltage-based mapping PWM method (1) and Optimizing method (2) Fig 10: Experimental results when using conventional Sinusoidal PWM method at modulation index m = 0.866 By applying the optimizing algorithm at the power factor of 0.85, in comparison with the voltage-based mapping PWM algorithm, the switching loss function decreases by about 10% For PF