Bài Giảng Truy Cập Bộ Nhớ Trực Tiếp DMA

M ch DMAC 8237A c a Intel ạ ủM ch DMAC 8237A c a Intel ạ ủ • Although i8237A may not appear as a discrete component in recent PCs, it’s still there… integrated in chipsets, ISPC • The i8

N i dung môn h c ộ ọ

N i dung môn h c ộ ọ

1 Gi i thi u chung v h vi x lýớ ệ ề ệ ử

2 B vi x lý Intel 8088/8086ộ ử

3 L p trình h p ng cho 8086ậ ợ ữ

4 T ch c vào ra d li uổ ứ ữ ệ

5 Ng t và x lý ng tắ ử ắ

6 Truy c p b nh tr c ti p DMAậ ộ ớ ự ế

7 Các b vi x lý trên th c tộ ử ự ế

• M ch DMAC 8237A c a Intelạ ủ

Gi i thi u v DMA ớ ệ ề

Gi i thi u v DMA ớ ệ ề

M ch DMAC 8237A c a Intel ạ ủ

M ch DMAC 8237A c a Intel ạ ủ

• Although i8237A may not appear as a discrete component in

recent PCs, it’s still there… (integrated in chipsets, ISPC)

• The i8237A has four independent DMA channels

• Original PC/XT design had one i8237A for four DMA channels

• PC/AT used two i8237As to provide 7 DMA channels

• i8237A is programmable device and can be configured for

single transfers, block transfers, Reads, Writes or

Memory-to-Memory transfers

• In the PC/AT design, a contrived 16-bit transfer design is

implemented using the i8237A

• i8237A uses a multiplexed address and data bus to reduce the device pin count

 DB0 DB7 lines contain the data bus along with the high byte of the

16-bit address bus

 An external latch is required to demultiplex the address lines

M ch DMAC 8237A c a Intel ạ ủ

M ch DMAC 8237A c a Intel ạ ủ

M ch DMAC 8237A c a Intel ạ ủ

M ch DMAC 8237A c a Intel ạ ủ

DREQ0 DACK0 DREQ1 DACK1 DREQ2 DACK2 DREQ3 DACK3

DB0 DB7

A0 A7

i8237 DMA

four DMA channels

HRQ HLDA

IOR IOW MEMR MEMW

ADSTB

EOP

DMA Addr.

Latch

DMA Page Regrs.

A16 A23

[A16 A19 for PC/XT]

I/O Mapped

to MPU, read and write

A8 A15

A0 A7

8253 (8254) Timer/

Counter

OUT1

15 usecs.

D Hi

CLR Q

Floppy Controller

Page Registers

DMA Address Tracking

• The i8237A has four registers for tracking memory addresses during a DMA block

 BASE ADDRESS REGISTER

 BASE WORD COUNT REGISTER

 CURRENT ADDRESS REGISTER

 CURRENT WORD COUNT REGISTER

DMA in the

PC/XT

Cascaded i8237As in the PC/AT

MPU

i8237A Master

i8237A Slave

DREQ0 DACK0

DREQ1 DACK1 DREQ2 DACK2

DREQ3 DACK3

DREQ5 DACK5

DREQ6 DACK6

DREQ7 DACK7

DREQ4 DACK4 HRQ

HOLDA

Cascaded i8237A DMA Controllers

DMA Cascadation

• DMA channel 7 (DREQ7) has the lowest

• Note, when a DMA transfer is in session, it cannot be 'interrupted' by

another DMA request, even if the DMA request is made by a higher priority DMA channel.

• The current DMA transfer session will be completed before the pending

DMA request is accepted

DMA Channels in the PC/AT