VLSI DESIGN AUTOMATION Homework 5 Update “INPUTOUTPUT” block function for CPU and writing DCT8bit test bench VLSI DESIGN AUTOMATION Homework 5 Update “INPUTOUTPUT” block function for CPU and writing DCT8bit test bench
VLSI DESIGN AUTOMATION Homework #5 Update “INPUT-OUTPUT” block function for CPU and writing DCT-8bit test bench Student: Bui Huu Nguyen Student ID: 2016310539 Submit date: 2016/11/15 A Block System structure that inset IN and OUT port BUS CPU_Bus sysbus n_reset Clock ACC_bus IN_Port 15-1618-20 load_ACC PC_bus load_PC load_IR OUT_Port 17-1921 load_MAR MDR_bus load_MDR IR_Port 5-13 ALU_ACC 10 ALU_add 11 ALU_sub RAM_Port 6-7-814-15 12 INC_PC 13 Addr_bus 14 CS 15 R_NW PC_Port 3-4-12 16 load_IN 17 load_OUT 18 INS ALU_Port 1-2-910-11 19 OUTS 20 IN_bus 21 OUT_bus SEQ_Port sysbus n_reset Clock CPU_Bus z_flag op B Sequencer state n_reset = S0 S1 S2 S10 S3 S4 S5 S6 S7 S9 S8 // Project: Simple CPU // File : IN.sv import cpu_defs::*; module IN (CPU_bus.IN_port bus, input wire [WORD_W-1:0] Data_IN); logic [WORD_W-OP_W-1:0] indata; assign bus.sysbus = bus.IN_bus ? indata : 'z; //always_ff @(posedge bus.clock, negedge bus.n_reset) always_ff @(posedge bus.clock) begin if (!bus.n_reset) indata