The mini mips verilog code and the test bench

The mini mips verilog code and the test bench

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THE MINI-MIPS VERILOG CODE AND THE TEST-BENCH

Verilog: Top with Data Memory

module top(

input clk, reset,

output [31:0] WriteData,DataAdr,

output MemWrite);

wire [31:0] Pcnext, Instr, Readdata; // instantiate processor and memories

mips mips (clk,reset,Instr,Readdata,Pcnext,DataAdr,WriteData,MemWrite); instructmem instructmem (Pcnext[7:2],Instr);

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Verilog: Controller module controller( input clk,reset, input [5:0] opcodeD,functD, input zeroM, output RegWriteW, output MemtoRegw, output MemWriteM, output [3:0] ALUcontrolE, output [1:0] ALUSrcE, output [1:0] RegDstE, output [1:0] jumpD, output PcSrcM); wire [2:0] ALUopD; wire [1:0] ALUSrcD,RegDstD; wire [3:0] ALUcontrolD; wire MemWriteD,RegWriteD,MemtoRegD; wire MemWriteE,RegWriteE,MemtoRegE; wire RegWriteM,MemtoRegM; wire BeqD,BegE,BneD,BneE,BeqM,BneM;

maindec maindec (opcodeD,RegWriteD,MemtoRegD,MemWriteD,BeqD, BneD,ALUSrcD,RegDstD,jumpD,ALUopD); ALUdec ALUdecoder (functD,ALUopD,ALUcontrolD);

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Verilog: Datapath module datapath( input clk,reset, input RegWriteW, input MemtoRegw, input [3:0] ALUcontrolE, input [1:0] ALUSrcE,RegDstE,jumpD, input PcSrcM, input [31:0] InstrF,ReaddataM, output zeroM, output [31:0]PcnextFD,ALUoutM,WriteDataM, output [5:0] opcodeD,functD); wire [31:0] InstrD; wire [31:0] SrcAD,SrcAE,SrcBE; wire [31:0] WriteDataD,WriteDataE; wire [31:0] ALUoutE,ALUoutW; wire [4:0] rtE,rdE; wire [4:0] WriteRegE,WriteRegM,WriteRegw; wire [31:0] PcnextbarFD; wire [31:0] PcPlus4F,PcBranchM,PcBranchE; wire [31:0] PcPlus4D,PcPlus4E; wire [31:0] SignExD,SignlmmE,SignlmmshE; wire [31:0] ResultW,ReaddataW; wire zeroE; wire [31:0] MuxResultD,BranchF; //Multiplexers mux2 muxPCSrcM_ (PcPlus4F,PcBranchM,PcSrcM,BranchF); mux4muxjump (BranchF,{PcPlus4F[31:28],InstrD[25:0],2'b00},{PcPlus4F[31:28],InstrD[25:0],2'b00)}, SrcAD,jumpD,PcnextbarFD);

mux4 muxjumpD (ResultW,ResultW,ResultW,PcPlus4D,jumpD,MuxResultD);

mux4 muxALUSrcE_ (WriteDataE,SignImmE,{InstrD[16:0],16'b00},32'b00,ALUSrcE,SrcBE); mux4 muxRegDstE_ (rtE,rdE,5'b11111,4'b0000,RegDstE,WriteRegE);

mux2 muxMemtoRegW (ALUoutW,ReaddataW,MemtoRegW,ResultW);

//register file (operates in Decode and WriteBack)

registerfile rf (clk,RegWriteW,InstrD[25:21],InstrD[20:16],WriteRegW,MuxResultD,SrcAD,WriteDataD);

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//Fetch stage Logic

flopr PcReg (clk,reset,PcnextbarFD,PcnextFD); adder PcAdd1 (PcnextFD,32'b100,PcPlus4F);

//Decode stage

assign opcodeD = InstrD[31:26]; assign functD = InstrD[5:0];

flopr r1D_ (clk,reset,PcPlus4F,PcPlus4D);

flopr 12D (clk,reset,InstrF,InstrD[31:0]); Signext se (InstrD[15:0],SignExD); //Execute stage

flopr rE (clk, reset, SrcAD,SrcAE);

flopr r2E (clk, reset, WriteDataD, WriteDataE); flopr r3E (clk, reset, InstrD[20:16],rtE); flopr r4E (clk, reset, InstrD[15:11],rdE); flopr r5E (clk, reset, SignExD,SignimmE); flopr r6E (clk, reset, PcPlus4D,PcPlus4E);

adder pcadd2 (SignimmshE,PcPlus4E,PcBranchE); SỊ2 shift2E (SignimmeE,SignimmshE); alu ALU (SrcAE,SrcBE,ALUcontrolE,ALUoutE,zeroE); // Memory stage flopr r1M (clk,reset,zeroE,zeroM); flopr r2M (clk,reset,ALUoutE,ALUoutM); flopr r3M (clk,reset,WriteDataE,WriteDataM); flopr r4M (clk,reset,WriteRegE,WriteRegM); flopr r5M (clk,reset,PcBranchE,PcBranchM); //WriteBack stage

flopr r1W (clk, reset, ALUoutM, ALUoutW); flopr r2W (clk, reset, ReaddataM,ReaddataW); flopr r3W (clk, reset, WriteRegM, WriteRegW); endmodule

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Verilog: ALU module alu (SrcA, SrcB, ALUcontrol, Result, zero); input [3:0] ALUcontrol; input [31:0] SrcA,SrcB; output zero; output reg [31:0] Result; always @(ALUcontrol,SrcA,SrcB) case(ALUcontrol)

4'b0000: Result <= SrcA&SrcB; //and

4'b0001: Result <= SrcA | SrcB; //or

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Verilog: Resettable Flip-Flop

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Verilog: Multiplexer 2 inputs

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Verilog: Multiplexer 4 inputs

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Verilog: Register File module registerfile( input clk, input we3, input [4:0] ra1,ra2,wa3, input [31:0] wd3, output [31:0] rd1,rd2); reg [31:0] rf[31:0];

// three port register file

// read two ports combinationally // write third port on rising edge of clock

// register O hardwired to 0

always @ (posedge clk) if (we3) rf[wa3] <= wd3; assign rd1 = (ral != 0) ? rf[ra1] : 0; assign rd2 = (ra2 != 0) ? rf[ra2] : 0;

endmodule

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Testbench: Top module testbench_TB; // \nputs reg clk; reg reset; // Outputs wire [31:0] WriteData; wire [31:0] DataAdr; wire MemWrite;

// \Instantiate the Unit Under Test (UUT)