victor grimblatt rd group director, digital IC design,

Digital IC Design Victor Grimblatt R&D Group Director © Synopsys 2012 SASE 2012 Agenda Introduction Electronic systems, an historic prospective Synopsys Design Flow © Synopsys 2012 Introduction © Synopsys 2012 Product Complexity / Capabilities Consumers Driving “Smart” Electronics 1980 © Synopsys 2012 1990 2000 2010 2020 Mobile Handset IC Market Value ($B) 100 80 60 40 20 2010 2011 2012 2013 2014 2015 Tablet IC Market Value ($B) 15 12 2010 2011 2012 2013 2014 2015 Source IBS, February 2011 $38B to $109B in non-memory ICs in years! © Synopsys 2012 Cloud Infrastructure: Data, Data, Data Creation Transportation 2014F 2012F 2010 2008 2006 2004 2002 2000 1998 1996 1994 1992 1990 Billions Microprocessor Sales $80 $70 $60 $50 $40 $30 $20 $10 $0 Source: Data Center Knowledge 2011; P Otellini, Intel, Investor Meeting 2010 IP Traffic, Exabytes Global IP Traffic Access Data Access 1,200 1,000 800 600 400 200 965.5 759.2 593.0 336.3 241.8 2010 2011F 451.2 2012F 2013F 2014F 2015F Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2011 Access Data Storage 10 Manipulation Storage 7.91 0.8 1.227 2009 2010 1.8 2011 2012 2013 2014 2015 Source: Wikipedia, 2011; Google, Stockholder Meeting 2010 © Synopsys 2012 Smart Everything Grid Buildings Cars Dogs…? Toasters Software Lines of Code “Smart” Microprocessors Storage Communication © Synopsys 2012 Example Sensors SW & E/E % Vehicle Cost 1970 100K 40% Electronic Content in Systems Increases 30% Semiconductor Content 25% 20% 15% 10% 5% 0% Source: ST, TI, IC Insights © Synopsys 2012 Drivers of Innovation and Differentiation EDA + IP Better Applications Sooner Electronics ~$1.31T Semi $320.8B Cheaper © Synopsys 2012 EDA & IP $8.4B Source: IC Insights, VDC Research, Synopsys Estimates What Drives the Drivers? Performance Mobile Power Cloud Infrastructure Power Performance Power/Cost/Perf “Smart” Integration © Synopsys 2012 10 Runset File Runset file is a control file that instructs Hercules where to find input data, which checks to perform and where to write output files Separate runsets are typically created for DRC and LVS • A DRC Runset instructs Hercules to check layout files for errors • A LVS Runset instructs Hercules to compare the layout netlist to the schematic netlist of a design © Synopsys 2012 138 Schematic Netlist The schematic Netlist file is used during LVS comparison It provides complete net information with each cell If schematic netlist is in CDL, NetTran will translate it to Hercules format nettran –verilog Johnson_count.v –cdl-a-cdl-s-sp-S-verilog-b1 VDD –verilog-b0 VSS\ -rootCell Johnson_count –sp /saed90nm.cdl –outName Johnson_count.sp © Synopsys 2012 139 Netlist Translation Hercules uses the NetTran utility to translate the netlist between different formats (e.g Verilog to SPICE, SPICE to Hercules netlist format) INPUT OUTPUT SPICE CDL Verilog EDIF EDIF3 (default) Hercules Silos 7/14/10 © Synopsys 2012 140 Hercules Netlist NetTran NetTran SPICE Verilog EDIF EDIF3 Hercules DRC Flow Input DRC Runset runset.ev Physical database Hercules (DRC run) Output Summary files (Error database) © Synopsys 2012 141 LVS Flow Input LVS Runset runset.ev Physical database Hercules (LVSrun) Output Summary files (Error database) © Synopsys 2012 142 Synopsys Design Flow Layout Parasitics Extraction (StarRC) © Synopsys 2012 143 StarRC Overview StarRC is a layout parasitic extraction tool StarRC can be used at any physical design cycle stage to extract accurate parasitics StarRC reads OpenAccess, Milkyway, LEF/DEF or Hercules connected databases directly, without external processing Extracted parasitics can be written into the Synopsys centralized Milkyway database for use by analysis and optimization tools Because StarRC gracefully handles designs with layout versus schematic (LVS) violations, including opens and shorts, timing convergence can be ensured before the physical verification cycle begins © Synopsys 2012 144 Inputs and Outputs of StarRC TCAD_GRD_FILE saed90nm_9lm.nxtgrd MAPPING_FILE tech2itf.map StarRC spf star_cmd rcx_cmd • • • TCAD_GRD_FILE -File containing the modeled layers of a circuit MAPPING_FILE-File containing physical layer mapping information between the input database and the specified TCAD_GRD_FILE star_cmd -ASCII file containing StarRC commands that controls extraction functions © Synopsys 2012 145 Input and Output Formats of StarRC StarRC supports these industry-standard formats: Input formats • LEF(Layout Exchange Format)/DEF(Design Exchange Format) • GDSII • Milkyway Output Netlist Formats • SPICE • Synopsys Binary Parasitic Format (SBPF) • Standard Parasitic Exchange Format (SPEF) • Detailed Standard Parasitic Format (DSPF) StarRC accepts input from GDSII, LEF/DEF, and IC Compiler formats © Synopsys 2012 146 StarRC Extraction Flow Milkyway database OR GDSII Physical Database StarRC Command File Technology data (layer physical information) *.nxtgrd Mapping file (used to map layers used in StarRC to technology layers) © Synopsys 2012 147 StarRC Parasitic Netlist Schematic Netlist Synopsys Design Flow SPICE-level Simulation of Completed Design (HSPICE) © Synopsys 2012 148 HSPICE Features HSPICE supports: • Analog/RF/mixed-signal IC Design • Verilog-A Behavioral Modeling • Design For Yield- Process Variability and MosRa Device Reliability Analysis • Transient Noise Analysis • Cell and Memory Characterization © Synopsys 2012 149 Input and Output Files of HSPICE Waveforms (*.tr) Netlist Measure Analyze type Options Model file © Synopsys 2012 150 HSPICE Measurement Results (*.mt) Synopsys Design Flow Architectural choices, RTL compilation and simulation (VCS) Logic synthesis (Design Compiler) Formal verification (Formality) Generation of test patterns (TetraMAX) Physical design (IC Compiler) Physical Verification (Hercules) Layout Parasitics Extraction (StarRC) SPICE-level simulation of completed design (HSPICE) © Synopsys 2012 151 Thank You © Synopsys 2012 152 [...]... Global Technical Services © Synopsys 2012 11 Leading the Way at 32/28nm Design > 370 32/28nm Active Designs Source: Synopsys Global Technical Services © Synopsys 2012 12 Leading the Way at 22/20nm Design > 70 22/20nm Active Designs Source: Synopsys Global Technical Services © Synopsys 2012 13 Leading the Way at 16/14nm Design > 12 16/14nm Active Designs Source: Synopsys Global Technical Services © Synopsys... Electronic Systems, an Historic Prospective © Synopsys 2012 20 Key Innovations in Electronics: Audio/Video © Synopsys 2012 21 Key Innovations in Electronics: Audio/Video © Synopsys 2012 22 Key Innovations in Electronics: Audio/Video © Synopsys 2012 23 Key Innovations in Electronics: Audio/Video © Synopsys 2012 24 Key Innovations in Electronics: Audio/Video © Synopsys 2012 25 Key Innovations in Electronics:... 501K-1M 1-2M 2-5M Logic Source: 2011 Synopsys Global User Survey © Synopsys 2012 18 5-10M Memory 50-100M >100M Hardware/Software Development Costs Software Is Half of Time-to-Market App-Specific SW $2.50 Low-Level SW OS Support $2.00 Design Management Post-silicon Validation $M $1.50 Masks Physical Design $1.00 RTL Verification $0.50 RTL Development Spec Development $- IP Qualification 1 3 5 Source:... Electronics: Audio/Video © Synopsys 2012 27 Key Innovations in Electronics: Audio/Video © Synopsys 2012 28 Key Innovations in Electronics: Audio/Video © Synopsys 2012 29 Key Innovations in Electronics: Audio/Video © Synopsys 2012 30 Key Innovations in Electronics: Audio/Video © Synopsys 2012 31 Key Innovations in Electronics: Audio/Video 2005 Sonos © Synopsys 2012 32 Key Innovations in Electronics: Computers... 2012 32 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 33 Going to a satellite not so far away! Apollo Guidance Computer, ~100 Microns, MIT 1961 -3 10 MIPS © Synopsys 2012 34 Source: MIT, 1961 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 35 Key Innovations in Electronics: Computers & Communications © Synopsys 2012 36