Embedded systems structure

Embedded Systems Structure Amr Ali Abdel-Naby Embedded Systems Developer amraldo@hotmail.com +2-012-3600-207 Embedded Systems Structure Amr Ali AbdelNaby@2010 Outline • • • • • Composition of Embedded Systems Processor System Bus Memory Devices Peripherals Amr Ali Abdel-Naby@2010 Embedded Systems Structure Part I: Embedded Systems Structure • • • • • Composition of Embedded Systems Processor System Bus Memory Devices Peripherals Amr Ali Abdel-Naby@2010 Embedded Systems Structure What is an Embedded System? • A system composed of HW + SW to perform a dedicated function • On average, a human being meets 100s of embedded systems daily Amr Ali Abdel-Naby@2010 Embedded Systems Structure Embedded System Components Application SW SW Operating System Device Drivers H W Processor Amr Ali Abdel-Naby@2010 Memory Devices Embedded Systems Structure I/O Devices Part I: Embedded Systems Structure • • • • • Composition of Embedded Systems Processor System Bus Memory Devices Peripherals Amr Ali Abdel-Naby@2010 Embedded Systems Structure The Processor • • • • The core of a digital system AKA CPU Performs arithmetic, control, data, and I/O operations A small IC that embeds everything a CPU needs is called a microprocessor • Nowadays, this IC is called a SOC Amr Ali Abdel-Naby@2010 Embedded Systems Structure The Processor Structure • • • • Registers ALU: Arithmetic Logic Unit CU: Control Unit Internal Bus Registers Internal Bus ALU Amr Ali Abdel-Naby@2010 Embedded Systems Structure CU Registers • Temporal storage inside the CPU o Flip-flops + latches • General purpose register o Carry out program or data processing • Control register o o Controls the program or the processor Program Counter (PC), … • Status/flag register o Shows the current state of the processor Amr Ali Abdel-Naby@2010 Embedded Systems Structure ALU • Arithmetic operations o +, -, … • Logical operators o AND, OR, … • Writes operation results to the status register or the flag register o Carry occurrence, overflow occurrence, … Amr Ali Abdel-Naby@2010 Embedded Systems Structure Types of Memories Types Volatile Memory NonVolatile Memory Speed Cost Use SRAM Several ns, Fast High Cache DRAM Tens of ns Low Main memory EEPROM Tens of ns High Small size data or program storage NAND Tens of ns Low Data Storage NOR Tens of ns High Program and Data Storage Flash Amr Ali Abdel-Naby@2010 Embedded Systems Structure C/Cs Read and WRITE with block units, High Capacity Random Access Memories • AKA as RAM • Data is maintained only when power is supplied • types of RAM: o Static RAM (SRAM)  Fast  4-6 transistors/bit  Does not need refreshing o Dynamic RAM (DRAM)      o Slow transistor/bit Needs refreshingSlow transistor/bit Needs refreshing Other types  SDRAM, Video RAM, … Amr Ali Abdel-Naby@2010 Embedded Systems Structure Cache Memory System CPU 400 MHZ Main Memory 10 MHZ CPU + Cache 400 MHZ BUS 66 MHZ BUS 66 MHZ System performance is lowered due to slow bus and memory regardless of high speed CPU Amr Ali Abdel-Naby@2010 Main Memory 10 MHZ Improved performance by accompanying CPU with a high speed memory to store frequently accessed instructions/data Embedded Systems Structure Read Operation with a Cache • Cache hit o o A requested instruction or data is in cache Cache performance is high when cache hit rate is high • Cache miss o o A requested instruction or data is not in cache Cache performance is low when cache miss is high • Line fill Retrieving data from external memory to cache in case of cache miss o Caches retrieve a complete line o Amr Ali Abdel-Naby@2010 Embedded Systems Structure Write Operation with a Cache • Write Through o A CPU write to a specific address writes to both the external memory and the cache • Write Back o A CPU write to a specific address writes only to the cache and postpones the writing to external memory at a later time Amr Ali Abdel-Naby@2010 Embedded Systems Structure Memory Management Unit • Address translation o From virtual address to physical address • Memory protection CPU Virtual Address Amr Ali Abdel-Naby@2010 MMU Physical Address Embedded Systems Structure Main Memory Part I: Embedded Systems Structure • • • • • Composition of Embedded Systems Processor System Bus Memory Devices Peripherals Amr Ali Abdel-Naby@2010 Embedded Systems Structure I/O Device • Exchanges information with CPU • Includes digital and non-digital signals • Only digital signals are exchanged directly with the CPU CPU Signals CPU Amr Ali Abdel-Naby@2010 Device Signals I/O Controller Embedded Systems Structure I/O Device I/O Device Address Allocation • Allocation is necessary to control each I/O device • I/O mapped I/O o o Exclusive I/O address space Widely used in PC world • Memory mapped I/O o o Uses unused regions of normal memory addresses Widely used in embedded world Amr Ali Abdel-Naby@2010 Embedded Systems Structure Memory Mapped I/O vs I/O Type Memory Mapped I/O Mapped Mapped I/O Example CPUs ARM, PowerPC, M68K, Intel x86 Intel x86 I/O Device Domain A memory region Exclusive I/O region Instruction Access both memory and I/O devices Address distinguishes both Separate memory and I/O device instructions Hardware A decoder interprets the address and decides CPU has a separate signal that distinguishes whether to select a memory or I/O device memory address and I/O addresses Remarks I/O region must be set Non-cacheable area I/O region variables must be declared as volatile type variable Amr Ali Abdel-Naby@2010 Embedded Systems Structure I/O Resource Management • Polling o o A program continuously checks the device Existence, data requests, operations completion, … • Interrupt o o o If a device needs a transaction, it interrupts the processor A processor executes a single instruction at a time Multitasking can be supported if interrupts are in use • Direct Memory Access (DMA) o Allows I/O device and memory to transfer data between each other without CPU interference Amr Ali Abdel-Naby@2010 Embedded Systems Structure Interrupt Controller • Controls interrupt requests (IRQ) generated by I/O devices • IRQ acknowledge (IRQACK) is provided back depending on the I/O device IRQ CPU IRQACK Amr Ali Abdel-Naby@2010 Interrupt Controller Mask, Pending IRQ IRQACK Embedded Systems Structure I/O Device Interrupt Generation • Interrupt request An I/O device requests an I/O operation with the CPU I/O device generates interrupt, so the CPU performs some operations without the program control o The CPU performs some operations to decide whether to process the interrupt or not o The code that processes the interrupt is called Interrupt Service Routine (ISR) o Interrupt vector is the memory location where the ISR rsides o o • Examples o Data reception complete Amr Ali Abdel-Naby@2010 Embedded Systems Structure Flow Control when Interrupt is Generated INT Amr Ali Abdel-Naby@2010 ISR Embedded Systems Structure Practice I: Embedded Systems Development • Please refer to the labs handouts Amr Ali Abdel-Naby@2010 Embedded Systems Structure [...]... performance Embedded Systems Structure Part I: Embedded Systems Structure • • • • • Composition of Embedded Systems Processor System Bus Memory Devices Peripherals Amr Ali Abdel-Naby@2010 Embedded Systems Structure System Bus Architectures • Von-Neumann CPU • Harvard CPU Instruction/Data Memory Instruction Memory Data Memory Amr Ali Abdel-Naby@2010 Embedded Systems Structure Part I: Embedded Systems Structure. .. physical address • Memory protection CPU Virtual Address Amr Ali Abdel-Naby@2010 MMU Physical Address Embedded Systems Structure Main Memory Part I: Embedded Systems Structure • • • • • Composition of Embedded Systems Processor System Bus Memory Devices Peripherals Amr Ali Abdel-Naby@2010 Embedded Systems Structure I/O Device • Exchanges information with CPU • Includes digital and non-digital signals •... readability Amr Ali Abdel-Naby@2010 Embedded Systems Structure C/Cs of Assembly Language • Pros Better readability and understanding compared to machine code o Easier to debug and maintain compared to machine code o • Cons Knowledge of processor internal structure and HW is necessary o Different assembly for different processors o Amr Ali Abdel-Naby@2010 Embedded Systems Structure Assembler and Assemble... Abdel-Naby@2010 Device Signals I/O Controller Embedded Systems Structure I/O Device I/O Device Address Allocation • Allocation is necessary to control each I/O device • I/O mapped I/O o o Exclusive I/O address space Widely used in PC world • Memory mapped I/O o o Uses unused regions of normal memory addresses Widely used in embedded world Amr Ali Abdel-Naby@2010 Embedded Systems Structure Memory Mapped I/O vs I/O... machine code Amr Ali Abdel-Naby@2010 Embedded Systems Structure Instruction • Instruction = Op Code + Operand o o Op Code is an action taken by a processor Operand is the target the Op Code should take action to ADD A,B,C Op Code: ADD Operands: A, B, C Symantec: Add register B and register C and put result in register A Amr Ali Abdel-Naby@2010 Embedded Systems Structure Types of Processors • Complex... Execute 2 Fetch 3 Amr Ali Abdel-Naby@2010 Execute 2 Execute 3 Embedded Systems Structure Fetch 3 Execute 3 Various Processors • i386 o o Long history PCs • ARM o o Simple Cell phones and PDAs • PowerPC o Networking capabilities • M68K o Network devices and portable terminals • MIPS o High speed network devices Amr Ali Abdel-Naby@2010 Embedded Systems Structure MCU, MPU, and SoC • System on Chip (SoC) o o... Abdel-Naby@2010 Embedded Systems Structure Cache Memory System CPU 400 MHZ Main Memory 10 MHZ CPU + Cache 400 MHZ BUS 66 MHZ BUS 66 MHZ System performance is lowered due to slow bus and memory regardless of high speed CPU Amr Ali Abdel-Naby@2010 Main Memory 10 MHZ Improved performance by accompanying CPU with a high speed memory to store frequently accessed instructions/data Embedded Systems Structure Read... complete line o Amr Ali Abdel-Naby@2010 Embedded Systems Structure Write Operation with a Cache • Write Through o A CPU write to a specific address writes to both the external memory and the cache • Write Back o A CPU write to a specific address writes only to the cache and postpones the writing to external memory at a later time Amr Ali Abdel-Naby@2010 Embedded Systems Structure Memory Management Unit •... integrated on a single chip  SW + HW • MCU, MPU o Another naming of an SoC  Depends on vendor Amr Ali Abdel-Naby@2010 Embedded Systems Structure Program • A list of acceptable processor instructions • Designed to achieve a specific result Amr Ali Abdel-Naby@2010 Embedded Systems Structure Machine Code and Assembly Language • Machine code o o o 1’s and 0’s only Understood by processor only Inconvenient... Abdel-Naby@2010 Embedded Systems Structure Instruction Processor Bus • A bus is a path that connects the various devices of a system • Internal bus o Between registers and ALU • External bus o o o o Between I/O devices, memories, and CPU Data bus: transfers data Address bus: transfers address information Control bus: transfers control signals Amr Ali Abdel-Naby@2010 Embedded Systems Structure Pipeline