memory architecture exploration for programmable embedded systems

[...]... the memory system performance for varied power and cost profiles for programmable embedded systems Let us now examine our proposed memory system exploration approach Figure 1.1 depicts three aspects of the memory sub-system that contribute towards 4 MEMORY ARCHITECTURE EXPLORATION the programmable embedded system’s overall behavior: (I) the Application, (II) the Memory Architecture, and (III) the Memory. .. algorithm Memory Architecture Exploration for the Compress Kernel Memory Modules and Connectivity Exploration for the Compress Kernel Memory Exploration for the Compress Kernel Memory Exploration for the Li Kernel Memory Exploration for the Li Kernel Memory Exploration for the Vocoder Kernel Memory Exploration for the Vocoder Kernel xi 70 76 82 84 86 88 97 98 100 100 111 112 113 115 115 116 117 This page... Audience This book is designed for different groups in the embedded systems- on-chip arena First, the book is designed for researchers and graduate students interested in memory architecture exploration in the context of compiler-in-the-loop exploration for programmable embedded systems- on-chip Second, the book is intended for embedded system designers who are interested in an early exploration methodology,... cost/performance and power The resulting architecture in Figure 1.2 contains the programmable processor, the synthsized ASIC, and an example memory and connectivity architecture We explore the memory system designs following two major exploration loops”: (I) Early Memory Architecture Exploration, and (II) Compiler-in-theloop Memory Exploration (I) In the first exploration loop” we perform early Memory. .. processor -memory architecture This new approach for memory architecture exploration replaces the traditional blackbox view of the memory system and allows for aggressive co-optimization of the programmable processor together with a customized memory system The book concludes with a set of experiments demonstrating the utility of our exploration approach We perform architecture and compiler exploration for a set... Experimental Results Exploration results for our Access Pattern based Memory Customization algorithm Selected cost/performance designs for the connectivity exploration Pareto coverage results for our Memory Architecture Exploration Approach Dynamic cycle counts for the TIC6201 processor with an SDRAM block exhibiting 2 banks, page and burst accesses Number of assembly lines for the first phase memory access... the memory access patterns in the application, the Processor -Memory Architecture as well as a memory- aware compiler, to sig- 2 MEMORY ARCHITECTURE EXPLORATION nificantly improve the memory system behavior By exploring a design space much wider than traditionally considered, it is possible to generate substantial performance improvements, for varied cost and power footprints 1.2 Memory Architecture Exploration. .. embedded systems Chapter 3: Early Memory Size Estimation In order to drive design space exploration of the memory sub-system, we perform early estimation of the memory size requirements for the different data structures in the application Chapter 4: Memory Architecture Exploration Starting from the most active access patterns in the embedded application, we explore the memory and connectivity architectures... pipelining information) However, it is also important to explore the design space of Memory Architecture with memory- library-aware compilation tools that explicitly model and exploit the high-performance features of such diverse memory modules Indeed, particularly for the memory system, customizing the memory architecture, (together with a more accurate compiler model for the different memory characteristics)... paretos for the connectivity exploration of compress, assuming cost/perf and cost/power memory modules exploration Cost/perf vs perf/power paretos in the cost/perf space for Compress, assuming cost-power memory modules exploration Cost/perf vs perf/power paretos in the perf/power space for Compress, assuming cost-power memory modules exploration Cost/perf vs perf/power paretos in the cost/perf space for . Memory Architecture Exploration for Programmable Embedded Systems This page intentionally left blank MEMORY ARCHITECTURE EXPLORATION FOR PROGRAMMABLE EMBEDDED SYSTEMS PETER GRUN Center for Embedded. algorithm. Memory Architecture Exploration for the Compress Ker- nel . Memory Modules and Connectivity Exploration for the Compress Kernel. Memory Exploration for the Compress Kernel. Memory Exploration. Compress Kernel. Memory Exploration for the Li Kernel . Memory Exploration for the Li Kernel . Memory Exploration for the Vocoder Kernel. Memory Exploration for the Vocoder Kernel. 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 6.1 6.2 6.3 6.4 6.5 6.6 6.7 100 100 111 112 113 115 115 116 117 70 76 82 84 86 88 97 98 This