Instruction cache optimizations for embedded systems

INSTRUCTION CACHE OPTIMIZATIONS FOR EMBEDDED SYSTEMS YUN LIANG (B.Eng, TONGJI UNIVERSITY SHANGHAI, CHINA) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY IN COMPUTER SCIENCE DEPARTMENT OF COMPUTER SCIENCE NATIONAL UNIVERSITY OF SINGAPORE 2010 Acknowledgements First of all, I would like to express my deepest gratitude to my Ph.D advisor, Professor Tulika Mitra for her constant guidance and encouragement during my five years of graduate study. Her persistent guidance helps me stay on track of doing research. Without her help this dissertation would not have been possible. I am grateful to my dissertation committee members, Professors Wong Weng Fai, Teo Yong Meng and Sri Parameswaran for their time and thoughtful comments. Thanks are also due to Professors Abhik Roychoudhury and Samarjit Chakraborty. It is an honor for me to work with them throughout my graduate study. I have greatly benefitted from the discussion I have had with them. I would like to thank the National University of Singapore for funding me with research scholarship and offering me the teaching opportunities to support my last year of study. My thanks also go to the administrative staffs in School of Computing, National University of Singapore for their supports during my study. I would like to thank my friends in NUS for assisting and helping me in my research: Ju Lei, Ge Zhiguo, Huynh Phung Huynh, Unmesh D. Bordoloi, Joon Edward Sim, Ankit Goel, Ramkumar Jayaseelan, Vivy Suhendra, Pan Yu, Li Xianfeng, Liu Haibin, i ii Liu Shanshan, Kathy Nguyen Dang, Andrei Hagiescu and David Lo. My graduate life at NUS would not have been interesting and fun without them. I woud like to extend heartfelt gratitude to my parents for their never ending love and faith in me and encouraging me to pursue my dreams. They are a great source of encouragement during my graduate study especially when I found it difficult to carry on. Thank you for always being there. Finally, this dissertation would not have been possible without the support of my wife Chen Dan. She sacrificed a great deal ever since I started my graduate study, but she was never one to complain. The hardest part has been the last year, when I was doing teaching assistantship and she was looking for jobs. In spite of all the difficulties, Chen Dan is always supportive. Thank you for your love and understanding. Contents Acknowledgements i Contents iii Abstract viii List of Publications x List of Tables xi List of Figures xii Introduction 1.1 Embedded System Design . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Memory Optimization for Embedded System . . . . . . . . . . . . . . 1.3 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . Background 10 iii iv 2.1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Cache Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Literature Review 3.1 Application Specific Memory Optimization . . . . . . . . . . . . . . . 14 3.2 Design Space Exploration of Caches . . . . . . . . . . . . . . . . . . . 15 3.3 14 3.2.1 Trace Driven Simulation . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 Analytical Modeling . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.3 Hybrid Approach . . . . . . . . . . . . . . . . . . . . . . . . . 18 Cache Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.1 Hard Real-time Systems . . . . . . . . . . . . . . . . . . . . . 20 3.3.2 General Embedded Systems . . . . . . . . . . . . . . . . . . . 21 3.4 Code Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 Cache Modeling for Timing Analysis . . . . . . . . . . . . . . . . . . 25 Cache Modeling via Static Program Analysis 27 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 Analysis Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Cache Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 4.3.1 Concrete Cache States . . . . . . . . . . . . . . . . . . . . . . 31 4.3.2 Probabilistic Cache States . . . . . . . . . . . . . . . . . . . . 32 Static Cache Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.1 Analysis of DAG . . . . . . . . . . . . . . . . . . . . . . . . . 35 v Analysis of Loop . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4.3 Special case for Direct Mapped Cache . . . . . . . . . . . . . . 39 4.4.4 Analysis of Whole Program . . . . . . . . . . . . . . . . . . . 41 4.5 Cache Hierarchy Analysis . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.7 4.4.2 4.6.1 Level-1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.2 Multi-level Caches . . . . . . . . . . . . . . . . . . . . . . . . 52 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Design Space Exploration of Caches 57 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 General Binomial Tree (GBT) . . . . . . . . . . . . . . . . . . . . . . 59 5.3 Probabilistic GBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.1 Concatenation of Probabilistic GBTs . . . . . . . . . . . . . . 64 5.3.2 Combining GBTs in a Probabilistic GBT . . . . . . . . . . . . 66 5.3.3 Bounding the size of Probabilistic GBT . . . . . . . . . . . . . 68 5.3.4 Cache Hit Rate of a Memory Block . . . . . . . . . . . . . . . 70 5.4 Static Cache Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Instruction Cache Locking 6.1 76 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 vi 6.2 Cache Locking Problem . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3 Cache Locking Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 84 Optimal Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.2 Heuristic Approach . . . . . . . . . . . . . . . . . . . . . . . . 91 6.4 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Procedure Placement 111 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.2 Procedure Placement Problem . . . . . . . . . . . . . . . . . . . . . . 114 7.3 Intermediate Blocks Profile . . . . . . . . . . . . . . . . . . . . . . . . 115 7.4 Procedure Placement Algorithm . . . . . . . . . . . . . . . . . . . . . 120 7.5 Neutral Procedure Placement . . . . . . . . . . . . . . . . . . . . . . . 123 7.6 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.7 6.3.1 7.6.1 Layout for a Specific Cache Configuration . . . . . . . . . . . . 129 7.6.2 Neutral Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Putting it All Together 141 8.1 Integrated Optimization Flow . . . . . . . . . . . . . . . . . . . . . . . 141 8.2 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 142 Conclusion 9.1 144 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 vii 9.2 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Bibliography 146 Abstract The application specific nature of embedded systems creates the opportunity to design a customized system-on-chip (SoC) platform for a particular application or an application domain. Cache memory subsystem bears significant importance as it bridges the performance gap between the fast processor and the slow main memory. In particular, instruction cache, which is employed by most embedded systems, is one of the foremost power consuming and performance determining microarchitectural features as instructions are fetched almost every clock cycle. Thus, careful tuning and optimization of instruction cache memory can lead to significant performance gain and energy saving. The objective of this thesis is to exploit application characteristics for instruction cache optimizations. The application characteristics we use include branch probability, loop bound, temporal reuse profile and intermediate blocks profile. These application characteristics are identified through profiling and exploited by our subsequent analytical approach. We consider both hardware and software solutions. The first part of the thesis focuses on hardware optimization — identifying best cache configurations to match the specific temporal and spatial localities of a given application through analytical approach. We first develop a static program analysis to viii ix accurately model the cache behavior of a specific cache configuration. Then, we extend our analysis by taking the structural relations among the related cache configurations into account. Our analysis can estimate the cache hit rates for a set of cache configurations with varying number of sets and associativity in one pass as long as the cache line size remains constant. The input to our analysis is simply the branch probability and loop bounds, which is significantly more compact compared to the memory address traces required by trace-driven simulators and other trace based analytical works. The second part of the thesis focuses on software optimizations. We propose techniques to tailor the program to the underlying instruction cache parameters. First, we develop a framework to improve the average-case program performance through static instruction cache locking. We introduce temporal reuse profile to accurately and efficiently model the cost and benefit of locking memory blocks in the cache. We propose two cache locking algorithms : an optimal algorithm based on branch-and-bound search and a heuristic approach. Second, we propose an efficient algorithm to place procedures in memory for a specific cache configuration such that cache conflicts are minimized. As a result, both performance and energy consumption are improved. Our efficient algorithm is based on intermediate blocks profile that accurately but compactly models cost-benefit of procedure placement for both direct mapped and set associative caches. Finally, we propose an integrated instruction cache optimization framework by combining all the techniques together. Chapter Conclusion 9.1 Thesis Contributions The application specific nature of embedded systems creates the opportunity to design a customized system-on-chip (SoC) platform for a particular application or an application domain. With the knowledge of application characteristics, many cache parameters can be customized to meet various design goals. This is especially true for parameterizable embedded systems. Furthermore, the program code can be transformed in various ways to fit the underlying cache architectures. The optimized memory architecture and program code can improve the performance and energy consumption significantly. The objective of this thesis is utilize application characteristic so as to achieve significant cache performance improvements. Application characteristics used in this thesis include basic block execution count profile (branch probability, loop bound), temporal reuse profile and intermediate blocks profile. These application characteristics 144 CHAPTER 9. CONCLUSION 145 are identified through profiling and exploited by our subsequent analytical approach. In this thesis, we consider both hardware (architecture) and software optimization solutions. For hardware (architecture) solutions, we propose techniques to customize the instruction cache according to the specific temporal and spatial localities of a given application. For software solutions, we propose techniques to tailor the program to underlying instruction cache parameters. More concretely, the contributions of this thesis are: • a static program analysis that accurately and efficiently model the cache behavior of a specific cache configuration. • an analytical approach that accurately explores cache design space with multiple cache configurations in a single pass. • a precise and accurate cache modeling using temporal reuse profile and two static instruction cache locking algorithms for performance improvement. • an improved procedure placement algorithm for set associative caches using intermediate blocks profile and an algorithm for a neutral code layout with good portability. 9.2 Future Directions Though the techniques developed by this thesis are mainly for instruction caches, most of them can be applied to data cache. First, probabilistic cache state proposed in chap- CHAPTER 9. CONCLUSION 146 ter and is a general concept which can be used for data cache as well [81] with special optimizations for space. Second, cache locking techniques in chapter can be used for data cache, given the corresponding program data reference trace. Finally, procedure placement technique in chapter can be used for data cache by replacing procedures with data segments. With the advent of multi-core architecture, the embedded computing world is moving into the direction of multiprocessing. This opens up new challenges for the embedded system designers. The main challenges arise from the mapping and scheduling of parallel tasks, conflict modeling of shared resources such as cache and communication media, and timing unpredictability caused by cache warm-up due to task migration and preemption. In this thesis, the techniques we developed are mainly targeted for a single core. When attempting to extend the local optimization techniques to global optimization, the interactions among the cores have to be taken into account. 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[...]... memory and the cache A cache is divided into K sets Each cache set, in turn, is divided into A cache blocks, where A is the associativity of the cache For a direct-mapped cache A = 1, for a set-associative cache A > 1, and for a fully associative cache K = 1 In other words, a direct-mapped cache has only one cache block per set, whereas a fully-associative cache has only one cache set Now the cache size... the cache instead of main memory, which consumes more power and incurs longer delay per access In this thesis, we focus on instruction cache, which is present in almost all embedded systems Instruction cache is one of the foremost power consuming and performance determining microarchitectural features of modern embedded systems as instructions are fetched almost every clock cycle For example, instruction. .. related to instruction cache exploration and optimization for embedded systems Chapter 4 presents a static program analysis technique to model the cache behavior of a particular application Chapter 5 extends the static program analysis in chapter 4 for efficient instruction cache design space exploration Chapter 6 discusses employing cache locking for improving average case execution time for general embedded. .. we will summarize the techniques of employing cache locking for improving the timing predictability for hard real-time systems and the average-case performance of general embedded systems 3.3.1 Hard Real-time Systems Instruction cache locking has been employed in hard real-time systems for better timing predictability [80, 25, 30, 66] In hard real-time systems, worst case execution time (WCET) is an... will be cache hits However, most existing cache locking techniques are proposed for improving the predictability of hard real-time systems Using cache locking for improving the performance of general embedded systems are not explored We observe that cache locking can be quite effective in improving the average-case execution time of general embedded applications as well We propose precise cache modeling... optimizing cache memory design for embedded systems has received a lot of attention from the research community [75, 106, 10, 15, 86, 104, 69, 59, 60, 88, 18, 78, 19, 96] In this thesis, we focus on design space exploration of caches — determining the best instruction cache parameters from vast number of cache configurations for a given application and software optimizations — instruction cache locking... be tailored for the specific cache architectures Cache aware program transformations allow the modified application to utilize the underlying cache more efficiently For architecture customization, the system designer can choose an on-chip cache configuration that is suited for a particular application and customize the caches for it However, the cache design parameters include the size of the cache, the... the cache returned from design space exploration may be too big Hence, we also consider software based instruction cache optimization techniques to further improve performance CHAPTER 1 INTRODUCTION 5 For software solutions, since the underlying instruction cache parameters are known, the program code can be appropriately tailored for the specific cache architecture More concretely, for software optimizations, ... 27% of the total power is spent by instruction cache for StrongARM 110 processor [70] Thus, careful tuning and optimization of instruction cache memory can lead to significant performance gain and energy saving Instruction cache performance can be improved via hardware (architecture) means and software means From an architectural perspective, caches can be customized for the specific temporal and spatial... Design Space Exploration of Caches One of the most effective cache optimizations is to tune cache parameters for the specific application The tuning process is done through cache design space exploration More concretely, for application specific embedded system, we can choose specific cache configuration from the huge cache design space to meet the design constraints (i.e., performance, energy and hardware . INSTRUCTION CACHE OPTIMIZATIONS FOR EMBEDDED SYSTEMS YUN LIANG (B.Eng, TONGJI UNIVERSITY SHANGHAI, CHINA) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY. the performance gap between the fast processor and the slow main memory. In particular, instruction cache, which is employed by most embedded systems, is one of the foremost power consuming and performance. optimization of instruction cache memory can lead to significant performance gain and energy saving. The objective of this thesis is to exploit application characteristics for instruction cache optimizations.