Instruction cache optimizations in embedded real time systems

INSTRUCTION CACHE OPTIMIZATIONS IN EMBEDDED REAL-TIME SYSTEMS DING HUPING (B.Eng., Harbin Institute of Technology) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF COMPUTER SCIENCE NATIONAL UNIVERSITY OF SINGAPORE 2013 Acknowledgements First of all, my gratitude goes to my Ph.D. advisor Prof. Tulika Mitra. Thanks for her persistent and generous guidance on the research. She is full of wisdom, and I benefit a lot from her insightful comments and advices. I would also thank her patience and encouragement during my study, especially when there are difficulties. She also offered me the research assistant position in the last year of my study. Without her help, this thesis would not be possible. I would like to thank my thesis committee members. Thanks for their time and valuable comments. I would like to express my sincere gratitude to Prof. Wong Weng-Fai. Thanks for his guidance in my early stage of Ph.D. study. He is generous and kind, and helped me a lot. I am also grateful to Dr. Liang Yun in Peking University for the research collaborations. I collaborated with him in most of my research work. It is my great pleasure to cooperate with him. I also thank my friends and lab mates, Sudipta Chattopadhyay, Wang Chundong, Qi Dawei, Chen Jie, Chen Liang, Mihai Pricopi and Thannirmalai Somu Muthukaruppan, for their help in the research work and the fun in daily life. I also give my sincere gratitude to my girlfriend Fu Qinqin, the beautiful and thoughtful girl, for being together with me for over four years. She brought me happiness during my Ph.D. study. She encourages me to pursue my dreams. Thanks for her patience and great love. I also want to thank my parents and my little sister. They have been always supportive of me in pursuing my dreams. Thanks for their support, encouragement and great love. The work presented in this thesis was partially supported by Singapore Ministry of Education Academic Research Fund Tier 2, MOE2009-T2-1-033. i Contents Acknowledgements i Contents ii Abstract vi List of Publications viii List of Tables ix List of Figures x Introduction 1.1 Embedded Real-time Systems . . . . . . . . . . . . . . . . . . 1.2 Cache Modeling and Optimization . . . . . . . . . . . . . . . . 1.2.1 Cache in Uni-Processor . . . . . . . . . . . . . . . . . . 1.2.2 Shared Cache in Multi-core Processors . . . . . . . . . 1.3 Research Aims . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . 10 Background 11 2.1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Cache Locking . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Worst-case Execution Time Computation . . . . . . . . . . . . 14 2.3.1 Micro-architectural Modeling . . . . . . . . . . . . . . 15 2.3.2 Program Path Analysis . . . . . . . . . . . . . . . . . . 18 Literature Review 3.1 21 Cache Analysis in Uni-processor . . . . . . . . . . . . . . . . . 21 3.1.1 Intra-task Cache Conflict Analysis . . . . . . . . . . . . 21 3.1.2 Inter-task Cache Interference Analysis . . . . . . . . . . 23 ii 3.2 Cache Analysis in Multi-core . . . . . . . . . . . . . . . . . . . 25 3.3 Cache Locking . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1 Cache Locking for Single Task . . . . . . . . . . . . . . 27 3.3.2 Cache Locking in Multitasking . . . . . . . . . . . . . . 28 3.4 Memory Optimizations in Multi-core Processors . . . . . . . . . 29 3.5 Other Optimizations for Worst-case Performance . . . . . . . . 30 3.5.1 Cache Partitioning . . . . . . . . . . . . . . . . . . . . 30 3.5.2 Code Layout Optimization . . . . . . . . . . . . . . . . 31 3.5.3 Scratchpad Memory . . . . . . . . . . . . . . . . . . . 31 Partial Cache Locking for Single Task 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 Motivating Example 4.3 Cache Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.1 4.4 4.5 34 . . . . . . . . . . . . . . . . . . . . . . . 35 Cache States . . . . . . . . . . . . . . . . . . . . . . . 37 Partial Cache Locking Algorithms . . . . . . . . . . . . . . . . 39 4.4.1 Optimal solution with concrete cache states . . . . . . . 40 4.4.2 Heuristic with abstract cache states . . . . . . . . . . . 43 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . 47 4.5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . 47 4.5.2 Partial Cache Locking vs. Static Analysis . . . . . . . . 47 4.5.3 Partial versus Full Cache Locking . . . . . . . . . . . . 48 4.5.4 Impact of Different Associativity . . . . . . . . . . . . 50 4.5.5 Impact of Different Block Sizes . . . . . . . . . . . . . 53 4.5.6 Optimal vs. Heuristic Approach . . . . . . . . . . . . . 53 4.5.7 Percentage of Lines Locked . . . . . . . . . . . . . . . 55 4.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Partial Cache Locking for Multitasking 57 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 Motivating Example . . . . . . . . . . . . . . . . . . . . . . . 59 5.2.1 WCET Comparison of Various Locking Schemes. . . . . 61 5.2.2 Scheduling Results of RMS . . . . . . . . . . . . . . . 62 5.3 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4 Framework Overview . . . . . . . . . . . . . . . . . . . . . . . 64 5.5 WCET and CRPD Analysis . . . . . . . . . . . . . . . . . . . . 66 5.5.1 Intra-Task WCET . . . . . . . . . . . . . . . . . . . . . 66 5.5.2 Inter-Task CRPD . . . . . . . . . . . . . . . . . . . . . 67 iii 5.6 5.7 5.6.1 Cost-benefit analysis within a task . . . . . . . . . . . . 70 5.6.2 Cost-benefit analysis of other tasks . . . . . . . . . . . . 71 5.6.3 Memory block selection strategy . . . . . . . . . . . . . 72 5.6.4 Integrated Locking + Analysis Algorithms . . . . . . . . 73 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . 78 5.7.1 Experiments Setup . . . . . . . . . . . . . . . . . . . . 78 5.7.2 CPU Utilization Comparison . . . . . . . . . . . . . . . 79 5.7.3 Response Time Speed-up . . . . . . . . . . . . . . . . . 79 5.7.4 CPU Utilization Breakdown . . . . . . . . . . . . . . . 80 5.7.5 Unlocked Cache Space . . . . . . . . . . . . . . . . . . 81 5.7.6 Runtime of Our Approach . . . . . . . . . . . . . . . . 82 5.8 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Dynamic Cache Locking 84 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.2 Motivating Example 6.3 Cache Modeling and Locking . . . . . . . . . . . . . . . . . . . 88 6.4 6.5 Locking Algorithm for Multitasking . . . . . . . . . . . . . . . 69 . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.1 Cache Modeling . . . . . . . . . . . . . . . . . . . . . 89 6.3.2 Cache Locking Mechanism . . . . . . . . . . . . . . . . 89 Dynamic Cache Locking Algorithm . . . . . . . . . . . . . . . 90 6.4.1 Framework Overview . . . . . . . . . . . . . . . . . . . 91 6.4.2 WCET Analysis . . . . . . . . . . . . . . . . . . . . . 92 6.4.3 Resilience Analysis . . . . . . . . . . . . . . . . . . . . 93 6.4.4 Locking Slot Analysis . . . . . . . . . . . . . . . . . . 94 6.4.5 Memory Block Selection . . . . . . . . . . . . . . . . . 101 6.4.6 Complexity Analysis . . . . . . . . . . . . . . . . . . . 102 Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . 103 6.5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . 103 6.5.2 Comparison with Static Approaches . . . . . . . . . . . 104 6.5.3 Comparison with Region-based Approach . . . . . . . . 105 6.5.4 Runtime of Different Methods . . . . . . . . . . . . . . 107 6.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Cache Locking for Shared Cache Multi-core Processors 109 7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.2 Motivating Example for Task Mapping . . . . . . . . . . . . . . 111 iv 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Task Model and System Architecture . . . . . . . . . Task Mapping Framework Overview . . . . . . . . . Components of the Task Mapping Framework . . . . 7.5.1 Intra-Task Cache Analysis . . . . . . . . . . 7.5.2 WCRT Estimation . . . . . . . . . . . . . . 7.5.3 ILP Formulation for Task Mapping . . . . . Cache Locking in Multi-core Processors . . . . . . . 7.6.1 Locking Mechanisms . . . . . . . . . . . . . 7.6.2 Locking Algorithm for Multi-core Processors Experimental Evaluation . . . . . . . . . . . . . . . 7.7.1 Experimental Setup . . . . . . . . . . . . . . 7.7.2 DEBIE Case Study . . . . . . . . . . . . . . 7.7.3 Synthetic Task Graphs . . . . . . . . . . . . 7.7.4 Impact of Different Number of Cores . . . . 7.7.5 L1 Block Size vs. L2 Block Size . . . . . . . Discussion . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 113 116 117 117 118 122 123 123 127 127 130 132 134 134 135 135 Conclusion 136 8.1 Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . 136 8.2 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . 137 Bibliography 139 v Abstract Applications in embedded real-time systems are required to meet their timing constraints. Deadline miss in hard real-time systems results in catastrophic effects. Thus, the worst-case performance of application plays an important role in the schedulability of hard real-time systems. However, due to the existence of micro-architectural features, such as caches, the worst-case timing analysis becomes intractable. Caches are widely employed in modern embedded real-time systems. They bridge the performance gap between the fast CPU and the slow off-chip memory. However, they also introduce timing unpredictability in real-time systems, as it is not known statically whether a memory block is in the cache or in the main memory. Existing approaches dealing with timing unpredictability of caches usually employ static cache analysis or cache locking techniques. Cache analysis statically models the cache behavior. However, it may not produce accurate results due to the existence of conservative estimation. Cache locking locks the entire cache with selected memory blocks and guarantees predictable timing. Nevertheless, such aggressive locking technique may have negative impact on the execution time, as the unlocked memory blocks cannot reside in the cache and exploit their locality. In this thesis, we propose partial cache locking technique to optimize the worst-case performance of embedded real-time systems. Partial cache locking only locks a part of the cache space, while the rest of the cache remains free and can be used by the unlocked memory blocks to exploit their cache locality. Thus, static cache analysis is still required for the unlocked cache space, while the locked cache contents are selected through accurate cost-benefit analysis. By integrating static cache analysis and cache locking, our partial cache locking approach can achieve the best of these two techniques. We first exploit the cache optimization in uni-processors. We propose static partial instruction cache locking for single task to minimize the WCET (Worstcase Execution Time), where intra-task cache conflicts are carefully handled. An optimal approach based on concrete cache state analysis and a time-efficient vi heuristic method based on abstract cache analysis are developed to select the cache contents. Substantial improvement on WCET is achieved, compared to state-of-the-art static cache analysis approach and full cache locking method. We extend our approach to multitasking real-time systems, where both intratask cache conflicts and inter-task interference are considered. Our approach takes the global effects on all task into account and selects the most beneficial memory blocks in improving the schedulability/utilization. Subsequently, we explore dynamic cache locking for single task. We propose a loop-based dynamic partial cache locking approach to minimize the WCET. Our approach can better capture the dynamic program behavior, compared to static cache locking. An ILP (Integer Linear Programming) formulation with global optimization is developed to allocate the amount of locked cache space for each loop, and the most beneficial memory blocks are selected to fill this space. Finally, we also apply partial cache locking in multi-core processors with shared cache, where the inter-core cache interference from concurrent executing tasks must also be carefully handled. Prior to cache locking, an ILP formulation based task mapping approach is proposed to optimize the WCRT (Worst-case Response Time) of multitasking applications. Based on the generated task mapping, we lock the memory blocks in the private L1 cache, which not only reduces the number of cache misses in L1 cache but also reduces the number of accesses to L2 cache. Experimental evaluation shows further improvement on WCRT for multitasking applications via cache locking. In summary, this thesis proposes and studies partial instruction cache locking in the context of different architectures and system models in embedded real-time systems. The worst-case performance of the applications is greatly improved, compared to the existing approaches. vii List of Publications • WCET-Centric Partial Instruction Cache Locking. Huping Ding, Yun Liang and Tulika Mitra. In Proceedings of the 49th annual Design Automation Conference (DAC ’12), June 2012. • Timing Analysis of Concurrent Programs Running on Shared Cache Multicores. Yun Liang, Huping Ding, Tulika Mitra, Abhik Roychoudhury, Yan Li, Vivy Suhendra. Real-Time Systems Journal, Volume 48, Issue 6, 2012. • Shared Cache Aware Task Mapping for WCRT Minimization. Huping Ding, Yun Liang and Tulika Mitra. In Proceedings of 18th Asia and South Pacific Design Automation Conference (ASP-DAC ’13), January 2013. • Integrated Instruction Cache Analysis and Locking in Multitasking Realtime Systems. Huping Ding, Yun Liang and Tulika Mitra. In Proceedings of the 50th annual Design Automation Conference (DAC ’13), June 2013. • WCET-Centric Dynamic Instruction Cache Locking. Huping Ding, Yun Liang and Tulika Mitra. In Proceedings of Design Automation and Test in Europe (DATE ’14), March 2014. viii block size can also outperform locking at L2 block size granularity, e.g., DEBIE benchmark. Locking at L2 block size can completely eliminate the access to L2 memory block in L2 cache once a memory block is locked, which leads to the reduction of shared L2 cache interference. One the other hand, locking at L1 block size granularity is more fine-grained and flexible than locking at L2 block size granularity. 7.8 Discussion A two-step framework is proposed to improve the WCRT for multitasking applications in multi-core processors with shared cache. However, we only consider homogeneous multi-core processors, and the tasks are assumed to execute in a non-preemptive fashion. In the task mapping step, we have approximations on the interference modeling and WCET computation modeling, in order to reduce the complexity of the ILP formulation. Thus, we may occasionally not achieve the best task mapping. 7.9 Summary In this chapter, we perform cache locking in multi-core processors with shared cache. Prior to cache locking, a cache aware task mapping approach is proposed to minimize the WCRT of concurrent tasks. Caches are modeled through abstract interpretation and an ILP formulation approach is employed for task mapping. Both the cache conflicts in the L2 cache and the workload balance are considered in our approach. Cache locking further minimizes the WCRT using the resultant task mapping. We statically lock the memory blocks in private L1 cache for each task. Both L1 block size granularity and L2 block size granularity are explored. Our cache locking approach not only reduces the number of cache misses in private L1 cache but also minimizes the number of accesses to shared L2 cache. Experimental results with both synthetic task graphs and realworld benchmarks show that both task mapping approach and cache locking technique substantially improve the WCRT. Our task mapping approach returns the best task mapping in most of the cases, and it is more efficient in runtime compared to an exhaustive enumeration approach that can produce optimal solution. Cache locking is complementary to task mapping and further improves the WCRT. 135 Chapter Conclusion 8.1 Thesis Contribution Timing constraint is an important feature in embedded real-time systems. Applications in real-time systems are required to meet their time deadlines, in order to guarantee proper functioning. Worst-case performance, thus becomes a crucial metric in the schedulability analysis of real-time systems. In this thesis, we study cache optimizations by proposing partial cache locking in embedded real-time systems, in order to improve the worst-case performance of applications. Our partial cache locking integrates static cache analysis and cache locking. With partial cache locking, only a portion of the cache is locked with memory blocks, while the free cache space can still be used by the unlocked memory blocks to exploit their cache locality. Accurate cost-benefit analysis is performed based on static cache analysis, in order to select the most beneficial memory blocks that can minimize the worst-case execution time. Our partial cache locking achieves the best of both static cache analysis and cache locking approach. Our partial cache locking is studied in different architectures and system models in embedded real-time systems. In uni-processors, static partial instruction cache locking is first developed for single task, in order to improve the WCET. We carefully model the intra-task cache conflict, as well as the cost and benefit by locking a memory block. An optimal approach based on concrete cache state and a time-efficient heuristic method based on abstract cache state are proposed to select the most beneficial memory blocks in improving the WCET. Then, we extend partial cache locking to multitasking real-time systems, and both intra-task and inter-task cache conflicts are carefully considered. With our approach, each task may lock a portion of the cache, while there is still 136 unlocked cache space that is shared by all the tasks in a time-multiplexed style. As the cache is shared by all the tasks, locking a memory block has global effect and can impact both WCET and CRPD. We propose a greedy selection method that iteratively select the memory blocks, where the global effect of cache locking is handled. Our approach improves the schedulability/utilization for both RMS (Rate Monotonic Scheduling) and EDF (Earliest Deadline First) scheduling policies. Static partial cache locking is also extended to dynamic cache locking in this thesis, in order to further improve the WCET for a single task. Compared to the region-based approaches that partition program into different regions, we propose a flexible loop-based dynamic cache locking approach. Our approach locks the memory blocks at the entry point of a loop and unlocks them at the corresponding exit point. Memory blocks from the same loop can be locked at different program points with consideration to global optimization of the WCET. Thus, we not only select the memory blocks to be locked, but also decide the locking points where they should be locked. At last, we also study partial cache locking in multi-core processors with shared cache. Inter-core cache conflict is considered due to the existence of shared cache. A two-step framework is proposed to minimize the WCRT. Prior to cache locking, a task mapping method is adopted to minimize WCRT. The task mapping approach considers both the workload balance and shared cache conflict. Based on the resultant task mapping, we further improve the WCRT via partial cache locking approach. 8.2 Future Directions Data cache is as important as instruction cache in embedded real-time systems, which provides fast access to the program data. Although we only study instruction cache optimizations for embedded real-time systems in this thesis, our techniques can be extended to data cache. Our partial cache locking technique relies on static cache analysis to select the beneficial memory blocks to lock. Recently, Huynh et al. [51] propose a scope-aware static data cache analysis method based on persistence analysis. They adopt the data address analysis technique proposed in [108]. With the data address analysis framework and the scope-aware abstract cache state analysis, we believe that our partial cache locking technique can be easily extended to data cache. As we have mentioned, cache locking can reduce the cache conflicts. However, cache locking cannot completely eliminate the cache conflicts. Suppose 137 there are three memory blocks m1 , m2 and m3 in a loop, and they are mapped to the same cache set of a 2-way set-associative cache. Clearly, these three memory blocks conflict in the cache set. When we lock one of them, all accesses to the locked memory blocks are cache hits, while the other two memory blocks can still conflict with each other. Recently, compiler-assisted code positioning approaches have been proposed to optimize the WCET [76, 37]. These methods change the layout of program codes, which may completely eliminate some of the cache conflicts. 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In Proceedings of the 25th IEEE International Real-Time Systems Symposium, RTSS ’04, pages 81–91, 2004. 150 [...]... corresponding time deadlines, while no timing constraint is required in generalpurpose computer systems Real- time systems that have timing constraint can be classified into two types, soft real- time systems and hard real- time systems In soft real- time systems, the timing constraint is elastic Miss of the deadline in soft real- time systems only results in loss of QoS but not the failure of systems Thus, the time. .. employed in modern embedded real- time systems It stores copies of instructions and speeds up the instruction fetch in the processors Instruction cache is accessed by the CPU almost very cycle in the processors, and it significantly in uences the average-case performance of processors Moreover, instruction cache also consumes a large part of the power in the processors [19] In embedded real- time systems, instruction. .. 3.1 Cache Analysis in Uni-processor We introduce the existing cache analysis approaches that target both intra-task cache conflict and inter-task cache interference in uni-processors 3.1.1 Intra-task Cache Conflict Analysis Cache makes the worst-case timing analysis in real- time systems challenging, as the timing is unpredictable due to the cache Conservatively assuming that all memory accesses are cache. .. dynamic cache locking for single task Finally, we consider cache optimizations in multi-core processor with shared cache 1.4 Thesis Contributions In this thesis, we perform post-compilation instruction cache optimizations via partial cache locking in embedded real- time systems We select the locked contents based on a static analysis of the program binary executable We make the following contributions in. .. partial cache locking for single task to multitasking in uni-processors, in order to improve the schedulability/utilization of real8 time systems In our approach, each task statically locks a portion of the cache, while there is still unlocked cache space that is shared by all tasks in a time- multiplexed style Locking a memory block in multitasking real- time systems in uences both WCET and CRPD (Cache- related... locking, cache locking is performed at the granularity of cache ways When a cache way is locked, all the sets in this particular way are locked Way locking is employed in [1], [2] and so on While line locking allows different number of cache lines to be locked in different cache sets Thus, compared to way locking, line locking is more flexible and fine-grained Line locking is used in [6], [5] and so on Cache. .. feature, there are also real- time constraints in embedded systems, such as timing constraint With the timing constraint, embedded systems are not merely required to produce correct results, but also have to meet the requirement of real- time response time, in order to guarantee the quality of service (QoS) or proper functioning In other words, applications on embedded real- time systems need to complete... unpredictable timing in embedded real- time systems In order to deal with the timing unpredictability problem of cache, many approaches have been proposed, including static cache analysis and cache locking method Static Cache Analysis Static cache analysis statically analyzes the program and models the cache, in order to capture the cache behavior of the program It is commonly used to model the intra-task cache. .. carefully handled in timing analysis Instruction cache modeling attracts lots of attentions in micro-architectural modeling One of the most well-known approach for instruction cache modeling is abstract interpretation [101] This method is also used in modeling of multi-level cache [48] and shared cache [62] In abstract interpretation approach, abstract cache states are defined at each program point to represent... al [47] reduce the inter-core interference in the shared cache through bypassing static single usage blocks from the shared caches via compile time analysis In [96] and [75], cache partitioning is employed in the shared cache to eliminate intercore cache interference However, cache partitioning may limit the shared cache performance, as each task can only use a portion of the shared cache 1.3 Research . types, soft real-time systems and hard real-time systems. In soft real-time systems, the timing constraint is elastic. Miss of the deadline in soft real-time systems only results in loss of QoS but. in cache misses, due to such intra-task cache conflict in T . In preemptive multitasking real-time systems, multiple tasks are scheduled on the same processor. Inter-task interference in the cache. for multitasking applications via cache locking. In summary, this thesis proposes and studies partial instruction cache lock- ing in the context of different architectures and system models in embedded real-time