Microelectronic circuit design 3rd edition by r jaeger solutions mmzzhh

Filter Capacitor iv We must choose between use of a center-tapped transformer full-wave or two extra diodes bridge.. At a current of 15 A, the diodes are not expensive and a four-diode b

Electronic door bell

Electronic gas pump

Pagers Personal computer Personal planner/organizer (PDA) Radar detector

Broadcast Radio (AM/FM/Shortwave) Razor

Satellite radio receiver Security systems Sewing machine Smoke detector Sprinkler system Stereo system Amplifier

Receiver

Stud sensor Talking toys Telephone Telescope controller Thermostats Toy robots Traffic light controller

TV receiver & remote control Variable speed appliances Blender Drill Mixer

Fan Vending machines Video game controllers Wireless headphones & speakers Wireless thermometer

Workstations Electromechanical Appliances*

Air conditioning and heating systems Clothes washer and dryer

0.1548= 6.46 years

1.6 F = 8.00x10−0.05806 2020−1970( )μm =10 nm

No, this distance corresponds to the diameter of only a few atoms Also, the wavelength of the

radiation needed to expose such patterns during fabrication is represents a serious problem

1.7

From Fig 1.4, there are approximately 600 million transistors on a complex Pentium IV

microprocessor in 2004 From Prob 1.4, the number of transistors/μP will be 8.85 x 1010

in

2020 Thus there will be the equivalent of 8.85x1010/6x108 = 148 Pentium IV processors

A 4 digit readout ranges from 0000 to 9999 and has a resolution of 1 part in 10,000 The

number of bits must satisfy 2B ≥ 10,000 where B is the number of bits Here B = 14 bits

1.25 The Thévenin equivalent resistance is found using the same approach as Problem 1.24,

1.26 (a)

R

βi v

R

βi v

6 kHz

1.41 Band-pass amplifier

f20

v O()t =10x5sin 2000( πt)+10x3cos 8000( πt)+ 0x3cos 15000( πt)

v O()t = 50sin 2000[ ( πt)+ 30cos 8000( πt) ] volts

1.44

v O()t = 20x0.5sin 2500( πt)+ 20x0.75cos 8000( πt)+ 0x0.6cos 12000( πt)

v O()t = 10.0sin 2500[ ( πt)+15.0cos 8000( πt) ] volts

1.45 The gain is zero at each frequency: vo(t) = 0

(a)

5V 1( −.05)≤ V ≤ 5V 1+ 05( ) or 5.75V≤ V ≤ 5.25V

V = 5.30 V exceeds the maximum range, so it is out of the specification limits

(b) If the meter is reading 1.5% high, then the actual voltage would be

V meter =1.015V act or Vact = 5.30

1.015= 5.22V which is within specifications limits

V2+

V

1.56 For one set of 200 cases using the equations in Prob 1.53

V =10 * 0.95 + 0.1* RAND()( ) R1= 22000 * 0.9 + 0.2 * RAND()( )

R1= 4700 * 0.9 + 0.2 * RAND()( ) R3 =180000 * 0.9 + 0.2 * RAND()( )

1.57 For one set of 200 cases using the Equations in Prob 1.54:

E BT

3

1062.8exp

For silicon, B = 1.08 x 1031 and EG = 1.12 eV:

cm A Q

j

2

10/

6 7

sec104

0

cm

MA cm

A x cm cm

C Qv

V cm

x

V E

K−3cm−6, k = 8.62x10-5eV/K and EG=1.12eV

This is a transcendental equation and must be solved numerically by iteration Using the HP solver routine or a spread sheet yields T = 2701 K Note that this temperature is far above the melting temperature of silicon

eV/K and EG=1.12eV

Using MATLAB as in Problem 2.5 yields T = 316.6 K

2.16

Si B

Since Ge is from column IV, acceptors come from column III and donors come from column

V (a) Acceptors: B, Al, Ga, In, Tl (b) Donors: N, P, As, Sb, Bi

A j

22 2

3 14

3 11 3

16 16

16

10502104

1010

4

102210

410105

/cm x

x

p

n | n /cm x

N

N

p

/cm x

n /cm

x x

N : N

N

N

i D

A

i D

No, the result is incorrect because of loss of significant digits

within the calculator It does not have enough digits

2.27

(a) Since boron is an acceptor, NA = 6 x 1018/cm3 Assume ND = 0, since it is not specified

The material is p-type

3 3

18

6 20 2

3 18

i 3

18 3

10

7.1610

6

10

and 10

6

So

2n

>>

/106

and10

re, temperatu

room

At

/cm /cm

x

/cm p

n n /cm

x

p

cm x

N N /cm

n

i

D A i

17

6 20 2

3 17

i 3

17 3

10 i

33310

3

10

and 10

3

So

2n

>>

/103

and/

10nre, temperatu

room

At

/cm /cm

x

/cm n

n p /cm

x

n

cm x

N N cm

i

A D

3 3

18

6 20 2

3 18

i 3

18 3

10 i

71610

6

10

and 10

6

So

2n

>>

/106

and/

10nre, temperatu

room

At

(b)

/cm /cm x

/cm p

n n /cm

x

p

cm x

N N cm

i

D A

(a) Phosphorus is a donor, and boron is an acceptor ND = 2 x 1017/cm3, and NA = 5 x 1017/cm3 Since NA > ND, the material is p-type

3 3

17

6 20 2

3 17

i 3

17 3

10

33310

3

10

and 10

3

So

2n

>>

/103

and10

re, temperatu

room

At

(b)

/cm /cm

x

/cm p

n n /cm

x

p

cm x

N N /cm

n

i

D A i

ND = 4 x 1016/cm3 Assume NA = 0, since it is not specified

2.3 x 10 15 1330 3.06 x 10 18

To change the resistivity to 0.25 ohm-cm:

Additional acceptor concentration = 1.1x1017- 1.7x1016 = 9.3 x 1016/cm3

(b) If donors are added:

n-type silicon

p-type silicon

Si02Photoresist

Structure after exposure and

development of photoresist layer

Mask

n-type silicon p-type silicon

Structure following ion implantation of n-type impurity

n +

Ion implantation

Side view

Top View Mask for ion implantation

06 -1.003E+04 9.426E-04 9.992E-

16 -1.003E+04

0.8 0.6

0.4 0.2

1.039 7.606E-15

V D I D -Measured I D -Calculated Squared Error

Total Squared Error 1.1622E-06

5 anode contacts and 14 cathode contacts

Resistance of anode contacts =10Ω

-1 -2 -3

-4

-5

-6

-1 mA -2 mA (b) Q-point

-1 -2 -3

-4

-5

-6

-1 mA (b) Q-point

iD

(c) Q-point

-1 -2 -3 -4

The load line equation: V = iD R + vD We need two points to plot the load line

(a) V = 6 V and R = 4kΩ: For vD = 0, iD = 6V/4 kΩ = 1.5 mA and for iD = 0, vD = 6V Plotting this line on the graph yields the Q-pt: (0.5 V, 1.4 mA)

(b) V = -6 V and R = 3kΩ: For vD = 0, iD = -6V/3 kΩ = -2 mA and for iD = 0, vD = -6V Plotting this line on the graph yields the Q-pt: (-4 V, -0.67 mA)

(c) V = -3 V and R = 3kΩ: Two points: (0V, -1mA), (-3V, 0mA); Q-pt: (-3 V, 0 mA)

(d) V = +12 V and R = 8kΩ: Two points: (0V, 1.5mA), (4V, 1mA); Q-pt: (0.5 V, 1.4 mA) (e) V = -25 V and R = 10kΩ: Two points: (0V, -2.5mA), (-5V, -2mA); Q-pt: (-4 V, -2.1 mA)

1 2 3 4 5 6 7 -1

-2 -3 -4 -5

Load line for (b) Q-Point

(-4V,-2.1 mA)

(e)

(c)

Q-Point (-3V,0 mA)

(d) Q-Point (0.5V,1.45 mA)

Using the equations from Table 3.1, (f = 10-10-9 exp , etc.)

VD = 0.7 V requires 12 iterations, VD = 0.5 V requires 22 iterations,

VD = 0.2 V requires 384 iterations - very poor convergence because the second iteration (VD = 9.9988 V) is very bad

1.0000E+00 -9.991E+03 -1.000E+04

9.2766E-04 1.496E-01 -1.003E+04

9.4258E-04 3.199E-06 -1.003E+04

9.4258E-04 9.992E-16 -1.003E+04

9.4258E-04 9.992E-16 -1.003E+04

Ideal diode model: ID = 1V/10kΩ = 100μA; (100μA, 0 V)

Constant voltage drop model: ID = (1-0.6)V/10kΩ = 40.0μA; (40.0μA, 0.6 V)

+

-V

I 1 kΩ 1.2 k Ω

1.5 V 1.2 V

0.3 V

+ -

+

-V

I 2.2 k Ω

(a) Ideal diode model: The 0.3 V source appears to be forward biasing the diode, so we will assume it is "on" Substituting the ideal diode model for the forward region yields

I =

2.2kΩ 0.3V = 0.136 mA This current is greater than zero, which is consistent with the diode

being "on" Thus the Q-pt is (0 V, +0.136 mA)

Ideal Diode:

0.3 V

+ -

+

-V I

2.2 k Ω

CVD:

0.3 V +

-0.6 V

I 2.2 k Ω

+ -

on

V

(b) CVD model: The 0.3 V source appears to be forward biasing the diode so we will assume it

is "on" Substituting the CVD model with Von = 0.6 V yields

-I=0 2.2 k Ω

- V +

(c) The second estimate is more realistic 0.3 V is not sufficient to forward bias the diode into significant conduction For example, let us assume that IS = 10-15 A, and assume that the full 0.3 V appears across the diode Then

16kΩ = 0.625 mA (c) Diode is reverse biased : I = 0 | V = −5 +16kΩ I( )= −5 V | VD= −10 V

(d ) Diode is reverse biased : I = 0 | V = 7 −16kΩ I( )= 7 V | VD= −10 V

(c) Diode is reverse biased : I = 0 | V = −5 +16kΩ I( )= −5 V | VD= −10 V

(d ) Diode is reverse biased : I = 0 | V = 7 −16kΩ I( )= 7 V | VD= −10 V

(c) Diode is reverse biased : I = 0 A | V = −5 +100kΩ I( )= −5 V | V D = −10 V

(d ) Diode is reverse biased : I = 0 A | V = 7 −100kΩ I( )= 7 V | V D = −10 V

(b)

(c) Diode is reverse biased : I = 0 | V = −5 +100kΩ I( )= −5 V | V D = −10 V

(d ) Diode is reverse biased : I = 0 | V = 7 −100kΩ I( )= 7 V | V D = −10 V

MODEL DIODE DIODE DIODE

ID 9.90E-04 -1.92E-12 7.98E-04

VD 7.14E-01 -1.02E+00 7.09E-01

NAME D1 D2 D3

MODEL DIODE DIODE DIODE

ID 4.74E-04 -4.22E-13 2.67E-11

VD 6.95E-01 -4.21E-01 2.63E-01

NAME D1 D2 D3

MODEL DIODE DIODE DIODE

ID 8.79E-03 1.05E-03 7.96E-04

VD 7.11E-01 7.16E-01 7.09E-01

NAME D1 D2 D3

MODEL DIODE DIODE DIODE

ID -4.28E-13 -8.55E-13 1.15E-03

VD -4.27E-01 -8.54E-01 7.18E-01

For all cases, the results are very similar to the hand analysis

MODEL DIODE DIODE DIODE

ID 1.47E-03 -4.02E-12 9.35E-04

VD 6.65E-01 -4.01E+00 6.53E-01

The simulation results are very close to those given in Ex 3.8

i D -6 -5 -4 -3 -2 -1

16.7ms 1ms

(a) V dc = − V( P −V on)= − 6.3 2 −1( )= −7.91V (b) C = I T

V r =7.910.55

10.5

260

+0.000e+000 +10.000m +20.000m +30.000m +40.000m +50.000m +60.000m +70.000m

-10.000 -5.000 +0.000e+000 +5.000 +10.000

SPICE Graph Results: VDC = 9.29 V, Vr = 1.05 V, IP = 811 A, ISC = 1860 A

2601

1.3ms = 923A

SPICE Graph Results: VDC = -6.55 V, Vr = 0.58 V, IP = 150 A, ISC = 370 A

Note that a significant difference is caused by the diode series resistance

3.94

(a) V dc = − V( P −V on)= − 6.3 2 −1( )= −7.91V (b) C = I T

V r =7.910.25

10.5

1

400= 0.158F (c) PIV ≥ 2V P = 2 ⋅ 6.3 2 =17.8V (d ) I surge =ωCV P = 2π( )400 (0.158) ( )6.3 2 = 3540 A

2400

194.3μs = 839A

3.95

(a) V dc = − V( P −V on)= − 6.3 2 −1( )= −7.91V (b) C = I T

V r =7.910.25

10.5

2

105

10.377μs = 839A

3.96

160

Simulation Results: VDC = -12.9 V, Vr = 0.20 V, IP = 33.3 A, ISC = 362 A RS results in a

significant reduction in the values of IP and ISC

10.25

3.112

3.3-V, 15-A power supply with Vr ≤ 10 mV Assume Von = 1 V

Filter Capacitor

(iv) We must choose between use of a center-tapped transformer (full-wave) or two extra diodes (bridge) At a current of 15 A, the diodes are not expensive and a four-diode bridge should be easily found The final choice would be made based upon cost of available components

3.113

200-V, 3-A power supply with Vr ≤ 4 V Assume Von = 1 V

Filter Capacitor

(i) The the half-wave rectifier requires a larger value of C which may lead to more cost

(ii) The PIV ratings are all low enough that they do not indicate a preference for one circuit over another

(iii) The peak current values are lower for the full-wave and full-wave bridge rectifiers and also indicate an advantage for these circuits

(iv) We must choose between use of a center-tapped transformer (full-wave) or two extra diodes (bridge) At a current of 3 A, the diodes are not expensive and a four-diode bridge should be easily found The final choice would be made based upon cost of available components

3.114

3000-V, 1-A power supply with Vr ≤ 120 V Assume Von = 1 V

Filter Capacitor

(i) A series string of multiple capacitors will normally be required to achieve the voltage rating

(ii) The PIV ratings are high, and the bridge circuit offers an advantage here

(iii) The peak current values are lower for the full-wave and full-wave bridge rectifiers but neither is prohibitively large

(iv) We must choose between use of a center-tapped transformer (full wave) or extra diodes (bridge) With a PIV of 3000 or 6000 volts, multiple diodes may be required to achieve the require PIV rating

For this case, simulation yields S = 3 ns

*Problem 3.145(b) - Diode Switching Delay

In case (a), the charge in the diode does not have time to reach the steady-state value given by Q

= (1mA)(50ns) = 50 pC At most, only 1mA(7.5ns) = 7.5 pC can be stored in the diode Thus is turns off more rapidly than predicted by the storage time formula It should turn off in approximately t = 7.5pC/3mA = 2.5 ns which agrees with the simulation results In (b), the diode charge has had time to reach its steady-state value Eq (3.103) gives: (50 ns) ln (1-1mA/(-3mA)) = 14.4 ns which is close to the simulation result

3.119

I C =1−10−15

exp 40V( )C −1[ ] A | For V C = 0, I SC =1A

(b) For ISC, the external currents cannot exceed the smallest of the short circuit current

of the individual diodes Thus, I SC = min 1.05A,1.00A,0.95A[ ]= 0.95 A

Note that diode three will be reversed biased in part (b)

Using the computer to find VC yields VC = 0.7768 V, IC = 0.9688 A, and Pmax = 7.53 Watts

cm2 | C ox

" = 69.1nF

cm2

50nm 20nm= 691nF

V2 | K n

' = 34.5μA

V2

50nm 5nm = 345μA

+0.2 V I

D G

S B

D G

S

B

+

V

4.14

K n = K n'W

L a( ) W = K n

K n' L= 4mA / V2100μA / V2(0.5μm)= 20 μm b( ) W = 800μA / V2

100μA / V2(0.5μm)= 4 μm

4.15

( ) V GS −V TN = 3 -1 = 2V and V DS = 3.3 | V DS > V( GS −V TN) so the saturation region is correct

VGS = 2 - (-0.5) = 2.5 V, VGS - VTN = 2.5 - 1 = 1.5 V, and VDS = 0.5 V > triode region

(f) The source and drain of the transistor are again reversed because of the sign change in VDS Assuming the voltages are defined relative to the original S and D terminals as in Fig P4.11(b),

VGS = 3 - (-6) = 9 V, VGS - VTN = 9 - 1 = 8.0 V, and VDS = 6 V > triode region

(e) The source and drain of the transistor are now reversed because of the sign change in VDS

Assuming the voltages are defined relative to the original S and D terminals as in Fig 4.54(b),

VGS = 2 - (-0.5) = 2.5 V, VGS - VTN = 2.5 – 0.7 = 1.8 V, and VDS = 0.5 V > triode region

(f) The source and drain of the transistor are again reversed because of the sign change in VDS

Assuming the voltages are defined relative to the original S and D terminals as in Fig 4.54(b),

VGS = 3 - (-3) = 6 V, VGS - VTN = 6 – 0.7 = 5.3 V, and VDS = 3 V > triode region

D

S B G

D G S B

B D

G

VDS = 3.3V, VGS – VTN = 1.3 V; VDS > VGS - VTN so the transistor is saturated

Starting with the solution from part (a) and solving iteratively yields VGS = 1.20772 V and ID =

108 μA, essentially no change

Starting with the solution from part (a) and solving iteratively yields VGS = 1.3925 V and IDS =

212 μA, essentially no change

4.33

(a) Since VDS = VGS and VTN > 0 for both transistors, both devices are saturated

I = I D1 = I D 2 or K n

'

2

101

'

2

W L

I = I D1 = I D 2 or K n

'

2

251

μA

V2

251

'

2

W L

Since VDS = VGS, and VTN < 0 for an NMOS depletion mode device, VGS - VTN will be greater

than VDS and the transistor will be operating in the triode region

G S

(d) In this circuit, the drain and source terminals of the transistor are reversed because of the

power supply voltage, and the current direction is also reversed However, now VDS = VGS and

since the transistor is a depletion-mode device, it is still operating in the triode region

4.40 See figures in previous problem but use W/L = 20/1

(a) If the transistor were saturated, then I D =25x10−6

2

201

= 250 μA but this would require

a power supply of greater than 25 V Thus the transistor must be operating in the triode region

10V −V DS

−6 201

(b) In this circuit, the drain and source terminals of the transistor are reversed because of the

power supply voltage, and the current direction is also reversed However, now VDS = VGS and

since the transistor is a depletion-mode device, it is still operating in the triode region