FPGA BASED DESIGN AND IMPLEMENTATION FOR OPTICAL TRANSPORT NETWORKS

VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY UNIVERSITY OF SCIENCE HA VAN KHA LY FPGA-BASED DESIGN AND IMPLEMENTATION FOR OPTICAL TRANSPORT NETWORKS Master Thesis in Electronic Engineering (Specification in Microelectronics & IC Design) SUPERVISOR: Dr BUI HUU PHU HCM CITY, 2010 ii ACKNOWLEDGEMENT I gratefully acknowledge the following individuals for helping me to complete my thesis report First of all, I would like to take this opportunity to express my deepest gratitude to my supervisor, Dr Bui Huu Phu, for his guidance, help and support the theory and concept of fiber optical system design and encouragement throughout the period of completing my project Thanks to all of my lecturers in HCM University of Science such as Prof Dr Dang Luong Mo, Prof Dr Nguyen Huu Phuong, Prof Dr Dinh Si Hien, Dr Bui Trong Tu and Dr Huynh Huu Thuan for their knowledge of the microelectronic, IC design and their patiences during my master course I have learned a lot from them I would like to thank to my brother, Dr Ha Hoang Kha, for all his help me through my thesis, especially in providing me the IEEE papers and the related softwares I acknowledge the kindly supports from Arrive Technologies Viet Nam The thesis might be impossibe without the supports from the company Particularly, I also would like to thank Mr Do Dinh Duc for his kind assistant, suggestion on explaining FPGA implementation, and for providing an excellent atmosphere at Arrive technologies Lab, and guidance especially in using AT FPGA board version 1.0 development board and configuration of the related software Finally, I sincerely thank to all my friends and all those whoever has helped me either directly or indirectly in the completion of my final year project and thesis ABSTRACT The thesis presents an approach to system design and implementation for optical transport networks The design of the system based on the Field Programmable Gate Array (FPGA) and Gigabit optical network is discussed Gigabit optical network interfaces provide fixed functionality and are optimized for sending and receiving large packets All modules are designed using Verilog Hardware Description Language (HDL) and implemented using AT FPGA board version 1.0 The board is connected to computer and Quartus II Version 8.0 is used to design, compile and implement for the hardware All processing is executed in AT FPGA version 1.0 board and only requires the input data to the hardware throughout interfaces To test and analyse results, input and output data are displayed to computer, and the results are compared using HyperTerminal or Telnet command Softwares and tools used in this project include Verilog HDL Design Entry Altera Quartus II 8.0 Some software tools are used to assist the design process and downloading process into Altera FPGA chip Stratix II EP2S180, while AT FPGA board version 1.0 is used to implement the designed module The experimental results at Gigabit Ethernet receiving interface indicate that the optical interface can receive all packet sizes and store them in SDRAM at Gigabit Ethernet line rate TABLE OF CONTENTS ABSTRACT CHAPTER : INTRODUCTION 1.1 1.2 1.3 1.4 Introduction Project objectives 11 Project scope 11 Thesis outline 12 CHAPTER : FPGA AND HDL CHIP DESIGN 14 2.1 2.2 2.3 2.4 Introduction 14 FPGA architecture overview 15 Stratix II FPGA 17 Hardware description language 21 2.4.1 Introduction 21 2.4.2 Verilog HDL Structure 22 CHAPTER : PRINCIPLES AND APPLICATIONS OF OPTICAL COMMUNICATIONS 30 3.1 3.2 3.3 Optical fiber communication technology 30 System overview, trends and advances 34 Standard and devices requirements 37 3.3.1 Standard 37 3.3.2 Devices requirements 41 CHAPTER : FPGA-BASED DESIGN AND IMPLEMENTATION 47 4.1 4.2 4.3 4.4 Overview of the design 47 Software design 51 Hardware design 52 4.3.1 High speed 8B/10B Encoder and Decoder Design 66 4.3.2 Details of the Encoding Process 67 4.3.3 FIFO Functionality 72 Download the design into hardware 78 CHAPTER : SIMULATION RESULTS AND EXPERIMENTAL TESTS ON FPGA CHIPS 80 5.1 5.2 5.3 Introduction 80 Individual component test 80 5.2.1 8B/10B encoder and decoder implemetation and simulation results 80 5.2.2 FIFO Implemetation and simulation results 86 5.2.3 System compilation 93 5.2.4 Breadboard prototype test 94 System level testing for transmitter and receiver 97 5.3.1 Optical link test 97 5.3.2 Gigabit Ethernet test 97 CHAPTER : CONCLUSION AND FUTURE WORK 100 6.1 6.2 Conclusion 100 Future work 101 REFERENCES 102 List of Figures Figure 2.1: Structure of an FPGA 15 Figure 2.2: SRAM-controlled Programmable Switches 16 Figure 2.3 : Actel Antifuse Structure 17 Figure 2.4: Top view Stratix II 18 Figure 2.5: Stratix II Block Diagram 19 Figure 2.6: 1,020-PIN FPGA Package Outline 20 Figure 2.7: Verilog 21 Figure 3.1: Optical transmitter and receiver 31 Figure 3.2: Fiber to the X (FTTX) 33 Figure 3.3: Enterprise LAN Topology 33 Figure 3.4: Today’s networks 34 Figure 3.5: Total Traffic Bandwidth Increases 35 Figure 3.6: Convergence of Ethernet and Optical transports 35 Figure 3.7: Overview of optical transport networks 36 Figure 3.8: Relationship of IEEE 802.3 layering model to OSI reference model 39 Figure 3.9: SPLC-20-4-X-BX 41 Figure 3.10: Diagram of host board connector block pin numbers and names 42 Figure 3.11: Block diagram of SFP 44 Figure 3.12: Single-mode fiber and multimode fiber 45 Figure 3.13: HDMP-1636A/46A/T1636A transceiver 46 Figure 4.1: Design flow using Quartus II 48 Figure 4.2: Design flow 48 Figure 4.3: Full IC Design Flow 51 Figure 4.4: Quartus II Software Basic Design Flow 52 Figure 4.5: Stratix II block diagram 54 Figure 4.6: Top-level block diagram of the system 55 Figure 4.7: FPGA Stratix II 56 Figure 4.8: Block diagram of Gigabit Ethernet 57 Figure 4.9: Block diagram of MAC 57 Figure 4.10: MAC control frame format 58 Figure 4.11: Format of frame preamble 59 Figure 4.12: Shift register generating CRC-8 60 Figure 4.13: Functional block diagram 65 Figure 4.14: The 8B/10B Encoder and decoder in a system stransmission 66 Figure 4.15: The 8B/10B coding scheme 67 Figure 4.16: State machine of running disparity 71 Figure 4.17: First-in, first-out functionality gives a FIFO register file a specific directionality 72 Figure 4.18: A typical block diagram of a synchronous FIFO 74 Figure 4.19: The illustrative examples of FIFO occupancy 75 Figure 4.20: A typical block diagram of a asynchronous FIFO 76 Figure 4.21: FIFO state machine transition diagram 77 Figure 4.22: FPGA daughter board 78 Figure 4.23: AT FPGA mother board and daughter board 79 Figure 4.24: The Gigabit Ethernet fibre optical connection 79 Figure 5.1: Encoder Block Diagram 81 Figure 5.2: Decoder Block Diagram 81 Figure 5.3: Schemetic Symbol of an 8B10B Encoder 82 Figure 5.4: Schemetic Symbol of an 8B10B Decoder 83 Figure 5.5: Encoder 8B10B Timing Diagrams 85 Figure 5.6: Decoder 8B10B Timing Diagrams 85 Figure 5.7: Schemetic Symbol of an Asynchronous FIFO 87 Figure 5.8: Initial write operations to an FIFO 91 Figure 5.9: Read and Write Operations to an Almost Full FIFO 92 Figure 5.10: Read and Write Operations to an almost empty FIFO 93 Figure 5.11: Full compilation was successful report 93 Figure 5.12: Linux System login 94 Figure 5.13: Load FPGA and show status 94 Figure 5.14: Data receive after sending messages 95 Figure 5.15: Show data in buffer 95 Figure 5.16: Clear data in buffer 96 Figure 5.17: The connection was tested 96 Figure 5.18: The disconnection was tested 96 Figure 5.19: System connection test with telnet 97 Figure 5.20: Wireshark Preferences 98 Figure 5.21: Wireshark Options 98 Figure 5.22: Command window 99 Figure 5.23: The sent packet and the received packet 99 List of Tables Table 2.1: Stratix II FPGA EP2S180 features 18 Table 3.1: Ethernet Communication Standards 37 Table 3.2: Common Fiber Optic Attachment options for standard 802.3z 38 Table 3.3: Diagram of Host Board Connector Block Pin Numbers and Names 43 Table 4.1: 3-bit to 4-bit Encoding Values 69 Table 4.2: 5-bit to 6-bit Encoding Values 69 Table 4.3: 8B/10B encoding/decoding mapping table 70 Abbreviation AES Advanced Encryption Standard APON ATM Passive Optical Network ALM Adaptive Logic Module ALU Arithmetic Logic Unit APD Avalanche Photodiode ASIC Application Specific Integrated Circuit BPON Broadband Passive Optical Network CAD Computer-Aided Design CDR Clock Data Recovery CMOS Complementary Metal-Oxide-Semiconductor CPLD Complex Programmable Logic Device DSL Digital Subcriber Line DTE Data Terminal Equipment EDA Electronic Design Automation EPON Ethernet based Passive Optical Network FIFO First-In First-Out FIR Finite Impulse Response FPGA Field Programmable Gate Array FTTH Fiber To The Home GMII Gigabit Media Independent Interface G-PON Gigabits Passive Optical Network HDL Hardware Description Language I/O Input/Output IC Integrated Circuit IEC Very-Large-Scale Integration IEEE Institute Of Electrical And Electronics Engineers ISI Intersymbol Interference ITU-T International Telecommunication Union - Telecommunication LAN Local Area Network LD Laser Diode LED Light Emitting Diode LLC Logical Link Control MAC Media Access Control MBd Megabaud MDI Medium Dependent Interface MMF Multi-Mode Fibers OSI Open Systems Interconnection PAL Programmable Array Logic PCS Physical Coding Sublayer PHY Gigabit Physical Layer PIN Positive-Intrinsic-Negative PLLs Phase-Locked Loops PMA Physical Medium Attachment PMD Physical Medium Dependent PON Passive Optical Network QDR Quad Data Rate RAM Random Access Memory RS Reconciliation Sublayer RTL Register Transfer Level SDRAM Synchronous Dynamic Random Access Memory SERDES Serialize/Deserialize (Serdes) SFP Small Form Factor Pluggable SMF Multi-Mode Fibers STM Synchronous Transport Module VLSI Very-Large-Scale Integration VOD Video On Demand CHAPTER 1: INTRODUCTION T his chapter introduces the motivation and objectives of this thesis about the optical transport implementation based on Field Programmable Gate Array Description on the available hardware for implementation is presented The problem statement of the project will also be carried out in this thesis The outline of the thesis is provided 1.1 Introduction Recently, there has been a great demand of the high-speed data transmission due to the emerging applications in digital communications such as high quality audio, video transmission [5], [12] The development of technology which can support the high data rate transmission of various applications is of considerable interest Among the advanced transmission technologies, the optical fiber systems are the suitable choice due to their potential advantages The optical transport networks enable to transmit more information than conventional cable networks In addition, the advances of signal processing techniques allow to implement the hardware for the high-speed data transmission efficiently There are several methods to implement the system One of the methods to implement the system is using FPGAs (Field Programmable Gate Arrays) FPGAs are the fastest, smallest, and shortest way to implement into hardware This method is flexibility of design process and the shorter time to market for the chip design [4], [18] The disadvantages of using this hardware are it needs memory and other peripheral chips to support the operation Besides that, it uses the most power usage and memory space, and would be the slowest in terms of time to produce the output compared to other hardwares 5.2.2.2 Behavior of Status Signals The activation of the ACLR, asynchronous initialization (reset), will force all four FIFO flags to the active (high) state On the first WR_CLK after the release of ACLR the FULL flag will become inactive, indicating that the FIFO is now ready to accept write operations EMPTY is deactivated on a rising edge of the RD_CLK following the first and second writes respectively Optional handshake signals are provided to simplify user control logic interacting with the FIFO Note that all of these handshake signals are synchronous to their respective clock domains and indicate the acknowledgment or rejection of requests during the prior rising clock edge The data count outputs (WR_USED and RD_USED) support the generation of user programmable flags Like all other FIFO outputs, the counts are synchronized to their respective clock domains and should be sampled only by logic operating on the same (or a synchronous) clock The data count vectors have clock latency and should not be used as substitutes for the FULL or EMPTY The clock latency of the counts in their respective clock domains is one cycle For example, the WR_USED does not reflect the impact of a write operation performed as a result of a request (WR_REQ active) during the prior clock cycle WR_USED and RD_USED values are not guaranteed to produce a precise representation of the FIFO contents at a particular point in time These values should be used as a gauge to determine the FIFO status The latency for operations in the opposing clock domain can be up to three clock cycles For example, in the case of the WR_USED, read operations that may have been performed during the immediate three prior RD_CLK periods will not be reflected in the data count vector This latency results from a design trade-off between clock frequency and count accuracy and is not as limiting as it may at first appear 89 We will analyze the simulation results to illustrate the FIFO functional operations Intial write operation to an FIFO: simulation results from ns to ns Figure 5.8 shows the functional simulation resuls for an initial write operation to an emplty FIFO from ns to 160 ns (1) At first, the aclr signal is asserted (actived), the all outputs are clear (2) At 200 ps, the wreq signal is asserted While the intial state of wrfull is high, the data are not written (3) At 450 ps, the wrfull is low, the date value 00000000 is written into the FIFO (4) At 550 ps, the wrused signal increments from 00000 (0 in Decimal) to 00001 (1 in Decimal) Latency is wrreq to wrused: wrclk cycle At the same time, the wrreq signal is high and therefore, the data value 00101011 is written (5) At 650 ps, the wrused signal increments from 00001 (1 in Decimal) to 00010 (2 in Decimal) (6) At 850 ps, the rdused counter increments from 00000 to 00001 Latency is wrclk + next rdclk cycles At this time, the rdreq is at active level, read operations should occurs, and the siganal value 00000000 outputs on the rddat pins (7) At 950 ps, the rdused is still 00001 because the data is written to FIFO at 550 ps The rdreq is high level and, hence, the data value 00101011 is read out (8) At 1050 ps, the rdused reduces from 00001 to 0000 Latency is rdreq to rdused: rdclk cycle 90 Figure 5.8: Initial write operations to an FIFO Read and Write Operations to an Almost Full FIFO: Simuation Results (36 ns to 40 ns) Figure 5.9 shows the functional simulation results for read and write operations into an alsom full FIFO from 36 ns to 40 ns It shows detailed behaviour of the wrfull, wrused, rdempty and rdused (1) At 37650 ps, the wrused signal is 01111 (15 in Decimal) (2) At 37750 ps, the wrreq is asserted, the data value 00010011 is writen in the memory, but the wrused signal is not still 01111 because the other data is read out at time 37345 ps (3) At 37850 ps, the wrreq is high, the wrful signal is asserted Latency is wreq to wrful: wrclk cycles And the wrused signal is 10000 at 37950 ps (The most significant bit of value indicates that the memory is full) (4) At 38050 ps, the wrused signal becomes to 01111 because the memory is read out at time 37650 ps 91 Figure 5.9: Read and Write Operations to an Almost Full FIFO Read and Write Operation to an Empty FIFO: Simuation Results (52 ns to 53 ns) Figure 5.10 illustrates the functional simulation results for read and write operations into an alsom empty FIFO from 52 ns to 53 ns It shows detailed behaviour of the wrfull, wrused, rdempty and rdused (1) At time 52150 ps the rdused is 00001 As the rdreq is high, the data value 01010100 outputs on the rddata pins, the FIFO becomes empty and the redmpty is asserted The rdused becomes 00000 at 52250 ps because the latency is rdclk clycle (2) At 52250 ps the rdreq is high, but the data values on the rddata are unchanged because rdempty signal is high 92 Figure 5.10: Read and Write Operations to an almost empty FIFO 5.2.3 System compilation Figure 5.11: Full compilation was successful report 93 5.2.4 Breadboard prototype test The first test performed on the breadboard prototype was to verify that the power on detection circuit worked properly The input voltage to the tag was connected to a function generator configured to generate a - 48 V DC Then, configuring the Board with the Hardware Design: To program the Stratix II GX FPGA with the hardware image for the design, perform the following steps: Open a command window to start the OS and login shown in Figure 5.12 Figure 5.12: Linux System login Change to the top-level directory of the unzipped design files, load FPGA which can load the file rbf Figure 5.13: Load FPGA and show status 94 Type the command, to send data and show reiceiving data after the plug and unplug the fibre opitcal cable Figure 5.14: Data receive after sending messages Figure 5.15: Show data in buffer 95 Figure 5.16: Clear data in buffer Figure 5.17: The connection was tested Figure 5.18: The disconnection was tested 96 5.3 System level testing for transmitter and receiver 5.3.1 Optical link test After the individual components on the tag were verified as working properly, the optical link test was checked 5.3.2 Gigabit Ethernet test An end-to-end connection between the development board and a powerful desktop PC was setup to measure the bandwidth of the Gigabit Ethernet as shown in Figure 5.19 Download and Test the Project: Open a Hyperterminal window with the required settings For the correct settings, see Hyperterminal Settings Figure 5.19: System connection test with telnet 97  Turn on the AT FPGA board  Open Wireshark on the PC to be used for testing You can use any PC with a Gigabit Ethernet network card installed and working  From the menu select "Edit->Preferences" In the dialog box that opens, select "User Interface->Columns" and set the columns as shown in the screenshot below Then click "OK" Figure 5.20: Wireshark Preferences From the menu select "Capture->Options" In the dialog box that opens, select the Gigabit Ethernet network card to which you will connect the FPGA board, then click "Start" Figure 5.21: Wireshark Options Connect the CAT5 Ethernet cable between the FPGA board and the PC running Wireshark You should notice that the Ethernet connection LEDs light up on both 98 the FPGA board and the PC The connection LEDs on the PC should be on the Ethernet (RJ45) connector on the back of your PC In order from left to right, the LEDs indicate: CONNECTION, TX, RX We will produce Ethernet packets from the PC by using "ping" From Windows, select "Start->Run" and type "cmd" Press "Enter" and you should have a command prompt Figure 5.22: Command window Observe the packets in Wireshark by clicking on them In the screenshot below, we see that the PC sent packets 1, and 5, while the FPGA board sent back packets 2, and with the MAC destination and source addresses swapped Notice also the short time delay of 225us between the the sent packet and the received copy Figure 5.23: The sent packet and the received packet Also observe that the RX and TX LEDs on the FPGA board will light up at the same time, indicating that each packet received is immediately transmitted back to the sender (after swapping the MAC sender/destination You now have a working Ethernet connection running at 1Gbps 99 addresses) CHAPTER 6: CONCLUSION AND FUTURE WORK I n this chapter, I summary the results which I have obtained during the thesis project Furthermore, I will point out the remains open problems which shoud be possibly researched in the coming time 6.1 Conclusion From the original idea of the beginning, I have done a lot of research, thinking about project, trying to improve my knowledge on IC design and fabrication This project was not too long to be accomplished in six months To help me to discover the diversity of this field, I attended to several interesting training courses There were a lot of difficult points, and I had to learn a lot before beginning the correct work, and I did it I am very glad to be more comfortable with it This thesis has described the design and implementation of a flexible and configurable Gigabit Ethernet for fiber optical networks transport using FPGAs This system is designed as an open research platform, with a range of configuration options and possibilities for extension in both software and hardware dimensions As mentioned in the objectives, an 8B/10B encoder-decoder, TX- FIFO, RXFIFO and Gigabit Ethernet MAC controller base optical transmitter and receiver have been successfully developed using Altera Stratix II FPGA development board The output from each module was tested using the appropriate software to ensure the correctness of the output result During the implementation stage, the operation for 8B/10B block and FIFO block were tested using ModelSim software Since ModelSim is the best to simulate the waveform and to compare the results Testing results have confirmed the correct operations of the system and the comparison result shows that module is working correctly 100 The performance of Gigabit Ethernet receive interface is evaluated in the ATVN board with Altera chip Stratix II The experimental results indicate that the FPGA-based Gigabit Ethernet is viable platform to achieve throughput competitive with real time network services Thus, based on the test result, it was concluded that the maximum range of the input optical power that could be processed is also limited by the maximum allowable frequency of the buffer, incorporated in the system to minimize the loading effects As a result, we have shown the path towards high speed 10GbE or higher speed in the future 6.2 Future work Some recommendations are suggested to develop this project First is to use higher speed, the synchronous dual-port Select-RAM mode which is available to makes it possible to incorporate fast and efficient FIFO designs running either with a common clock or with two asynchronous clocks The larger FIFOs with common clocks are recommended Second, instead of using bit binary representation, use 64 bits or more to represent each number in binary to develope by the IEEE P802.3ba Task Force LSI of 100GbE enabled the large capacity of 100 Gb/s At the same time, however, the power consumption is increasing, and new innovations and technical development are needed for implementation In this design, the receiver module which is mainly used is good at processing for the positive input value Therefore, any imaginary value should be mapped into real value such that receiver can process the input data correctly For the future works, it is suggested to develop other modules to extend this work to evaluate the higher Gigabit Ethernet, such as 10 and 100 Gigabit Ethernet Moreover, implementing the synchronizing FIFOs, using on-chip block select RAMS can be extended for SONET 101 REFERENCES [1] Actel Corporation “Implementing an 8b/10b Encoder/Decoder for Gigabit Ethernet in the Actel SX FPGA Family”, Application Note AC135, Actel Corporation, 1998 [2] Al X Widmer, Peter A Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code”, IBM Journal of Research and Development, 1983 [3] Alteon Web Systems, "Gigabit Ethernet/PCI Network Interface Card: Host/NIC Software Interface Definition", Revision 12.4.13, July 1999 [4] B Zedman, Designing with FPGA and CPLDs, CMP, September 2002 [5] C Decusatis, Fiber Optic Data Communication: Technological Trends and Advances, Academic Press, 2002 [6] H J P P Silva, M M Mosso, R A A Lima, B C L Guedes, and A Podcameni, “A New Optical Gigabit Ethernet Network Element”, Microwave and Optical Technology Letters, Vol 48, No 7, July 2006 [7] Huub van Helvoort, SDH/SONET Explained in Functional Models Modeling the Optical Transport Network, John Wiley & Sons Ltd, England, 2005 [8] IEEE 802.3 2002 Edition [9] IEEE LAN/MAN Standards Committee, “IEEE Std 802.3-2005 Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications,” IEEE, December 2005 [10] IEEE Standard for Information Technology — Telecommunications and information exchange between systems — Local and metropolitan area networks — Common specifications Part 3: Media Access Control (MAC) Bridges, ANSI/IEEE Standard 802.1D, 1998 edition Available at http://standards.ieee.org/getieee802/download/802.1D-1998.pdf [11] J Bhasker, Verilog HDL Synthesis, A Practical Prime, Lucent technology, Star Galaxy, 1998 102 CPU INTERF ACE [12] K Kitayama, F Masetti-Placci and G Prati, Optical Networks and Technologies, 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Xilinx Product Specification, DS200, November 2002 [21] Yong-Woo Kim, Beomseok Shin and Jin-Ku Kang, “High-speed 8B/10B encoder design using a simplified coding table”, IEICE Electron Express, Vol 5, No 16, pp.581-585, 2008 103 ... project and thesis ABSTRACT The thesis presents an approach to system design and implementation for optical transport networks The design of the system based on the Field Programmable Gate Array (FPGA) ... is the design and implementation of the hardware platform for the FPGA- based optical network transport with the Gigabit Ethernet interface This system is designed as an open research platform,... chapters, namely introduction, FPGA and HDL chip design, principles and applications of optical communications, design and implementation, results and analysis, conclusion and future works  Chapter