n this chapter, I summary the results which I have obtained during the thesis project. Furthermore, I will point out the remains open problems which shoud be possibly researched in the coming time.
6.1 Conclusion
From the original idea of the beginning, I have done a lot of research, thinking about project, trying to improve my knowledge on IC design and fabrication. This project was not too long to be accomplished in six months. To help me to discover the diversity of this field, I attended to several interesting training courses. There were a lot of difficult points, and I had to learn a lot before beginning the correct work, and I did it. I am very glad to be more comfortable with it.
This thesis has described the design and implementation of a flexible and configurable Gigabit Ethernet for fiber optical networks transport using FPGAs.
This system is designed as an open research platform, with a range of configuration options and possibilities for extension in both software and hardware dimensions.
As mentioned in the objectives, an 8B/10B encoder-decoder, TX- FIFO, RX- FIFO and Gigabit Ethernet MAC controller base optical transmitter and receiver have been successfully developed using Altera Stratix II FPGA development board.
The output from each module was tested using the appropriate software to ensure the correctness of the output result. During the implementation stage, the operation for 8B/10B block and FIFO block were tested using ModelSim software. Since ModelSim is the best to simulate the waveform and to compare the results. Testing results have confirmed the correct operations of the system and the comparison result shows that module is working correctly.
I
The performance of Gigabit Ethernet receive interface is evaluated in the ATVN board with Altera chip Stratix II. The experimental results indicate that the FPGA-based Gigabit Ethernet is viable platform to achieve throughput competitive with real time network services.
Thus, based on the test result, it was concluded that the maximum range of the input optical power that could be processed is also limited by the maximum allowable frequency of the buffer, incorporated in the system to minimize the loading effects. As a result, we have shown the path towards high speed 10GbE or higher speed in the future.
6.2 Future work
Some recommendations are suggested to develop this project. First is to use higher speed, the synchronous dual-port Select-RAM mode which is available to makes it possible to incorporate fast and efficient FIFO designs running either with a common clock or with two asynchronous clocks. The larger FIFOs with common clocks are recommended.
Second, instead of using 8 bit binary representation, use 64 bits or more to represent each number in binary to develope by the IEEE P802.3ba Task Force LSI of 100GbE enabled the large capacity of 100 Gb/s. At the same time, however, the power consumption is increasing, and new innovations and technical development are needed for implementation.
In this design, the receiver module which is mainly used is good at processing for the positive input value. Therefore, any imaginary value should be mapped into real value such that receiver can process the input data correctly.
For the future works, it is suggested to develop other modules to extend this work to evaluate the higher Gigabit Ethernet, such as 10 and 100 Gigabit Ethernet.
Moreover, implementing the synchronizing FIFOs, using on-chip block select
REFERENCES
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