CHAPTER 5 SIMULATION RESULTS AND EXPERIMENTAL TESTS ON
5.2.2 FIFO Implemetation and simulation results
The asynchronous FIFO is a First-In-First-Out memory queue with control logic that performs management of the read and write pointers, generation of status flags, and optional handshake signals for interfacing with the user logic. The individual read and write ports are fully synchronous (all operations qualified by a rising clock edge), but this FIFO does not require the read and write clocks to be synchronized to each other.
FIFO status cannot be corrupted by invalid requests. Requesting a read operation while the EMPTY flag is active will not cause any change in the current sate of the FIFO. Similarly, requesting a write operation while the FULL flag is active will not cause any change in the current state of the FIFO. In addition to the EMPTY and FULL flags, a count vector can be enabled to provide a more granular measure of the FIFO state. For the write domain the vector is WR_USED, and for the read domain it is RD_USED. The widths of these vectors are user programmable to provide easy generation of additional flags. In keeping with the fully synchronous interface, the count vector can be synchronized to either the read or the write clock domain, or two independent counts can be enabled, one for each clock domain.
By using Verilog, the asynchronous FIFO can be implemented. The schemetic symbol of an asynchronous FIFO is described in Figure 5.7.
aclr rd_clk rd_req wr_dat[DAT_WIDTH-1..0]
wr_clk wr_req
rd_dat[DAT_WIDTH-1..0]
rd_empty rd_used[ADDR_WIDTH..0]
wr_full wr_used[ADDR_WIDTH..0]
fifo
inst
aclr INPUTVCC
rd_clk INPUTVCC
re_req INPUTVCC
wr_dat[DAT_WIDTH-1..0] INPUTVCC
wr_clk INPUTVCC
wr_req INPUTVCC
re_dat[DAT_WIDTH-1..0]
OUTPUT
rd_empty OUTPUT
rd_used[ADDR_WIDTH...0]
OUTPUT
wr_used[ADDR_WIDTH...0]
OUTPUT wr_full OUTPUT
Figure 5.7: Schemetic Symbol of an Asynchronous FIFO
Core signal names are presented in Table 5.3.
Table 5.3: Core Signal Pinout
Name Direction Description
aclr Input Assert this signal to clear all the outputstatus ports.
wrclk Input Positive-edge-triggered clock. Use to synchronise the following ports:
■ wrdata
■ wrreq
■ wrfull
■ wrused
wrdat Input Holds the data to be written in the FIFO when the wrreq isgnal is asserted.
wrreq Input Assert this signal to request for a write operation. Ensure that the following conditions are met:
■ Do not assert the wrreq signal when the
wrfull port is high.
■ Do not assert the wrreq signal during
signal.
rdclk Input Postive-edge triggered clock. Use to synchronize the following ports:
■ rddat
■ rdreq
■ rdempty
■ rdused
rdreq Input Assert this signal to request for a read operation.
Ensure that the following conditions are met:
■ Do not assert the rdreq signal when the rdempty port is high.
rddat Output Shows the data read from the read request operation.
The width of the rddat port must be equal to the width of the data port.
wrfull Output When asserted, the FIFO is considered full. Do not perform write request operation when the FIFO is full.
rdempty Output When asserted, the FIFO megafunction is considered empty. Do not perform read request operation when the FIFO megafunction is empty.
rdused Output Count vector (unsigned binary)
representing the number of data word currently in FIFO, synchronized to rdclk.
wrused Output Count vector (unsigned binary)
representing the number of data words currently in FIFO, synchronized to wrclk.
5.2.2.2 Behavior of Status Signals
The activation of the ACLR, asynchronous initialization (reset), will force all four FIFO flags to the active (high) state. On the first WR_CLK after the release of ACLR the FULL flag will become inactive, indicating that the FIFO is now ready to accept write operations. EMPTY is deactivated on a rising edge of the RD_CLK following the first and second writes respectively. Optional handshake signals are provided to simplify user control logic interacting with the FIFO. Note that all of these handshake signals are synchronous to their respective clock domains and indicate the acknowledgment or rejection of requests during the prior rising clock edge. The data count outputs (WR_USED and RD_USED) support the generation of user programmable flags. Like all other FIFO outputs, the counts are synchronized to their respective clock domains and should be sampled only by logic operating on the same (or a synchronous) clock. The data count vectors have clock latency and should not be used as substitutes for the FULL or EMPTY. The clock latency of the counts in their respective clock domains is one cycle.
For example, the WR_USED does not reflect the impact of a write operation performed as a result of a request (WR_REQ active) during the prior clock cycle.
WR_USED and RD_USED values are not guaranteed to produce a precise representation of the FIFO contents at a particular point in time. These values should be used as a gauge to determine the FIFO status. The latency for operations in the opposing clock domain can be up to three clock cycles.
For example, in the case of the WR_USED, read operations that may have been performed during the immediate three prior RD_CLK periods will not be reflected in the data count vector. This latency results from a design trade-off between clock frequency and count accuracy and is not as limiting as it may at first appear.
We will analyze the simulation results to illustrate the FIFO functional operations.
Intial write operation to an FIFO: simulation results from 0 ns to 2 ns.
Figure 5.8 shows the functional simulation resuls for an initial write operation to an emplty FIFO from 0 ns to 160 ns.
(1) At first, the aclr signal is asserted (actived), the all outputs are clear.
(2) At 200 ps, the wreq signal is asserted. While the intial state of wrfull is high, the data are not written.
(3) At 450 ps, the wrfull is low, the date value 00000000 is written into the FIFO.
(4) At 550 ps, the wrused signal increments from 00000 (0 in Decimal) to 00001 (1 in Decimal). Latency is wrreq to wrused: 1 wrclk cycle. At the same time, the wrreq signal is high and therefore, the data value 00101011 is written.
(5) At 650 ps, the wrused signal increments from 00001 (1 in Decimal) to 00010 (2 in Decimal).
(6) At 850 ps, the rdused counter increments from 00000 to 00001. Latency is 1 wrclk + next 3 rdclk cycles. At this time, the rdreq is at active level, read operations should occurs, and the siganal value 00000000 outputs on the rddat pins.
(7) At 950 ps, the rdused is still 00001 because the data is written to FIFO at 550 ps. The rdreq is high level and, hence, the data value 00101011 is read out.
(8) At 1050 ps, the rdused reduces from 00001 to 0000. Latency is rdreq to rdused: 1 rdclk cycle.
Figure 5.8: Initial write operations to an FIFO.
Read and Write Operations to an Almost Full FIFO: Simuation Results (36 ns to 40 ns).
Figure 5.9 shows the functional simulation results for read and write operations into an alsom full FIFO from 36 ns to 40 ns. It shows detailed behaviour of the wrfull, wrused, rdempty and rdused.
(1) At 37650 ps, the wrused signal is 01111 (15 in Decimal).
(2) At 37750 ps, the wrreq is asserted, the data value 00010011 is writen in the memory, but the wrused signal is not still 01111 because the other data is read out at time 37345 ps.
(3) At 37850 ps, the wrreq is high, the wrful signal is asserted. Latency is wreq to wrful: 0 wrclk cycles. And the wrused signal is 10000 at 37950 ps (The most significant bit of value 1 indicates that the memory is full).
(4) At 38050 ps, the wrused signal becomes to 01111 because the memory is read out at time 37650 ps.
Figure 5.9: Read and Write Operations to an Almost Full FIFO
Read and Write Operation to an Empty FIFO: Simuation Results (52 ns to 53 ns)
Figure 5.10 illustrates the functional simulation results for read and write operations into an alsom empty FIFO from 52 ns to 53 ns. It shows detailed behaviour of the wrfull, wrused, rdempty and rdused.
(1) At time 52150 ps the rdused is 00001. As the rdreq is high, the data value 01010100 outputs on the rddata pins, the FIFO becomes empty and the redmpty is asserted. The rdused becomes 00000 at 52250 ps because the latency is 1 rdclk clycle.
(2) At 52250 ps the rdreq is high, but the data values on the rddata are unchanged because rdempty signal is high.
Figure 5.10: Read and Write Operations to an almost empty FIFO