DESIGN AND MANAGMENT OF SCALABLE FPGA ARCHITECTURES

DESIGN AND MANAGEMENT OF SCALABLE FPGA ARCHITECTURES RIZWAN SYED (M.Sc. Elect. & Comp. Engg, NUS) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2013 Declaration I hereby declare that this thesis is my original work and it has been written by me in its entirety. I have duly acknowledged all the sources of information which have been used in the thesis. This thesis has also not been submitted for any degree in any university previously. RIZWAN SYED DECEMBER 02, 2013 iii Acknowledgments I have always regarded the journey as being more important than the destination itself. While for PhD the destination is surely desired, the importance of the journey cannot be underestimated. At the end of this long road, I am thankful to Allah (SWT) for helping me throughout my PhD. Then, I would like to express my sincere gratitude to all those who supported me all the years and made this journey enjoyable. Without their help and support, this thesis would not have reached its current form. First of all I would like to thank Dr. Yajun Ha, my supervisor, for mentoring me all through the journey of PhD. He has always motivated me all through my research and has constantly made me think of how I can improve my ideas and apply them in a more practical way. His eye for details helped me maintain a high quality of my research. Despite being a very busy person, he always ensured that we had enough time for regular discussions. Whenever I needed something done urgently, whether it was feedback on a draft or filling some form, he always gave it utmost priority. He often worked in holidays and weekends to give me feedback on my work in time. Further, I would like to thank A/P Bharadwaj Veeravalli for all the support and supervision during all the years of my PhD. He was always an inspiration for me and always gave me useful insight into research methodology, and critical comments on my publications throughout my PhD project. I was very fortunate to have two supervisors who were all very hard working and motivating. v My thanks also extend to all my friends most notably Xiaolei Chen, Zhao Wenfeng, Yu Heng, and Rajesh Panicker for all the support and all the nice discussions and constructive feedback that I got from them. I would like to thank my family and friends for their interest in my project and the much needed support. I would especially like to thank my parents without whom I would not have been able to achieve this result. Last but not least, I would like to thank my wife for her ongoing support and enduring all the troubles during my PhD. Rizwan Syed vi Summary Field Programmable Gate Arrays (FPGAs) have been demonstrated in various applications to deliver significant performance speed-ups as compared to other software-centric platforms and in some case with significant improvement in efficiency as well. Although, FPGAs are slower and inefficient than Application-Specific Integrated Circuits (ASICs), yet their disadvantage is offset by their on-the-field programmability, low non-recurring engineering costs and fast-turnaround times. However, designing larger FPGAs is getting more difficult even with the ongoing advancement in semiconductor manufacturing technology. Global wire delay has emerged as a problem for both ASICs and FPGAs. FPGAs conventionally implement global interconnects using long wires and switch blocks, which make them slow and inefficient. Another issue is clock skew in the distribution of the global clock for larger FPGAs. Furthermore, the increasing area overheads due to larger programmable routing-interconnect required to support increasing computation resources make the scalability an issue for existing FPGA architecture. Another issue is decreasing yields with increasing FPGA die sizes. This adversely affect the manufacturing cost of the device. On the other hand, as the resources in FPGAs increase, the runtime of the implementation tools also increase. This can be mitigated by adopting hierarchical design methodology and reusing of implemented sub-components. The later will require only the new components to be implemented and thus will require lesser time to implement. However, this would require runtime resource vii management of FPGA. Existing tools that support resource management of FPGA impose various constraints and overheads that make their proposals practically less useful. Furthermore, to improve the reliability of the system, such a resource manager should be self-aware by measuring physical quantity such as the temperature profile of a FPGA die. This would allow the manager to perform thermal management by adjusting performance of running tasks. Envisioning that reconfigurable computing will be a part of mainstream computing, this thesis presents a scalable FPGA architecture to mitigate the issues with scalability of single FPGAs and multi-FPGA systems. Furthermore, it proposes an abstract architecture for resources management of scalable FPGA architecture supporting the abstraction of both computing and communication resources. This thesis makes the following contributions. First, to solve the issues with scalability of FPGAs, we propose a novel scalable FPGA architecture and its design methodology. This architecture allows us to model both single FPGAs and multi-FPGA systems under a single architecture. In this architecture, we partition a FPGA into multiple tiles. We assume a tile to be a current generation FPGA. These tiles use a hierarchical network for routing between them and thus separate local routing from global. Due to the use of a hierarchical network, the architecture can be easily scaled just by the addition of more tiles and higher-levels. Second, to enable efficient resource management on the scalable FPGA architecture, we initially develop a low overhead framework that supports important features such as dynamically sized reconfigurable regions, abstraction in communication among hardware applications, clock network management and in-circuit debugging for hardware applications. This allows us to abstract the computational and communication resources of our scalable FPGA architecture. Third, to extend our framework to multi-FPGA systems, we develop a scalable AXI interconnect for existing FPGAs. The scalable AXI interconnect uses high-speed serial links for inter-FPGA communications. Packet switching is used to deliver packets from source FPGA to destination FPGA using one or more hops. The interconnect has a low area and transport overheads while offering high-bandwidth and low latency as compared to other interconnects. Finally, we implement a LUT-based temperature sensor that has a resolution of 0.5◦ C and an accuracy of ±0.5◦ C using two-point calibration. It utilizes viii 52% less resources than the state-of-the-art. We use an array of such sensors to monitor the thermal profile of the FPGA die and then use it to and adjust performance of running applications as required through dynamic frequency scaling. ix x 6. THERMAL MANAGEMENT FOR RECONFIGURABLE PLATFORMS can be augmented with runtime resource management to improve the reliability of a multi-FPGA platform. 102 CHAPTER Conclusions and Future Work In this chapter, we present the major conclusions from this thesis from the perspective of scalability, productivity and reliability of reconfigurable systems. Then we highlight several issues that remain to be solved. As mentioned earlier, FPGAs have been demonstrated in various applications to deliver significant performance speed-ups as compared to other software centric platforms and in some case with significant improvement in efficiency as well. Although, FPGAs are slower and inefficient as compared to ASICs, yet their disadvantage is offset by their on-the-field programmability, low non-recurring engineering costs and fast-turnaround times. However, designing larger FPGAs is getting more difficult even with the ongoing advancement in semiconductor manufacturing technology. Global wire delay has emerged as a problem for both ASICs and FPGAs. FPGAs conventionally implement global interconnects using long wires and switch blocks, which make them slow and inefficient. Another problem is due to clock skew in the distribution of the global clock for larger FPGAs. Furthermore, increasing area overheads due to programmable routing interconnect (to support increasing computation resources) make the scalability an issue for existing FPGA architecture. Another issue is decreasing yields with increasing FPGA die sizes. This adversely affect the manufacturing cost of the device. We addressed all these 103 7. CONCLUSIONS AND FUTURE WORK issues by designing a scalable FPGA architecture as mentioned in Chapter 3. It uses globally synchronous locally asynchronous paradigm to overcome the issues with long wire delays as well as clock skew. This allows the communications within a localized areas, called tiles, to be synchronized locally to a clock while adopting asynchronous communication methodology using a hierarchical network for globally communications. By reusing interconnecting wires in the hierarchical interconnect, the area requirement for the interconnect is reduced. This has the added benefit of traffic localization. The architecture can be easily scaled by the adding of higher level and tiles. Then a design methodology is proposed to allow existing designs to be mapped to this architecture. The architecture was then successfully demonstrated using an emulation prototype. The experimental results and predicted values reported show the effectiveness of the new architecture. The proposed architecture not only solves the issue related to global wire delay but also solves the issue of reduction in yields with increasing die sizes. In the architecture, each tiles can be essentially fabricated as a separate silicon and integrated together on a larger substrate using 3D-IC fabrication. As proof of this concept, Virtex [5] uses the same methodology to integrate multiple dies onto a single substrate [17]. Thus, Virtex can be considered as an instance of this architecture. However, as reconfigurable systems scale, the runtime of the implementation tools also increase which adversely affects productivity. This can be mitigated by adopting hierarchical design methodology and also by reusing of implemented sub-components. The later will require only the new components to be implemented and thus will require lesser time to implement. However, this would require runtime resource management of FPGA. Existing tools that support resource management of FPGA impose various constraints and overheads that make their proposals practically less useful. To address this issue, we designed a practical and efficient resource management framework in Chapter 4. It supported the abstraction of both computation and communication resources of the FPGA. The communication among the sub-components was enabled through the use of a deterministic network-on-chip. Furthermore, it supported practically important features like dynamic sized regions, clock management, and per-application on-chip debug capability. To support this framework, a design methodology was also proposed that used existing implementation tools without any modifications. Then, the effectiveness of the framework 104 7. CONCLUSIONS AND FUTURE WORK was demonstrated using a prototype. It was shown that the area overheads of using such a framework was low while the performance overhead depended up on the application model. If a data flow model is used, then the overheads are negligible. Else the overheads will be significant. It was argued that this is a non-issue as most well-designed applications are modular and can use data-flow model easily. Although the proposed framework did enable efficient runtime resource management but it was limited to only one FPGA. The problem of increasing implementation times is more pronounced for multi-FPGA systems. Therefore, in Chapter 5, we extended the framework to allow the benefits of runtime resource management to be utilized on multi-FPGA platforms. A scalable interconnect was designed supporting the popular industry standards, AXI4 and AXI4-Stream. It used a hybrid-network comprising of both circuit-switching and packet-switching networks. On-chip routing was enabled by hierarchical circuit-switching network supporting deterministic timing in communications. On the hand, off-chip communication was achieved through packet-switching network utilizing high-speed transceivers. Most scalable network topologies were supported by the interconnect. This made the interconnect scalable as it was shown to be cost effective and easier to scale as compared parallel interfaces and other interconnects. Furthermore, the interconnect not only abstracted communication among hardware task, but also the abstracted the address space so that different task can use the same space while avoiding any conflicts. This allowed the system to contain very large amounts of memory without requiring large addresses by reusing the same address space. The interconnect was demonstrated in conjunction with AARP. The performance of the interconnect was comparable to the high-performance interconnect Infiniband while the overheads was comparable with existing commercial multi-FPGA solutions. Although the solutions presented earlier addressed some of the major issues with scalability and productivity of reconfigurable system, yet reliability remained unaddressed. As systems scale in terms of both process technology and size, reliability become a growing concern. Temperature is one of the factors that affect the reliability of a device and this can be mitigated through thermal management. In case of FPGAs, this is not possible due to lack of multiple sensors to monitor the temperature profile of the die. Furthermore, runtime resource management makes the estimation of power dissipation impractical. Therefore, in Chapter 6, we developed a low overhead temperature sensor that 105 7. CONCLUSIONS AND FUTURE WORK had low resource utilization and good accuracy. A comparative study showed that it provided comparable performance while using 52% less resources than the state-of-the-art. The effects of resource utilization and placement on the sensor was also studied. Then, an array of such sensors was used to monitor the thermal profile of the FPGA. This information was used to control the operating frequencies of test applications through dynamic frequency scaling. It was demonstrated that FPGA device could operate reliably with the proposed thermal management solution. 7.1 Future Work While this thesis presents solutions to various problems in the analysis and design of scalable FPGA architectures and its resource management, a number of issues remain to be solved. Some of these are listed below. 1. Automated Tools: Works presented this thesis are aimed towards improving productivity with scalable reconfigurable computing. The proposed framework can be improved even further by developing automated tools that allow designers to use develop instances of the framework effortlessly. Furthermore, such tools could also guide a developer through the design methodologies presented in this thesis and assist in the development of hardware applications. 2. Thermal-Aware Resource Allocation: Although thermal management support was developed as part of this thesis, yet there is no existing allocator than can fully utilize it’s potential. By extending resource allocators to support thermal management, we are essentially allowing the runtime manager to estimate the performance of the applications under thermal constraints and thus allow it to provide potentially better and feasible solutions to runtime allocation problem. 3. Distributed/Scalable Resource Allocator: The works presented in this thesis focused on the implementation of a framework to support scalable runtime resource management. However, this also requires a distributed and scalable resource allocator that can schedule applications on the multi-FPGA platforms efficiently at runtime while maximizing their 106 7. CONCLUSIONS AND FUTURE WORK performance. Such an allocator would improve the scalability of the overall system. 4. Support for Data Flow Graphs: Existing allocators for FPGAs typically take single tasks and schedule it on the platform. Therefore, they not essentially support mapping applications with sub-tasks connected as data flow graphs. The motivation to develop efficient resource management in this thesis was reuse of implemented sub-components. Therefore, this problem will not be fully solved without developing such an allocator that can allocate such application on FPGAs. 5. Integration with Existing Operating Systems: Integration with existing operating system will enable developers to write applications that are composed of software as well as hardware. This is analogous to OpenCL, DX Compute APIs for the graphic processing units (GPUs) in existing operating systems. This will increase the abstraction provided by the framework and thus improve productivity. 6. Support for Quality of Service: The interconnect presented in Chapter routes off-chip traffic using best-effort. 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IEEE/ACM International Conference on, Nov 2008, pp. 722–727. 117 [...]... the die of existing FPGAs and use this information to control the regional power dissipation of the FPGA die However, the study of other effects on the reliability of FPGAs will be beyond the scope of this thesis 1.6 Key Contributions and Thesis Overview The main aim of this thesis is to study the problems associated with scalability in FPGAs and its resource management and propose practical and novel... scalability of FPGAs and also improve the productivity of designers by providing better tools and framework Following are some of the major contributions that have been achieved during the course of this research and have led to this thesis • A novel Scalable FPGA Architecture to significantly reduce the overheads associated with designing larger FPGAs This work was published in [32] • A design methodology... [34] The organization of thesis as follows Chapter 2 gives an overview of the existing FPGA architectures and explains the design flow associated with implementing hardware applications on FPGA Then it discusses runtime resource management for reconfigurable platforms and also present related works and its shortcoming In Chapter 3, we introduce our scalable FPGA architecture and its design methodology We... algorithms and design methodologies will be beyond the scope of this thesis Third, to improve the reliability of reconfigurable systems, we will study existing works and understand the difficulties in real time thermal monitoring of existing FPGAs Then, we will design and develop a low overhead temperature sensor using the resources within existing FPGAs This will enable us to monitor the temperature profile of. .. in scalable reconfigurable computing, and are addressed in this thesis • Scalability in FPGA Architecture: Design a FPGA architecture along with its interconnect to allow scalability without significant performance and area overheads (Scalability in FPGAs, Scalable Interconnect) • Efficiency in Resource Management: Design and develop a framework to allow reuse of implemented sub-components across designs... the merits and demerits of such an architecture by the use of a case study In Chapter 4, we present our framework for resource management of FPGA and demonstrate its effectiveness experimentally using a prototype Chapter 5 introduces our scalable off-chip interconnect and we evaluate its performance and overheads on a multi -FPGA system In Chapter 6, we present our LUT-based temperature sensor and compare... the performance and efficiency of FPGAs as compared to ASICs [3] However, scaling of FPGAs is not possible without increasing the routing resources of the FPGA The increase in switching requirement is asymptotically bounded below by Eq.1.1 [23] and is superlinear with number of logic resources Nsw (N) = BSW ·N = Ω N (p+0.5) , (1.1) where Nsw (N) is the number of switches, N is the number of logic resources,... Productivity) Fig 1.4: The Design Productivity Gap [2] and is shown in Fig.1.4 The productivity gap is a comparison between the manufacturing complexity (i.e number of transistors that we can manufacture) and the designer productivity (i.e number of transistors that we can design) Although this trend is for ASICs, we still find a similar trend in the design of circuits on FPGAs The complexity in designing digital... 2.1 Architectures of different programmable devices 16 2.2 Simplified architecture of a modern-day FPGA 18 2.3 Generic Design Flow 2.4 Configuration Architectures of FPGAs 22 3.1 Routing Methodology 3.2 Proposed sFPGA2 Implementation 32 3.3 sFPGA2 Architecture Block Diagram 33 3.4 IO Transceiver Design. .. 1.4.3 Scalable Interconnect Our scalable FPGA architecture presented earlier solves the issue of scalability for single -FPGA systems However, for multi -FPGA systems, the solution presented earlier is too expensive in terms of required off-chip infrastructure This is due to the fact that the hierarchical interconnect requires a large number of switching-units To solve this issue, we develop a scalable off-chip . DESIGN AND MANAGEMENT OF SCALABLE FPGA ARCHITECTURES RIZWAN SYED (M.Sc. Elect. & Comp. Engg, NUS) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND. presents a scalable FPGA architecture to mitigate the issues with scalability of single FPGAs and multi -FPGA systems. Furthermore, it proposes an abstract architecture for resources management of scalable. scalability of FPGAs, we propose a novel scalable FPGA architecture and its design methodology. This architecture al- lows us to model both single FPGAs and multi -FPGA systems under a single architecture.