Design and Implementation of VLSI Systems_Lecture 05: Circuit Characterzation performace estimation doc

Design and Implementation of VLSI Systems Lecture 05 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 05: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION 2 Delay Estimation 1 Logical Effort for Delay Estimation 2 Power Estimation 3 Interconnect and Wire Engineering 4 Scaling Theory 5 3 Delay Estimation 1 Logical Effort for Delay Estimation 2 Power Estimation 3 Interconnect and Wire Engineering 4 Scaling Theory 5 LECTURE 05: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION INTRODUCTION  Critical paths are those which require attention to timing details  Timing analyzer is a design tool that automatically finds the slowest path in a logic design  Altera: Classic Timing Analyzer, TimeQuest Timing Analyzer  Synopsys: PrimeTime  The critical paths can be affected at four main levels  The architecture/ microarchitecture level  The logic level  The circuit level  The layout level 4 DELAY DEFINITIONS  tpdr: rising propagation delay  Max time: From input to rising output crossing VDD/2  tpdf: falling propagation delay  Max time: From input to falling output crossing VDD/2  tpd: average propagation delay. tpd = (tpdr + tpdf)/2  tcdr: rising contamination (best-case) delay  Min time: From input to rising output crossing VDD/2  tcdf: falling contamination (best-case) delay  Min time: From input to falling output crossing VDD/2  tcd: average contamination delay. tcd = (tcdr + tcdf)/2  tr: rise time  From output crossing 0.2 VDD to 0.8 VDD  tf: fall time  From output crossing 0.8 VDD to 0.2 VDD 5 HOW TO CALCULATE DELAY? JUST RUN SPICE! (V) 0.0 0.5 1.0 1.5 2.0 t(s) 0.0 200p 400p 600p 800p 1n t pdf = 66ps t pdr = 83ps V in V out •Time consuming •Not very useful for designers in evaluating different options and optimizing different parameters • We need a simple way to estimate delay for “what if” scenarios. • Fidelity vs. accuracy 6 TRANSISTOR RESISTANCE In the linear region •Not accurate, but at least shows that the resistance is proportional to L/W and decreases with V gs 7 SWITCH-LEVEL RC MODELS  An nMOS transistor with width of one unit is defined to have effective resistance R.  The resistance of a pMOS transistor = 2× resistance of nMOS transistor of the same size due to the pMOS mobility.  Wider transistors have lower resistance  a pMOS transistor of double-unit width has effective resistance R.  A transistor of k unit width has kC capacitance and R/k resistance 8 kg s d g s d kC kC kC R/k kg s d g s d kC kC kC 2R/k CALCULATE K 9 EXAMPLE: 3-INPUT NAND GATE  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 3 3 2 22 3 10 C = C gate + C source diffusion + C drain diffusion  To keep estimation simple C gate = C diffusion o The capacitance consists of gate capacitance and source/drain diffusion capacitance [...]... VDD A VDD B Y GND A B Y GND 16 LECTURE 05: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION 1 Delay Estimation 2 Logical Effort for Delay Estimation 3 Power Estimation 4 Interconnect and Wire Engineering 5 Scaling Theory 17 INTRODUCTION   Chip designers face a bewildering array of choices  What is the best circuit topology for a function?  How many stages of logic give least delay?  How wide should... effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current  Measure from delay vs fanout plots  Or estimate by counting transistor widths  2 A Y 2 A 2 Y 1 Cin = 3 g = 3/3 A 2 B 2 Cin = 4 g = 4/3 4 B 4 Y 1 1 Cin = 5 g = 5/3 23 CATALOG OF GATES  Logical effort of common gates Gate type Number of inputs 1 2 3 4 n NAND 4/3 5/3 6/3 (n+2)/3... 2 2 2 4, 4 6, 12, 6 8, 16, 16, 8 Inverter Tristate / mux XOR, XNOR 1 2 24 CATALOG OF GATES  Parasitic delay of common gates In multiples of pinv (1) Gate type  1 Number of inputs 2 3 4 n NAND 2 3 4 n NOR 2 3 4 n 4 6 8 2n 4 6 8 Inverter Tristate / mux XOR, XNOR 1 2 25 EXAMPLE: RING OSCILLATOR  Estimate the frequency of an N-stage ring oscillator Logical Effort: Electrical Effort: Parasitic Delay:... process has frequency of ~ 200 MHz g=1 h=1 p=1 d=2 fosc = 1/(2*N*d) = 1/4N 26 EXAMPLE: FO4 INVERTER  Estimate the delay of a fanout -of- 4 (FO4) inverter d Logical Effort: Electrical Effort: Parasitic Delay: Stage Delay: g=1 h=4 p=1 d=5 The FO4 delay is about 300 ps in 0.6 mm process 15 ps in a 65 nm process 27 LIMITATIONS OF LINEAR DELAY MODEL  Input and Output Slope 28 LIMITATIONS OF LINEAR DELAY MODEL... t pd  R i to  source Ci nodes i  R1C1   R1  R2  C2    R1  R2   RN  CN R1 R2 R3 C1 C2 RN C3 CN 12 COMPUTING  Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates 2 2 A 2 B 2x R Y (6+4h)C x R/2 THE RISE AND FALL DELAYS R/2 2C Y (6+4h)C Y 4hC 6C h copies 2C t pdr   6  4h  RC  Best-case t pdf   2C   R    6  4h  C   R  R  2  ...EXAMPLE: 3-INPUT NAND GATE  Annotate the 3-input NAND gate with gate and diffusion capacitance 2C 2 2C 2C 2C 2 2C 2C 2 2C 3C 3C 3C 2C 2 2C 3 3 3 3C 3C 2 2 3 5C 5C 5C 3 3 9C 3C 3C 3C 3C 11 ELMORE DELAY MODEL ON transistors look like resistors  Pullup or pulldown network modeled as RC ladder  Elmore delay of RC ladder  t pd  R i to  source Ci nodes i  R1C1... a method to make these decisions  Uses a simple model of delay ???  Allows back -of- the-envelope calculations  Helps make rapid comparisons between alternatives  Emphasizes remarkable symmetries 18 EXAMPLE    32 bits 16 words 4:16 Decoder Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor Help Ben design the decoder for a register file Decoder specifications:... 60 ps current  g  1 for inverter  h: electrical effort = Cout / Cin  Ratio of output to input capacitance  Sometimes called fanout  p: parasitic delay  Represents delay of gate driving no load  Set by internal parasitic capacitance 21  DELAY PLOTS d =f+p = gh + p What about NOR2? 6 Normalized Delay: d  2-input NAND Inverter 5 g=1 p=1 d=h+1 4 3 g = 4/3 p=2 d = (4/3)h + 2 Effort Delay: f 2 1... 68W86, an embedded automotive processor Help Ben design the decoder for a register file Decoder specifications:  16 word register file  Each word is 32 bits wide  Each bit presents load of 3 unit-sized transistors  True and complementary address inputs A[3:0]  Each input may drive 10 unit-sized transistors Ben needs to decide:  How many stages to use? A[3:0] A[3:0]  How large should each gate be?... gate own diffusion capacitance) 6 or 7 RC  Independent of load   Effort delay 4h RC  Proportional to load capacitance  20 DELAY IN A LOGIC GATE Delay has two components: d = f + p  f: effort delay = gh (a.k.a stage effort) d d  abs  Again has two components    3RC  g: logical effort  3 ps in 65 nm process  Measures relative ability of gate to deliver in 0.6 mm process 60 ps current  g . Design and Implementation of VLSI Systems Lecture 05 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 05: CIRCUIT. A V DD GND B Y A V DD GND B Y 16 LECTURE 05: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION 17 Delay Estimation 1 Logical Effort for Delay Estimation 2 Power Estimation 3 Interconnect and Wire Engineering. Logical Effort for Delay Estimation 2 Power Estimation 3 Interconnect and Wire Engineering 4 Scaling Theory 5 LECTURE 05: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION INTRODUCTION