Design and Implementation of VLSI Systems_Lecture 06: Circuit characterization and performance estimation ppt

Design and Implementation of VLSI Systems Lecture 06 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 INTRODUCTION  The delay of a logic gate: C: load capacitance t ∝ 𝐶 𝐼 ∆𝑉 I: output current ∆𝑉: output voltage swing 2  nMOS provides more current than pMOS for the same size and capacitance  Static CMOS requires both nMOS and pMOS on each input.  All the node voltages in static CMOS must transition between 0 and V DD  propagation delay + power consumption.  Circuit families LECTURE 06: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION Static CMOS 1 Ratioed Circuits 2 Dynamic Circuits 3 Pass-transistor Circuits 4 3 LECTURE 06: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION Static CMOS 1 Ratioed Circuits 2 Dynamic Circuits 3 Pass-transistor Circuits 4 4 OUTLINE  Bubble Pushing  Compound Gates  Logical Effort Example  Input Ordering  Asymmetric Gates  Skewed Gates  Best P/N ratio 5 EXAMPLE 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. D0 S D1 S Y 6 EXAMPLE 2 Y D0 S D1 S 7 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. BUBBLE PUSHING  Start with network of AND / OR gates  Convert to NAND / NOR + inverters  Push bubbles around to simplify logic  Remember DeMorgan’s Law Y Y Y D Y (a) (b) (c) (d) 8 EXAMPLE 3 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; Endmodule 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. Y D0 S D1 S 9 COMPOUND GATES  Logical Effort of compound gates A B C D Y A B C Y A B C C A B A B C D A C B D 2 2 1 4 44 2 2 2 2 4 4 4 4 g A = 6/3 g B = 6/3 g C = 5/3 p = 7/3 g A = 6/3 g B = 6/3 g C = 6/3 p = 12/3 g D = 6/3 YA A Y g A = 3/3 p = 3/3 2 1 YY unit inverter AOI21 AOI22 A C D E Y B Y B C A D E A B C D E g A = 5/3 g B = 8/3 g C = 8/3 g D = 8/3 2 2 2 22 6 6 6 6 3 p = 16/3 g E = 8/3 Complex AOI Y A B C Y A B C D   Y A B C D E   YA 10 [...]... conditions)  27 INFLUENCE OF FAN-IN AND FAN-OUT ON DELAY 28 FAST COMPLEX GATE -DESIGN TECHNIQUES 29 FAST COMPLEX GATE - DESIGN TECHNIQUES 30 FAST COMPLEX GATE - DESIGN TECHNIQUES 31 LECTURE 06: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION 1 Static CMOS 2 Ratioed Circuits 3 Dynamic Circuits 4 Pass-transistor Circuits 32 INTRODUCTION a) Small Vout (VOL) 33 b) c) RATIOED CIRCUITS Def: The transfer... dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes  25 STATIC CMOS (REVIEW) 26 PROPERTIES OF COMPLEMENTARY CMOS GATES (REVIEW) High noise margins: VOH and VOL are at VDD and GND, respectively  No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode  Comparable rise and fall... that edge gu = 2.5 / 3 = 5/6  gd = 2.5 / 1.5 = 5/3  18 HI- AND LO-SKEW   Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an un-skewed inverter delivering the same output current for the same transition Skewed gates transistors reduce size of noncritical HI-skew gates favor rising output (small nMOS)... INTRODUCTION a) Small Vout (VOL) 33 b) c) RATIOED CIRCUITS Def: The transfer function depends on the ratio of the strength of the pull-down transistor to the pullup device  Ratioed circuits dissipate power continually in certain states and have poorer noise margins than complementary circuits  Ratioed circuits tend to be used only in very limited circumstances  34 PSEUDO-NMOS  In the old days, nMOS processes... stages Latest-arriving input For area and power:  Many simple stages vs fewer high fan-in stages 24 STATIC CMOS CIRCUIT (REVIEW) At every point in time (except during the switching transients) each gate output is connected to either VDD or VSS via a low-resistive path  The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the... maximum input capacitance of 16 units on each input It must drive a load of 160 units Estimate the delay of the two designs H = 160 / 16 = 10 B = 1 N = 2 D0 S Y D1 S P  22 4 G  (4 / 3) (4 / 3)  16 / 9 D0 S D1 S Y P  4 1  5 F  GBH  160 / 9 ˆ f  N F  4.2 G  (6 / 3) (1)  2 F  GBH  20 ˆ f  N F  4.5 ˆ D  Nf  P  12.4 ˆ D  Nf  P  14 11 EXAMPLE 5  Annotate your designs with transistor... RATIOS  In general, best P/N ratio is sqrt of equal delay ratio Only improves average delay slightly for inverters  But significantly decreases area and power  Inverter NAND2 2 fastest P/N ratio A 1.414 Y 1 gu = 1.15 gd = 0.81 gavg = 0.98 NOR2 B Y A 2 B 2 2 A 2 2 Y gu = 4/3 gd = 4/3 gavg = 4/3 1 1 gu = 2 gd = 1 gavg = 3/2 23 OBSERVATIONS  For speed:     NAND vs NOR Many simple stages vs fewer high... time is known  2 B Y 2 Connect latest input to inner terminal 14 ASYMMETRIC GATES Asymmetric gates favor one input over another  Ex: suppose input A of a NAND gate is most critical     Use smaller transistor on A (less capacitance) Boost size of noncritical input A So total resistance is same reset gA = 10/9  gB = 2  gtotal = gA + gB = 28/9 Y  2 A reset 2 Y 4/3 4 Asymmetric gate approaches... a pMOS that is always ON Ratio issue  Make pMOS about ¼ effective strength of pulldown network  1.8 load 1.5 P/2 1.2 Ids P = 24 Vout 16/2 Vin Vout 0.9 0.6 P = 14 0.3 P=4 35 0 0 0.3 0.6 0.9 Vin 1.2 1.5 1.8 PSEUDO-NMOS GATES Design for unit current on output to compare with unit inverter  pMOS fights nMOS  Inverter Y A NAND2 gu gd gavg pu pd pavg = = = = = = A B gu g Y gd avg pu pd pavg Y inputs... symmetric 2 2 A 1 1 B 1 1 Y 16 SKEWED INVERTER o 𝛽𝑛 𝛽𝑝 = 1: un-skewed inv o 𝛽𝑛 𝛽𝑝 > 1: HI-skewed inv o 𝛽𝑛 𝛽𝑝 < 1: LO-skewed inv Transfer characteristics of skewed inverter 17 SKEWED GATES Skewed gates favor one edge over another  Ex: suppose rising output of inverter is most critical   Downsize noncritical nMOS transistor HI-skew inverter unskewed inverter (equal rise resistance) 2 A 2 Y A 1/2  unskewed . CHARACTERIZATION & PERFORMANCE ESTIMATION Static CMOS 1 Ratioed Circuits 2 Dynamic Circuits 3 Pass-transistor Circuits 4 3 LECTURE 06: CIRCUIT CHARACTERIZATION & PERFORMANCE ESTIMATION. Design and Implementation of VLSI Systems Lecture 06 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011. nMOS and pMOS on each input.  All the node voltages in static CMOS must transition between 0 and V DD  propagation delay + power consumption.  Circuit families LECTURE 06: CIRCUIT CHARACTERIZATION