Digital design width CPLD Application and VHDL - Chapter 8 doc

329 ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ ❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ CHAPTER 8 Introduction to Programmable Logic Architectures OUTLINE 8.1 Programmable Sum-of-Products Arrays 8.2 PAL Fuse Matrix and Combinational Outputs 8.3 PAL Outputs with Programmable Polarity 8.4 PAL Devices with Programmable Polarity 8.5 Universal PAL and Generic Array Logic 8.6 MAX7000S CPLD 8.7 FLEX10K CPLD CHAPTER OBJECTIVES Upon successful completion of this chapter, you will be able to: • Draw a diagram showing the basic hardware conventions for a sum-of- products-type programmable logic device. • Describe the structure of a programmable array logic (PAL) AND matrix. • Draw fuses on the logic diagram of a PAL to implement simple logic functions. • Describe the structures of combinational, programmable polarity, and registered PAL outputs. • Determine the number and type of outputs from a PAL/GAL part number. • Explain the structure of an output logic macrocell (OLMC). • State differences between Universal PAL and generic array logic (GAL) and standard PAL. • Interpret the logic diagrams of Universal PAL and GAL devices to deter- mine the number of outputs and product terms and the type of control signals available in a device. • Interpret block diagrams to determine the basic structure of an Altera MAX7000S CPLD, including macrocell configuration, Logic Array Blocks (LABs), control signals, and product term expanders. • State the differences between PLDs based on sum-of-products (SOP) archi- tecture versus look-up table (LUT) architecture. • Interpret block diagrams to determine the basic structure of a logic element in an Altera FLEX10K CPLD, including look-up tables, cascade chains, carry chains, and control signals. • Interpret block diagrams to determine how a logic element in a FLEX10K device relates to the overall structure of the device. • Interpret block diagrams to determine how logic array blocks and embed- ded array blocks relate to the overall structure of a FLEX10K CPLD. I n thepast several chapters, we have beenusingAltera’s MAXϩPLUS II software to make circuit designs for downloading into a complex programmable logic device (CPLD). We have treated this device as a black box—something whose function we design, but whose structure we do not really understand. In this chapter, we will look inside the box. ■ 330 CHAPTER 8 • Introduction to Programmable Logic Architectures Before we examine the structure of an Altera MAX7000S CPLD, we will look at the internal structure of several simpler devices that are based on similar technologies, such as the PAL16L8 and PAL16R8 low-density PLDs (largely for an historical overview), the PALCE16V8, and the GAL22V10. These devices are based on programmable matrices of sum-of-products (SOP) circuits, as is the Altera MAX series of devices. The main programming element is the EEPROM (electrically erasable programmable read-only memory) cell. EEPROM-based devices will retain their programmed data when power is removed from the device. The Altera FLEX series of CPLDs is based on another technology altogether. It stores logic functions in look-up tables (LUTs) that act as truth tables with four input bits. The main logic element of the FLEX series is the SRAM (static random access memory) cell. SRAM-based CPLDs must have their programming data loaded every time they are powered up. They have the advantage of being faster than EEPROM devices, with a higher bit capacity. 8.1 Programmable Sum-of-Products Arrays Product line A single line on a logic diagram used to represent all inputs to an AND gate (i.e., one product term) in a PLD sum-of-products array. Input line A line that applies the true or complement form of an input variable to the AND matrix of a PLD. PAL Programmable array logic. Programmable logic with a fixed OR matrix and a programmable AND matrix. The original programmable logic devices (PLDs) consisted of a number of AND and OR gates organized in sum-of-products (SOP) arrays in which connections were made or broken by a matrix of fuse links. An intact fuse allowed a connection to be made; a blown fuse would break a connection. Figure 8.1a shows a simple fuse matrix connected to a 4-input AND gate. True and complement forms of two variables, A and B, can be connected to the AND gate in any com- bination by blowing selected fuses. In Figure 8.1a, fuses for A ෆ and B are blown. The output of theAND gate represents the product term AB ෆ , the logical product of the intact fuse lines. Figure 8.1b shows a more compact notation for the AND-gate fuse matrix. Rather than showing each AND input individually, a single line, called the product line, goes into the AND gate, crossing the true and complement input lines. An intact connection to an input line is shownby an “X” on the junction between the input line and the product line. A symbol convention similar to Figure 8.1b has been developed for programmable logic. Figure 8.2 shows an example. The circuit shown in Figure 8.2 is a sum-of-products network whose Boolean expression is given by: F ϭ A ෆ B ෆ C ϩ A B ෆ C ෆ The product terms are accumulated by the AND gates as in Figure 8.1b. A buffer having true and complement outputs applies each input variable to the AND matrix, thus producing two input lines. Each product line can be joined to any input line by leaving the corresponding fuse intact at the junction between the input and product lines. If a product line, such as for the third AND gate, has all its fuses intact, we do not show the fuses on that product line. Instead, this condition is indicated by an “X” through the gate. The output of the third AND gate is a logic 0, since (A ෆ A B ෆ B C ෆ C) ϭ 0. This is nec- essary to enable the OR gate output: A ෆ B ෆ C ϩ A B ෆ C ෆ ϩ 0 ϭ A ෆ B ෆ C ϩ A B ෆ C ෆ KEY TERMS 8.1 • Programmable Sum-of-Products Arrays 331 Unconnected inputs are HIGH (e.g., A ෆ и 1 и B ෆ и 1 и 1 иC ϭ A ෆ B ෆ C for the the first prod- uct line). If the unused AND output was HIGH, the function F would be: A ෆ B ෆ C + A B ෆ C ෆ + 1 = 1 The configuration in Figure 8.2, with a programmable AND matrix and a hardwired OR connection, is called PAL (programmable array logic) architecture. 1 Since any combinational logic function can be written in SOP form, any Boolean function can be programmed into these PLDs by blowing selected fuses. The programming B A A B A B B A A B A B a. Crosspoint fuse matrix ( A and B intact ) b. PLD notation for fuse matrix Blown Intact FIGURE 8.1 Crosspoint Fuse Matrix FIGURE 8.2 PLD Symbology 1 PAL is a registered trademark of Vantis Semiconductor. 332 CHAPTER 8 • Introduction to Programmable Logic Architectures is done by special equipment and its associated software. The hardware and software se- lects each fuse individually and applies a momentary high-current pulse if the fuse is to be blown. The main problem with fuse-programmable PLDs is that they can be programmed one time only; if there is a mistake in the design and/or programming or if the design is updated, we must program a new PLD. More recent technology has produced sev- eral types of erasable PLDs, based not on fuses but on floating-gate metal-oxide- semiconductor transistors. These transistors also form the basis of memory technolo- gies such as electrically erasable programmable read-only memory (EEPROM or E 2 PROM). 8.2 PAL Fuse Matrix and Combinational Outputs JEDEC Joint Electron Device Engineering Council JEDEC file An industry-standard form of text file indicating which fuses are blown and which are intact in a programmable logic device. Text file An ASCII-coded document stored on disk. Checksum An error-checking code derived from the accumulated sum of the data being checked. Cell A programmable location in a PLD, specified by the intersection of an input line and a product line. Product line first cell number The lowest cell number on a particular product line in a PAL AND matrix where all cells are consecutively numbered. Input line number A number assigned to a true or complement input line in a PAL AND matrix. Multiplexer A circuit that selects one of several signals to be directed to a single output. Figure 8.3 shows the logic diagram of a PAL16L8 PAL circuit. This device can produce up to eight different sum-of-products expressions, one for each group of AND and OR gates. The device has active-LOW tristate outputs, as indicated by the “L” in the part number. Each is controlled by a product line from the related AND matrix. The pins that can be used only as inputs or outputs are marked “I” or “O,” re- spectively. Six of the pins can be used as inputs or outputs and are marked “I/O.” The I/O pins can also feed back a derived Boolean expression into the matrix, where it can be employed as part of another function. A detail of an I/O section is shown in Figure 8.4. The part number of a PAL device gives the designer information about the number of inputs and outputs and their configurations, as follows: Number of inputs Output type: H ϭ Active HIGH L ϭ Active LOW P ϭ Programmable polarity R ϭ Registered (D flip-flop) X ϭ XOR registered C ϭ Complementary (both HIGH and LOW) Number of (registered) outputs PAL 16 R 8 KEY TERMS 8.2 • PAL Fuse Matrix and Combinational Outputs 333 The numbering system has some potential ambiguities. For example, it is not possible to use 16 inputs and 8 outputs in a PAL16L8 device at the same time; 6 of the inputs are actually input/output pins. Some possible configurations are as follows: 16 inputs (10 dedicated ϩ 6 I/O) and 2 dedicated outputs 10 dedicated inputs and 8 outputs (2 dedicated ϩ 6 I/O) 12 inputs (10 dedicated ϩ 2 I/O) and 6 outputs (2 dedicated ϩ 4 I/O) Each of the outputs of the PAL16L8 is buffered by a tristate inverter, whose ENABLE input is controlled by its own product line. When the ENABLE line of the tristate inverter is FIGURE 8.3 Unprogrammed PAL16L8 334 CHAPTER 8 • Introduction to Programmable Logic Architectures HIGH, the inverter output is the same as it would normally be—a logic HIGH or LOW, de- termined by the state of the corresponding OR gate output. When the ENABLE line is LOW, the inverter output is in the high-impedance state. The output acts as an open circuit, neither HIGH nor LOW; it is as though the output was completely disconnected from the circuit. The inverter is permanently enabled if all fuses on the ENABLE product line are blown, and permanently disabled if these fuses are all intact. Published logic diagrams of PAL devices generally do not have fuses drawn on them. This allows us to draw fuses for any application. In practice, PLDs have become too complex to manually draw fuse maps for most applications. Historically, PLD programming would begin with fuses drawn on a logic diagram, and each fuse would be selected and blown individually by someone operating a hardware de- vice constructed for such a purpose. Fuse assignment is now done with special software such asABEL, CUPL, or PALASM. These programs will take inputs such as Boolean equations, truth tables, or other forms and produce the simplest SOP solution to the particular problem. (MAXϩPLUS II is not config- ured to generate programming data for low-density PALs, although it can generate data for similar devices in the Altera Classic PLD series.) The end result of such software is a JEDEC file, an industry-standard way of listing which fuses in the PLD should remain intact and which should be blown. The JEDEC file is stored on disk as an ASCII text file. Most PLD programmers will accept the JEDEC file and use it as a template for blowing fuses in the target device. Fuse locations, called cells, are specified by two numbers: the product line first cell number, shown along the left side of the diagram, and the input line number, shown along the top. The address of any particular fuse is the sum of its product line first cell number and its input line number. The fuses on the PAL16L8 device are numbered from 0000 to 2047 (ϭ 2016 ϩ 31). Figure 8.5 shows an example of a JEDEC file for a PAL16L8 application. The file starts with an ASCII “Start Text” character (^B). Next is some information required by the PAL programmer about the type of device (PAL16L8), number of fuses (2048), and so forth. The fuse information starts with the line L0000, which is the first product line. The 1s and 0s which follow show the programmed state of each cell in each product line; a 1 is a blown fuse and a 0 is an intact fuse. In other words, each 0 in the JEDEC file represents an X in the same position on the PAL logic diagram. The product terms for first sum-of-products output are set by the states of fuses 0000 to 0255 (eight product lines). In the file shown, all fuses are blown in the first product I/O FIGURE 8.4 PAL16L8 I/O Section 8.2 • PAL Fuse Matrix and Combinational Outputs 335 line, the second product line shows three intact fuses, and so forth. Since all fuses are intact in the last three lines, they need not be shown in the JEDEC file. Whenever some unprogrammed product lines are omitted from the fuse map, the last fuse line shown ends with an asterisk (*). The next line with programmed fuses is indicated by a new fuse number. For example, the second group of fuses (0256 to 0511) in Figure 8.5 begins after the line marked L0256 in the JEDEC file. The remaining fuse lines are similarly indicated. The JEDEC file in Figure 8.5 ends with a hexadecimal checksum (C8DCF), an error- checking code derived from the programming data, and an ASCII “End Text” code (^C). FIGURE 8.5 Sample JEDEC File 336 CHAPTER 8 • Introduction to Programmable Logic Architectures In order to examine the general principle of fuse programming, let us develop the pro- grammed logic diagram for a common combinational circuit: a 4-to-1 multiplexer. (After developing the fuse maps for several examples, we will not refer to this technique again.) This circuit, shown in Figure 8.6a, directs one of four input logic signals, D 0 to D 3 ,to output Y, depending on the state of two select inputs S 0 and S 1 . The circuit works on the enable/inhibit principle; each AND gate is enabled by a different combination of S 1 S 0 . The binary state of the select inputs is the same as the decimal subscript of the selected data input. For instance, S 1 S 0 ϭ 10 selects data input D 2 ; the AND gate corresponding to D 2 is enabled and the other three ANDs are inhibited. The logic equation for output Y is given by: Y ϭ D 0 S ෆ 1 S ෆ 0 ϩ D 1 S ෆ 1 S 0 ϩ D 2 S 1 S ෆ 0 ϩ D 3 S 1 S 0 Since the outputs of the PAL16L8 are active LOW, as illustrated in Figure 8.6b, we should rewrite the equation as follows: Y ෆ ϭ D ෆ 0 S ෆ 1 S ෆ 0 ϩ D ෆ 1 S ෆ 1 S 0 ϩ D ෆ 2 S 1 S ෆ 0 ϩ D ෆ 3 S 1 S 0 The D inputs must be complemented to reverse the effect of the active-LOW output. The output is enabled when the EN input is HIGH. Figure 8.7 shows the PAL16L8A logic diagram with fuses for the multiplexer application. 8.3 PAL Outputs With Programmable Polarity The multiplexer application developed in the previous section uses a PAL device whose output is always fixed at the active-LOW polarity. This fixed polarity is suitable for most applications, but Boolean functions that would normally have active-HIGH outputs must be implemented in DeMorgan equivalent form, which is not always very straightforward. Some applications require both active-HIGH and active-LOW outputs. In such cases, it is useful to have a device whose output polarity is fuse programmable. Figure 8.8 shows the logic diagram of a PAL20P8 PAL device. This device is the same as a PAL16L8, except that there are four more dedicated inputs, and the polarity of each output is programmable. The Exclusive OR gate on each output is programmed to act as ei- ther an inverter or a buffer. When its associated fuse is intact, the XOR input is grounded and passes the output of its related SOP network in true form. When combined with the output inverter, this produces an active-LOW output. When the polarity fuse is blown, the fused XOR input floats to the HIGH state, inverting the SOP output; the output pin be- comes active HIGH. FIGURE 8.6 4-to-1 Multiplexer Circuits 8.3 • PAL Outputs With Programmable Polarity 337 The polarity fuses are given numbers higher than those of the main fuse array. In this case, the product line fuses are numbered 0000 to 2559 and the output polarity fuses are numbered 2560 to 2567. Figure 8.9 illustrates the selection of output polarity. Two Boolean functions, F1 and F2, are programmed into the fuse array, with outputs at pins (17) and (15), respectively. The equations are: F1 ϭ A B ϩ A ෆ B ෆ F2 ϭ A B ϩ A ෆ B ෆ FIGURE 8.7 Programmed Logic Diagram for a 4-to-1 Multiplexer FIGURE 8.8 PAL20P8 Logic Diagram 338 CHAPTER 8 • Introduction to Programmable Logic Architectures We could, if we chose, rewrite F2 to show the output as active LOW: F ෆ ෆ 2 ෆ ϭ A B ϩ A ෆ B ෆ The portion of the PAL20P8 logic diagram shown in Figure 8.9 represents the fuses required to program F1 and F2. Pins (14) and (16) supply inputs A and B to the matrix. The ENABLE lines of the tristate output buffers float HIGH, since all fuses are blown on the corresponding product lines, thus permanently enabling the output buffers. The fuses numbered 2565 and 2567 select the polarity at pins (15) and (17). Fuse 2565 is blown. The fused input to the corresponding XOR gate floats HIGH, thus making the gate into an inverter. Combined with the tristate buffer, this makes pin (17) active HIGH. Fuse 2567 is intact. This grounds the input to the corresponding XOR gate, making the gate into a noninverting buffer. Combined with the tristate output buffer, this makes pin (15) active LOW. [...]... LABs and a number of 3 58 C H A P T E R 8 • Introduction to Programmable Logic Architectures Dedicated Inputs and Global Signals Row Interconnect 6 LAB Local Interconnect 4 4 16 Carry-In and Cascade-In 2 24 8 4 4 LE1 4 LE2 4 LAB Control Signals LE3 Column-to-Row Interconnect 16 8 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 8 2 Column Interconnect Carry-Out and Cascade-Out FIGURE 8. 26 FLEX10K LAB (Courtesy of Altera)... macrocells have? 8. 11 State the four configurations possible with a macrocell in a GAL22V10 8. 26 8. 12 Is there a global output enable function available for a PALCE16V8? For a GAL22V10? 8. 7 FLEX10K CPLD 8. 13 Can the registered outputs of a PALCE16V8 be clocked by a product term function from the PAL AND matrix? 8. 27 Briefly state the difference between CPLDs having sumof-products architecture and look-up table... 1 0 1 0 1 362 C H A P T E R 8 • Introduction to Programmable Logic Architectures The Boolean equations for the BCD-to-2421 decoder are: 8. 17 How many macrocells are available in the following CPLDs: a EPM7032 b EPM7064 c EPM7128S d EPM7160S 8. 18 Which of the CPLDs listed in Problem 8. 17 are in-system programmable? What does it mean when a device is insystem programmable? 8. 19 How many logic array blocks... in an Altera MAX7000S CPLD? Y4 ϭ D4 ϩ D3D2 ϩ D3D1 Y3 ϭ D4 ϩ D3D2 ϩ D3D1 ෆ Y2 ϭ D4 ϩ D3D2 ϩ D3D2D1 ෆ ෆ Y1 ϭ D1 8. 5 Repeat Problem 8. 4 for a 2421-to-BCD code converter 8. 4 PAL Devices with Registered Outputs 8. 6 What is a registered output? 8. 20 8. 7 State the number of registered outputs for each of the following PAL devices: How many user I/O pins are there in an EPM7128SLC84 CPLD? How many pins per... problems Section 8. 1 Introduction to Progammable Logic Section 8. 2 PAL Fuse Matrix and Combinational Outputs 8. 4 Make a photocopy of Figure 8. 8 (PAL20P8 logic diagram) Draw fuses on the PAL20P8 logic diagram showing how to make a BCD-to-2421 code converter, as developed in Example 3.22 Table 8. 3 shows how the two codes relate to each other The equations are listed on page 362 Section 8. 3 PAL Outputs... 8. 23 FLEX10K Logic Element (Courtesy of Altera) AND Cascade Chain d[3 0] OR Cascade Chain d[3 0] LUT LUT LE1 d[7 4] LE1 d[7 4] LUT LUT LE2 d[(4n-1) (4n-4)] d[(4n-1) (4n-4)] LUT LEn FIGURE 8. 24 Cascade Chain Operation (Courtesy of Altera) LE2 LUT LEn 8. 7 FIGURE 8. 25 Carry Chain Operation (n-bit Full Adder) (Courtesy of Altera) • FLEX10K CPLD 357 Carry-In a1 LUT Register s1 b1 Carry Chain LE1 a2 LUT... be optimum for the design Third, a standard PAL cannot be programmed while it is installed in a circuit A number of low-density PLDs have been developed to address these concerns Devices such as the PALCE16V8 Universal PAL (Vantis Corporation), and the GAL16V8 and GAL22V10 Generic Array Logic (Lattice Semiconductor)* are based on sum-of-products fuse matrices, just as the earlier-version PALs However,... 0 X 8 SG1 1 1 VCC 0 X 1 0 56 SL00 D 63 SL10 SL01 1 1 0 0 1 0 0 1 1 0 0 X SG1 GND I/O1 1 0 1 1 0 X SG1 I8 I/O2 1 0 Q 7 I7 15 I/O3 1 0 Q 6 I6 349 • Universal PAL and Generic Array Logic (GAL) Q 1 0 Q 1 0 1 1 0 X 9 10 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 SG0 SL00 13 FIGURE 8. 17 (b) (PALCE16V8 Logic Diagram OE/19 350 C H A P T E R 8 • Introduction to Programmable Logic Architectures FIGURE 8. 18 GAL22V10... table and then program the appropriate cells in a CPLD AND matrix The look-up table implementation of this function is based on a totally different concept 8. 7 Table 8. 2 Truth Table for a 2-bit Equality Comparator • FLEX10K CPLD 355 LUT A1 A0 B1 B0 Decimal AEQB 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 2 3 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 4 5 6 7 0 1 0 0 A1 A0 AEQB B1 B0 a 2-bit comparator look-up... flip-flop The active buffer passes the contents of the flip-flop to AEQB; all other buffers are in the high-impedance state, blocking the data from the other flip-flops The contents of the flip-flops are loaded when the look-up table is configured (programmed) with the required function After that the flip-flops retain their information until they are reconfigured For our comparator example, flip-flops 0, 5, 10, and . (17) and (15), respectively. The equations are: F1 ϭ A B ϩ A ෆ B ෆ F2 ϭ A B ϩ A ෆ B ෆ FIGURE 8. 7 Programmed Logic Diagram for a 4-to-1 Multiplexer FIGURE 8. 8 PAL20P8 Logic Diagram 3 38 CHAPTER 8. with Programmable Polarity 8. 4 PAL Devices with Programmable Polarity 8. 5 Universal PAL and Generic Array Logic 8. 6 MAX7000S CPLD 8. 7 FLEX10K CPLD CHAPTER OBJECTIVES Upon successful completion of this chapter, . such as the PAL16L8 and PAL16R8 low-density PLDs (largely for an historical overview), the PALCE16V8, and the GAL22V10. These devices are based on programmable matrices of sum-of-products (SOP)