Digital design width CPLD Application and VHDL - Chapter 3 ppt

57 ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ ❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ CHAPTER 3 Boolean Algebra and Combinational Logic OUTLINE 3.1 Boolean Expressions, Logic Diagrams, and Truth Tables 3.2 Sum-of-Products (SOP) and Product- of-Sums (POS) Forms 3.3 Theorems of Boolean Algebra 3.4 Simplifying SOP and POS Expressions 3.5 Simplification by the Karnaugh Map Method CHAPTER OBJECTIVES Upon successful completion of this chapter you will be able to: • Explain the relationship between the Boolean expression, logic diagram, and truth table of a logic gate network and be able to derive any one from either of the other two. • Draw logic gate networks in such a way as to cancel out internal inversions automatically (bubble-to-bubble convention). • Write the sum of products (SOP) or product of sums (POS) forms of a Boolean equation. • Use rules of Boolean algebra to simplify the Boolean expressions derived from logic diagrams and truth tables. • Apply the Karnaugh map method to reduce Boolean expressions and logic circuits to their simplest forms. I n Chapter 3, we will examine the rudiments of combinational logic. A combinational logic circuit is one in which two or more gates are connected together to combine sev- eral Boolean inputs. These circuits can be represented several ways, as a logic diagram, truth table, or Boolean expression. A Boolean expression for a network of logic gates is often not in its simplest form. In such a case, we may be using more components than would be required for the job, so it is of benefit to us if we can simplify the Boolean expression. Several tools are available to us, such as Boolean algebra and a graphical technique known as Karnaugh mapping. We can also simplify the Boolean expression by taking care to draw the logic diagrams in such a way as to automatically eliminate inverting functions within the circuit. ■ 58 CHAPTER 3 • Boolean Algebra and Combinational Logic 3.1 Boolean Expressions, Logic Diagrams and Truth Tables Logic gate network Two or more logic gates connected together. Logic diagram A diagram, similar to a schematic, showing the connection of logic gates. Combinational logic Digital circuitry in which an output is derived from the combination of inputs, independent of the order in which they are applied. Combinatorial logic Another name for combinational logic. In Chapter 2, we examined the functions of single logic gates. However, most digital cir- cuits require multiple gates. When two or more gates are connected together, they form a logic gate network. These networks can be described by a truth table, a logic diagram (i.e., a circuit diagram), or a Boolean expression. Any one of these can be derived from any other. A digital circuit built from gates is called a combinational (or combinatorial) logic circuit. The output of a combinational circuit depends on the combination of inputs. The inputs can be applied in any sequence and still produce the same result. For example, an AND gate output will always be HIGH if all inputs are HIGH, regardless of the order in which they became HIGH. This is in contrast to sequential logic, in which sequence mat- ters; a sequential logic output may have a different value with two identical sets of inputs if those inputs were applied in a different order. We will study sequential logic in a later chapter. Boolean Expressions from Logic Diagrams Bubble-to-bubble convention The practice of drawing gates in a logic diagram so that inverting outputs connect to inverting inputs and noninverting outputs con- nect to noninverting inputs. Order of precedence The sequence in which Boolean functions are performed, unless otherwise specified by parentheses. Writing the Boolean expression of a logic gate network is similar to finding the expression for a single gate. The difference is that in a multiple gate network, the inputs will usually not consist of single variables, but compound expressions that represent outputs of previ- ous gates. These compound expressions are combined according to the same rules as single vari- ables. In an OR gate, with inputs x and y, the output will always be x ϩ y regardless of whether x and y are single variables (e.g., x ϭ A, y ϭ B, output ϭ A ϩ B) or compound ex- pressions (e.g., x ϭ AB, y ϭ AC, output ϭ AB ϩ AC). Figure 3.1 shows a simple logic gate network, consisting of a single AND and a single OR gate. The AND gate combines inputs A and B to give the output expression AB. The OR combines the AND function and input C to yield the compound expression AB ϩ C. KEY TERMS KEY TERMS A AB B C AB CY ϩϭ FIGURE 3.1 Boolean Expression from a Gate Network 3.1 • Boolean Expressions, Logic Diagrams and Truth Tables 59 ❘❙❚ EXAMPLE 3.1 Derive the Boolean expression of the logic gate network shown in Figure 3.2a. A AB CD B C D ABY ϩϭ CD A B C D Y a. Logic gate network b. Boolean expression from logic gate network FIGURE 3.2 Example 3.1 Figure 3.2b shows the gate network with the output terms indicated for each gate. The AND and NAND functions are combined in an OR function to yield the output expression: Y ϭ AB ϩ C ෆ D ෆ ❘❙❚ The Boolean expression in Example 3.1 includes a NAND function. It is possible to draw the NAND in its DeMorgan equivalent form. If we choose the gate symbols so that outputs with bubbles connect to inputs with bubbles, we will not have bars over groups of variables, except possibly one bar over the entire function. In a circuit with many inverting functions (NANDs and NORs), this results in a cleaner notation and often a clearer idea of the function of the circuit. We will follow this notation, which we will refer to as the bubble- to-bubble convention, as much as possible. ❘❙❚ EXAMPLE 3.2 Redraw the circuit in Figure 3.2 to conform to the bubble-to-bubble convention. Write the Boolean expression of the new logic diagram. Solution A AB B C D AB CY ϩϭ D ϩ CD ϩ FIGURE 3.3 Example 3.2 Using DeMorgan Equivalents to Simplify a Circuit Figure 3.3 shows the new circuit. The NAND has been converted to its DeMorgan equivalent so that its active-HIGH output drives an active-HIGH input on the OR gate. The new Boolean expression is Y ϭ AB ϩ C ෆ ϩ D ෆ . ❘❙❚ Boolean functions are governed by an order of precedence. Unless otherwise speci- fied, AND functions are performed first, followed by ORs. This order results in a form sim- ilar to that of linear algebra, where multiplication is performed before addition, unless otherwise specified. Solution 60 CHAPTER 3 • Boolean Algebra and Combinational Logic Figure 3.4 shows two logic diagrams, one whose Boolean expression requires paren- theses and one that does not. A AB B C AB AC ϩ AC a. No parentheses required (AND, then OR) A B C (A B ϩ AB ϩ C) ϩ (A B) ϩ AB ϩ C ϩ b. Parentheses required (OR, then AND) FIGURE 3.4 Order of Precedence The AND functions in Figure 3.4a are evaluated first, eliminating the need for paren- theses in the output expression. The expression for Figure 3.4b requires parentheses since the ORs are evaluated first. ❘❙❚ EXAMPLE 3.3 Write the Boolean expression for the logic diagrams in Figure 3.5. FIGURE 3.5 Example 3.5 Order of Precedence A B Y S C a. P Q R b. 3 2 1 3 2 1 Solution Examine the output of each gate and combine the resultant terms as re- quired. Figure 3.5a: Gate 1: A ෆ и B ෆ Gate 2: B и C Gate 3: Y ϭ Gate 1 ϩ Gate2 ϭ A ෆ и B ෆ ϩ B и C Figure 3.5b: Gate 1: P ෆ ϩ Q ෆ ϭ P ϩ Q ෆ Gate 2: Q ϩ R ෆ Gate 3: S ϭ G ෆ a ෆ t ෆ e ෆ 1 ෆ и G ෆ a ෆ t ෆ e ෆ 2 ෆ ϭ (P ϩ Q ෆ )(Q ϩ R ෆ ) ϭ (P ϩ Q ෆ )(Q ϩ R ෆ ) 3.1 • Boolean Expressions, Logic Diagrams and Truth Tables 61 Note that when two bubbles touch, they cancel out, as in the doubly inverted P input or the connection between the outputs of gates 1 and 2 and the inputs of gate 3. In the re- sultant Boolean expression, bars of the same length cancel; bars of unequal length do not. ❘❙❚ ❘❙❚ SECTION 3.1A REVIEW PROBLEM 3.1 Write the Boolean expression for the logic diagrams in Figure 3.6, paying attention to the rules of order of precedence. A B OUT C D a. W X Z Y b. Y FIGURE 3.6 Section Review Problem 3.1 Logic Diagrams from Boolean Expressions Levels of gating The number of gates through which a signal must pass from in- put to output of a logic gate network. Double-rail inputs Boolean input variables that are available to a circuit in both true and complement form. Synthesis The process of creating a logic circuit from a description such as a Boolean equation or truth table. We can derive a logic diagram from a Boolean expression by applying the order of prece- dence rules. We examine an expression to create the first level of gating from the circuit in- puts, then combine the output functions of the first level in the second level gates, and so forth. Input inverters are often not counted as a gating level, as we usually assume that each variable is available in both true (noninverted) and complement (inverted) form. When in- put variables are available to a circuit in true and complement form, we refer to them as double-rail inputs. The first level usually will be AND gates if no parentheses are present, OR gates if parentheses are used. (Not always, however; parentheses merely tell us which functions to synthesize first.) Although we will try to eliminate bars over groups of variables by use of DeMorgan’s theorems and the bubble-to-bubble convention, we should recognize that a bar over a group of variables is the same as having those variables in parentheses. Let us examine the Boolean expression Y ϭ AC ϩ BD ϩ AD. Order of precedence tells us that we synthesize the AND functions first. This yields three 2-input AND gates, with outputs AC, BD, and AD, as shown in Figure 3.7a. In the next step, we combine these AND functions in a 3-input OR gate, as shown in Figure 3.7b. KEY TERMS 62 CHAPTER 3 • Boolean Algebra and Combinational Logic When the expression has OR functions in parentheses, we synthesize the ORs first, as for the expression Y ϭ (A ϩ B)(A ϩ C ϩ D)(B ϩ C). Figure 3.8 shows this process. In the first step, we synthesize three OR gates for the terms (A ϩ B), (A ϩ C ϩ D), and (B ϩ C). We then combine these terms in a 3-input AND gate. FIGURE 3.7 Logic Diagram for Y ϭ AC ϩ BD ϩ AD A AC BD AD B C D a. ANDs first A B C D b. Combine ANDs in an OR gate ACYBD ϩϭ AD ϩ C D A B Y (A B)(A C a. ORs first b. Combine ORs in an AND gate C D A B (A (B ϩ B) (A C D) C) ϭϩ ϩ D)(B ϩ C) ϩ ϩ ϩϩ FIGURE 3.8 Logic Diagram for Y ϭ (A ϩ B) (A ϩ C ϩ D) (B ϩ C) ❘❙❚ EXAMPLE 3.4 Synthesize the logic diagrams for the following Boolean expressions: 1. P ϭ QR ෆ S ෆ ϩ S ෆ T 2. X ϭ (W ϩ Z ϩ Y)V ෆ ϩ (W ෆ ϩ V)Y ෆ Solution 1. Recall that a bar over two variables acts like parentheses. Thus the QR ෆ S ෆ term is synthe- sized from a NAND, then an AND, as shown in Figure 3.9a. Also shown is the second AND term, S ෆ T. 3.1 • Boolean Expressions, Logic Diagrams and Truth Tables 63 Figure 3.9b shows the terms combined in an OR gate. FIGURE 3.9 Example 3.4 Logic Diagram of P ϭ QR ෆ S ෆ ϩ S ෆ T R Q RS S T S ST QRS a. Combine inputs (NAND, then AND) R Q RS S T S ST QRS P QRS ST b. First and second level gates combined in and OR ϭϩ 2. Figure 3.10 shows the synthesis of the second logic diagram in three stages. Figure 3.10a shows how the circuit inputs are first combined in two OR gates. We do this first because the ORs are in parentheses. In Figure 3.10b, each of these functions is com- bined in an AND gate, according to the normal order of precedence. The AND outputs are combined in a final OR function, as shown in Figure 3.10c. FIGURE 3.10 Example 3.4 Logic Diagram for X ϭ (W ϩ Z ϩ Y)V ෆ ϩ (W ෆ ϩ V)Y ෆ W W Z Y V b. Combine with ANDs (order of precedence) c. Find output (OR) a. ORs first (parentheses) W W W Z Y V Y V (W W W Z Y V W Y V ϩ Z W W ϩ V Y ϩ W ϩ Z ϩ V Y ϩ W ϩ Z ϩ V)Y (W ϩ X(W ϭ X ϩ (W ϩ Y)V ϩ Z ϩ Y)V ϩ V Y ϩ (W ϩ Z Y)V ϩ (W V)Y V)Y ϩ ϩ 64 CHAPTER 3 • Boolean Algebra and Combinational Logic ❘❙❚ EXAMPLE 3.5 Use DeMorgan’s theorem to modify the Boolean equation in part 1 of Example 3.4 so that there is no bar over any group of variables. Redraw Figure 3.9b to reflect the change. Solution P ϭ QR ෆ S ෆ ϩ S ෆ T ϭ Q(R ෆ ϩ S ෆ ) ϩ S ෆ T Figure 3.11a shows the modified logic diagram. The levels of gating could be further reduced from three to two (not counting input inverters) by “multiplying through” the parentheses to yield the expression: P ϭ QR ෆ ϩ QS ෆ ϩ S ෆ T Figure 3.11b shows the logic diagram for this form. We will examine this simplifica- tion procedure more formally in a later section of this chapter. FIGURE 3.11 Example 3.5: Reworking Figure 3.9b a. Logic diagram of P ϭ Q(R ϩ S) ϩ ST b. Logic diagram of P ϭ QR ϩ QS ϩ ST Q(R ST Q R S T S QR Q R S T QS ST P ϩ S) Q(R ϩϭ S) ϩ ST P QR ϩϭ QS ϩ ST (R ϩ S) ❘❙❚ Truth Tables from Logic Diagrams or Boolean Expressions There are two basic ways to find a truth table from a logic diagram. We can examine the output of each gate in the circuit and develop its truth table. We then use our knowledge of gate properties to combine these intermediate truth tables into the final output truth table. Alternatively, we can develop a Boolean expression for the logic diagram and by examin- ing the expression fill in the truth table in a single step. The former method is more thor- ough and probably easier to understand when you are learning the technique. The latter method is more efficient, but requires some practice and experience. We will look at both. Examine the logic diagram in Figure 3.12. Since there are three binary inputs, there will be eight ways those inputs can be combined. Thus, we start by making an 8-line truth table, as in Table 3.1. FIGURE 3.12 Logic Diagram for AB ϩ C AB A B C AB ϩ C 3.1 • Boolean Expressions, Logic Diagrams and Truth Tables 65 The OR gate output will describe the function of the whole circuit. In order to assess the OR function, we must first evaluate the AND output. We add a column to the truth table for the AND gate and look for the lines in the table where both A AND B equal logic 1 (in this case, the last two rows). For these lines, we write a 1 in the AB column. Next, we look at the values in column C and the AB column. If there is a 1 in either column, we write a 1 in the column for the final output. Table 3.1 Truth Table for Figure 3.12 A B C AB AB ϩ C 000 0 0 001 0 1 010 0 0 011 0 1 100 0 0 101 0 1 110 1 1 111 1 1 ❘❙❚ EXAMPLE 3.6 Derive the truth table for the logic diagram shown in Figure 3.13. FIGURE 3.13 Example 3.6 Logic Diagram A B C Solution The Boolean equation for Figure 3.13 is (A ෆ ϩ B ෆ )(A ϩ C). We will create a column for each input variable and for each term in parentheses, as well as a column for the final output. Table 3.2 shows the result. For the lines where A OR B is 0, we write a 1 in the (A ෆ ϩ B ෆ ) column. Where A OR C is 1, we write a 1 in the (A ϩ C) column. For the lines where there is a 1 in both the (A ෆ ϩ B ෆ ) AND (A ϩ C) columns, we write a 1 in the final out- put column. Table 3.2 Truth Table for Figure 3.13 ABC (A ෆ ϩ B ෆ )(A ϩ C)(A ෆ ϩ B ෆ )(A ϩ C) 000 1 0 0 001 1 1 1 010 1 0 0 011 1 1 1 100 1 1 1 101 1 1 1 110 0 1 0 111 0 1 0 ❘❙❚ 66 CHAPTER 3 • Boolean Algebra and Combinational Logic Another approach to finding a truth table involves analysis of the Boolean expression of a logic diagram. The logic diagram in Figure 3.14 can be described by the Boolean ex- pression Y ϭ A ෆ BC ϩ A ෆ C ෆ ϩ B ෆ D ෆ . A B C D Y FIGURE 3.14 Logic Diagram Table 3.3 Truth Table for Figure 3.14 ABCD Y terms 0000 1 A ෆ C ෆ ,B ෆ D ෆ 0001 1 A ෆ C ෆ 0010 1 B ෆ D ෆ 0011 0 0100 1 A ෆ C ෆ 0101 1 A ෆ C ෆ 0110 1 A ෆ BC 0111 1 A ෆ BC 1000 1 B ෆ D ෆ 1001 0 1010 1 B ෆ D ෆ 1011 0 1100 0 1101 0 1110 0 1111 0 ❘❙❚ SECTION 3.16 REVIEW PROBLEM 3.2 Find the truth table for the logic diagram shown in Figure 3.15. A B C Y FIGURE 3.15 Section Review Problem 3.2 We can examine the Boolean expression to determine that the final output of the cir- cuit will be HIGH under one of the following conditions: 1. A ϭ 0 AND B ϭ 1 AND C ϭ 1; 2. A ϭ 0 AND C ϭ 0; 3. B ϭ 0 AND D ϭ 0. All we have to do is look for these conditions in the truth table and write a 1 in the out- put column whenever a condition is satisfied. Table 3.3 shows the result of this analysis with each line indicating which term, or terms, contribute to the HIGH output. [...]... bar) 3 Combine all minterms in an OR function ❘❙❚ EXAMPLE 3. 7 Tables 3. 5 and 3. 6 show the truth tables for the Exclusive OR and the Exclusive NOR functions Derive the sum-of-products expression for each of these functions and draw the logic diagram for each one Table 3. 5 XOR Truth Table Table 3. 6 XNOR Truth Table A B AᮍB A B A ᮍB 0 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 0 0 1 3. 2 • Sum-of-Products and. .. reading the output for each one Suppose the unknown circuit in Figure 3. 16 yields the truth table shown in Table 3. 4 The truth table output is HIGH for three conditions: 1 When A AND B AND C are all LOW, OR 2 When A is LOW AND B AND C are HIGH, OR 3 When A is HIGH AND B AND C are LOW Table 3. 4 Truth Table for Figure 3. 19 FIGURE 3. 16 Digital Circuit with Unknown Function A B C Y 0 0 0 0 1 1 1 1 0 0 1.. .3. 2 67 • Sum-of-Products and Product-of-Sums Forms 3. 2 Sum-of-Products and Product-of-Sums Forms KEY TERMS Product term A term in a Boolean expression where one or more true or complement variables are ANDed (e.g., ෆ C ) Aෆ Minterm A product term in a Boolean expression where all possible variables appear... C D (A ϩ ෆ ϩ ෆ ϩ ෆ ) ෆ B C D The logic circuits are shown in Figures 3. 21 and 3. 22 72 C H A P T E R 3 • Boolean Algebra and Combinational Logic FIGURE 3. 21 Example 3. 8 SOP Form FIGURE 3. 22 Example 3. 8 POS Form ❘❙❚ 3. 3 • Theorems of Boolean Algebra 73 ❘❙❚ SECTION 3. 2 REVIEW PROBLEM 3. 3 Find the SOP and POS forms of the Boolean functions represented by the following truth tables a A B C b A B C Y Y... (Theorem 22) Figure 3. 31 shows the logic circuits for the left and right sides of the equation for Theorem 23 This theorem is a special case of one of the distributive properties, Theorem 6, where w ϭ x Proof: FIGURE 3. 31 Theorem 23 ❘❙❚ EXAMPLE 3. 12 Simplify the following Boolean expressions, using Theorem 23 and other rules of Boolean algebra Draw the logic circuits of the unsimplified and simplified expressions... expressions a L ϭ (M ϩ ෆ )(M ϩ ෆ) N P b Y ϭ (AෆϩෆB ϩ AB)(AෆϩෆB ϩ C) ෆෆෆ ෆෆෆ Solution Figure 3. 32 shows the logic circuits for the unsimplified and simplified versions of the above expressions FIGURE 3. 32 Example 3. 12 Logic Circuits for Unsimplified and Simplified Expressions 3. 3 • Theorems of Boolean Algebra 83 Theorem 23: (x ϩ y)(x ϩ z) ϭ x ϩ yz P a Let x ϭ M, let y ϭ ෆ, let z ϭ ෆ: N L ϭ (x ϩ y)(x ϩ z) ϭ x... or variables Table 3. 9 Truth Table for the SOP and POS Networks in Figure 3. 35 A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Earlier in this chapter, we discovered that we can generate a Boolean equation from a truth table and express it in sum-of-products (SOP) or product-of-sums (POS) form From this equation, we can develop a logic circuit diagram The next step in the design or analysis... Section 3. 2, we found the SOP and POS forms of the Boolean expression represented by Table 3. 9 These forms yield the logic diagrams shown in Figures 3. 17 and 3. 20 For convenience, the circuits are illustrated again in Figure 3. 35 The corresponding algebraic expressions can be simplified by the rules of Boolean algebra to give us a simpler circuit in each case 1 0 0 1 1 0 0 0 FIGURE 3. 35 Unsimplified SOP and. .. Figure 3. 38 Shows the logic diagram of the simplified expression A Table 3. 11 Truth Table for Section Review Problem A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 B Y ϭ AB ϩ AD D FIGURE 3. 38 Example 3. 14 Simplified SOP Circuit ❘❙❚ SECTION 3. 4 REVIEW PROBLEM 3. 5 Find the maximum SOP and POS simplifications for the function represented by Table 3. 11 ❘❙❚ 90 C H A P T E R 3 • Boolean... to implement For example, the logic circuit in Figure 3. 21 requires eight 4-input AND gates and an 8-input OR gate Using Boolean algebra, we can reduce its Boolean expression to Y ϭ AD ϩ A B C ϩ A B D ϩ A B ෆ This form can be implemented with 4 AND gates and ෆ ෆෆෆ ෆෆ C a 4-input OR You will use a simplification technique for this example in an end-ofchapter problem In the meantime, let us examine some . Figures 3. 21 and 3. 22. 72 CHAPTER 3 • Boolean Algebra and Combinational Logic FIGURE 3. 22 Example 3. 8 POS Form FIGURE 3. 21 Example 3. 8 SOP Form ❘❙❚ 3. 3 • Theorems of Boolean Algebra 73 ❘❙❚ SECTION 3. 2. HIGH output. 3. 2 • Sum-of-Products and Product-of-Sums Forms 67 3. 2 Sum-of-Products and Product-of-Sums Forms Product term A term in a Boolean expression where one or more true or comple- ment variables. 57 ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ ❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ CHAPTER 3 Boolean Algebra and Combinational Logic OUTLINE 3. 1 Boolean Expressions, Logic Diagrams, and Truth Tables 3. 2 Sum-of-Products (SOP) and Product- of-Sums (POS) Forms 3. 3 Theorems