Digital design width CPLD Application and VHDL - Chapter 7 doc

275 ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ ❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ CHAPTER 7 Introduction to Sequential Logic OUTLINE 7.1 Latches 7.2 NAND/NOR Latches 7.3 Gated Latches 7.4 Edge-Triggered D Flip-Flops 7.5 Edge-Triggered JK Flip-Flops 7.6 Edge-Triggered T Flip-Flops 7.7 Timing Parameters CHAPTER OBJECTIVES Upon successful completion of this chapter, you will be able to: • Explain the difference between combinational and sequential circuits. • Define the set and reset functions of an SR latch. • Draw circuits, function tables, and timing diagrams of NAND and NOR latches. • Explain the effect of each possible input combination to a NAND and a NOR latch, including set, reset, and no change functions, as well as the am- biguous or forbidden input condition. • Design circuit applications that employ NAND and NOR latches. • Describe the use of the ENABLE input of a gated SR or D latch as an en- able/inhibit function and as a synchronizing function. • Outline the problems involved with using a level-sensitive ENABLE input on a gated SR or D latch. • Explain the concept of edge-triggering and why it is an improvement over level-sensitive enabling. • Draw circuits, function tables, and timing diagrams of edge-triggered D, JK, and T flip-flops. • Describe the toggle function of a JK flip-flop and a T flip-flop. • Describe the operation of the asynchronous preset and clear functions of D, JK, and T flip-flops and be able to draw timing diagrams showing their functions. • Use MAXϩPLUS II to create simple circuits and simulations with D latches and D, JK, and T flip-flops. • Create simple flip-flop designs using VHDL. T he digital circuits studied to this point have all been combinational circuits, that is, cir- cuits whose outputs are functions only of their present inputs. A particular set of input states will always produce the same output state in a combinational circuit. 276 CHAPTER 7 • Introduction to Sequential Logic This chapter will introduce a new category of digital circuitry: the sequential circuit. The output of a sequential circuit is a function both of the present input conditions and the previous conditions of the inputs and/or outputs. The output depends on the sequence in which the inputs are applied. We will begin our study of sequential circuits by examining the two most basic se- quential circuit elements: the latch and the flip-flop, both of which are part of the general class of circuits called bistable multivibrators. These are similar devices, each being used to store a single bit of information indefinitely. The difference between a latch and a flip- flop is the condition under which the stored bit is allowed to change. Latches and flip-flops are also used as integral parts of more complex devices, such as programmable logic devices (PLDs), usually when an input or output state must be stored. ■ 7.1 Latches Sequential circuit A digital circuit whose output depends not only on the present combination of inputs, but also on the history of the circuit. Latch A sequential circuit with two inputs called SET and RESET, which make the latch store a logic 0 (reset) or 1 (set) until actively changed. SET 1. The stored HIGH state of a latch circuit. 2. A latch input that makes the latch store a logic 1. RESET 1. The stored LOW state of a latch circuit. 2. A latch input that makes the latch store a logic 0. All the circuits we have seen up to this point have been combinational circuits. That is, their present outputs depend only on their present inputs. The output state of a combina- tional circuit results only from a combination of input logic states. The other major class of digital circuits isthe sequential circuit. The present outputs of a sequential circuit depend not only on its present inputs, but also on its past input states. The simplest sequential circuit is the SR latch, whose logic symbol is shown in Figure 7.1a. The latch has two inputs, SET (S) and RESET (R), and two complementary outputs, Q and Q ෆ . If the latch is operating normally, the outputs are always in opposite logic states. KEY TERMS FIGURE 7.1 SR Latch (Active HIGH Inputs) The latch operates like a momentary-contact pushbutton with START and STOP func- tions, shown in Figure 7.2. A momentary-contact switch operates only when it is held down. When released, a spring returns the switch to its rest position. Suppose the switch in Figure 7.2 is used to control a motor starter. When you push the START button, the motor begins to run. Releasing the START switch does not turn the motor off; that can be done only by pressing the STOP button. If the motor is running, 7.1 • Latches 277 pressing the START button again has no effect, except continuing to let the motor run. If the motor is not running, pressing the STOP switch has no effect, since the motor is already stopped. There is a conflict if we press both switches simultaneously. In such a case we are trying to start and stop the motor at the same time. We will come back to this point later. The latch SET input is like the START button in Figure 7.2. The RESET input is like the STOP button. By definition: A latch is set when Q ϭ 1 and Q ෆ ϭ 0. A latch is reset when Q ϭ 0 and Q ෆ ϭ 1. The latch in Figure 7.1 has active-HIGH SET and RESET inputs. To set the latch, make R ϭ 0 and make S ϭ 1. This makes Q ϭ 1 until the latch is actively reset, as shown in the timing diagram in Figure 7.1b. To activate the reset function, make S ϭ 0 and make R ϭ 1. The latch is now reset (Q ϭ 0) until the set function is next activated. Combinational circuits produce an output by combining inputs. In sequential circuits, it is more accurate to think in terms of activating functions. In the latch described, S and R are not combined by a Boolean function to produce a particular result at the output. Rather, the set function is activated by making S ϭ 1, and the reset function is activated by mak- ing R ϭ 1, much as we would activate the START or STOP function of a motor starter by pressing the appropriate pushbutton. The timing diagram in Figure 7.1b shows that the inputs need not remain active after the set or reset functions have been selected. In fact, the S or R input must be inactive be- fore the opposite function can be applied, in order to avoid conflict between the two func- tions. ❘❙❚ EXAMPLE 7.1 Latches can have active-HIGH or active-LOW inputs, but in each case Q ϭ 1 after the set function is applied and Q ϭ 0 after reset. For each latch shown in Figure 7.3, complete the timing diagram shown. Q is initially LOW in both cases. (The state of Q before the first ac- tive SET or RESET is unknown unless specified, since the present state depends on previ- ous history of the circuit.) NOTE FIGURE 7.2 Industrial Pushbutton (e.g., Motor Starter) FIGURE 7.3 Example 7.1 SR Latch 278 CHAPTER 7 • Introduction to Sequential Logic SOLUTION The Q and Q ෆ waveforms are shown in Figure 7.3. Note that the outputs re- spond only to the first set or reset command in a sequence of several pulses. ❘❙❚ EXAMPLE 7.2 Figure 7.4 shows a latching HOLD circuit for an electronic telephone. When HIGH, the HOLD output allows you to replace the handset without disconnecting a call in progress. FIGURE 7.4 Example 7.2 Latching HOLD Button The two-position switch is the telephone’s hook switch (the switch the handset pushes down when you hang up), shown in the off-hook (in-use) position. The normally closed pushbutton is a momentary-contact switch used as a HOLD button. The circuit is such that the HOLD button does not need to be held down to keep the HOLD active. The latch “re- members” that the switch was pressed, until told to “forget” by the reset function. Describe the sequence of events that will place a caller on hold and return the call from hold. Also draw timing diagrams showing the waveforms at the HOLD input, hook switch inputs, S input, and HOLD output for one hold-and-return sequence. (HOLD out- put ϭ 1 means the call is on hold.) SOLUTION To place a call on hold, we must set the latch. We can do so if we press and hold the HOLD switch, then the hook switch. This combines two HIGHs—one from the HOLD switch and one from the on-hook position of the hook switch—into the AND gate, making S ϭ 1 and R ϭ 0. Note the sequence of events: press HOLD, hang up, release HOLD. The S input is HIGH only as long as the HOLD button is pressed. The handset can be kept on-hook and the HOLD button released. The latch stays set, as S ϭ R ϭ 0 (neither SET not RESET active) as long as the handset is on-hook. To restore a call, lift the handset. This places the hook switch into the off-hook posi- tion and now S ϭ 0 and R ϭ 1, which resets the latch and turns off the HOLD condition. Figure 7.5 shows the timing diagram for the sequence described. FIGURE 7.5 Example 7.2 HOLD Timing Diagram ❘❙❚ 7.2 • NAND/NOR Latches 279 ❘❙❚ SECTION 7.1 REVIEW PROBLEM 7.1 A latch with active-HIGH S and R inputs is initially set. R is pulsed HIGH three times, with S ϭ 0. Describe how the latch responds. 7.2 NAND/NOR Latches An SR latch is easy to build with logic gates. Figure 7.6 shows two such circuits, one made from NOR gates and one from NANDs. The NAND gates in the second circuit are drawn in DeMorgan equivalent form. FIGURE 7.6 SR Latch Circuits The two circuits both have the following three features: 1. OR-shaped gates 2. Logic level inversion between the gate input and output 3. Feedback from the output of one gate to an input of the opposite gate During our examination of the NAND and NOR latches, we will discover why these features are important. A significant difference between the NAND and NOR latches is the placement of SET and RESET inputs with respect to the Q and Q ෆ outputs. Once we define which output is Q and which is Q ෆ , the locations of the SET and RESET inputs are automatically defined. In a NOR latch, the gates have active-HIGH inputs and active-LOW outputs. When the input to the Q gate is HIGH, Q ϭ 0, since either input HIGH makes the output LOW. Therefore, this input must be the RESET input. By default, the other is the SET input. In a NAND latch, the gate inputs are active LOW (in DeMorgan equivalent form) and the outputs are active HIGH. A LOW input on the Q gate makes Q ϭ 1. This, therefore, is the SET input, and the other gate input is RESET. Since the NAND and NOR latch circuits have two binary inputs, there are four possi- ble input states. Table 7.1 summarizes the action of each latch for each input combination. The functions are the same for each circuit, but they are activated by opposite logic levels. Table 7.1 NOR and NAND Latch Functions SRAction (NOR Latch) S ෆ R ෆ Action (NAND Latch) 0 0 Neither SET nor RESET 0 0 Both SET and RESET active; output does not active; forbidden condi- change from previous tion state 01RESET input active 0 1 SET input active 10SET input active 1 0 RESET input active 1 1 Both SET and RESET 1 1 Neither SET nor RESET active; forbidden condi- active; output does not tion change from previous state 280 CHAPTER 7 • Introduction to Sequential Logic We will examine the NAND latch circuit for each of the input conditions in Table 7.1. The analysis of a NOR latch is similar and will be left as an exercise. NAND Latch Operation Figure 7.7 shows a NAND latch in its two possible stable states. In each case the inputs S ෆ and R ෆ are both HIGH (inactive). S 1 ϭ Q 1 1 ϭ 0 R 1 ϭ Q 0 ϭ Q 1 ϭ a. Set S 1 ϭ Q 0 0 ϭ 1 R 1 ϭ b. Reset FIGURE 7.7 NAND Latch Stable States Figure 7.7a shows the latch in its SET condition (Q ϭ 1). The feedback connections from each gate output to the input of the opposite gate keep the latch in a stable condition. The upper gate has a LOW on the “inner” input. Since, for a NAND gate, either input LOW makes the output HIGH, this makes Q ϭ 1. This HIGH value is fed to the gate on the other side of the latch. The lower gate has both inputs HIGH, thus keeping its output LOW. The LOW at Q ෆ feeds back to the upper gate, forming a closed loop of consistent logic levels. There is no tendency for the outputs to change under these conditions. Figure 7.7b shows a similar state for the latch in a RESET condition (Q ϭ 0). As with the SET state, the stability of the latch depends on the feedback connections. The logic val- ues of the latch gate inputs are the same as before, except that the LOW input is on the lower gate, not the upper gate as in the SET condition. Figure 7.8 shows a NAND latch as a Graphic Design File created with MAXϩPLUS II. The inputs are labeled nS and nR and one output as nQ as we cannot enter input names with bars over them. (BOR2 ϭ “Bubbled OR, 2-inputs”.) nS INPUT OUTPUT OUTPUT INPUT BOR2 BOR2 nR Q nQ FIGURE 7.8 Graphic Design File representation of a NAND Latch. The documentation for MAXϩPLUS II recommends that you do not create your own latch circuits or similar cross-coupled structures. Rather, you should use primi- tives such as LATCH, or components such as lpm_latch, which can be used in gdf or vhd files. We will use the design in Figure 7.8 only to illustrate the function of a NAND latch and to generate some timing data with the MAXϩPLUS II simulator. In order to make MAXϩPLUS II synthesize this circuit as we have drawn it in Figure 7.8, we must select Global Project Logic Synthesis from the Assign Menu (Figure 7.9). NOTE 7.2 • NAND/NOR Latches 281 In the resulting dialog box (Figure 7.10), we must choose the WYSIWYG (What You See Is What You Get) synthesis style and check the box that says Multi-Level Synthesis for MAX5000/7000 Devices. FIGURE 7.9 Assign Menu FIGURE 7.10 Choosing WYSIWYG Synthesis Style When we compile the graphic file, MAXϩPLUS II synthesizes the following equa- tions, which we can read in the project report file: ** EQUATIONS ** nR : INPUT; nS : INPUT; — — Node name is ‘nQ’ ϭ ‘:3’ — — Equation name is ‘nQ’, type is output nQ ϭ LCELL( _EQ001 $ GND); _EQ001 ϭ !nR # !Q; — — Node name is ‘Q’ ϭ ‘:2’ — — Equation name is ‘Q’, type is output Q ϭ LCELL ( _EQ002 $ GND); _EQ002 ϭ !nS # !nQ; We can rewrite the synthesized latch equations as: Q ϭ n ෆ S ෆ ϩ n ෆ Q ෆ nQ ϭ n ෆ R ෆ ϩ Q ෆ ➥ nd_latch.gdf 282 CHAPTER 7 • Introduction to Sequential Logic When we run the MAXϩPLUS II Timing Analyzer, we get the delay matrix shown in Figure 7.11. The delays are symmetrical for this circuit. The delay from nS to Q (7.5 ns) is through one gate; from nS to nQ (12.5 ns) is through two gates. These values are the same for the path from nR to nQ (7.5 ns; one gate) and from nR to Q (12.5 ns; two gates). We can see these changes on simulation waveforms for the SET and RESET functions. FIGURE 7.11 NAND Latch Delay Matrix (WYSIWYG Synthesis) Figures 7.12 and 7.13 show the transition of a NAND latch from the RESET to the SET condition. In Figure 7.12a, the latch is stable in the RESET condition (Q ϭ 0) at time t Ͻ 0 (i.e., before a SET pulse is applied to the latch). At time t ϭ 0, the S ෆ input goes LOW (Fig- ure 7.12b) and 7.5 ns later, the output Q goes HIGH (Figure 7.12c). This applies a HIGH to the lower gate in the latch and at t ϭ 12.5 ns (Figure 7.12d), the Q ෆ output goes LOW, closing the loop. The latch is now in a new stable configuration and the S ෆ input can go back HIGH, as shown in Figure 7.12e. Q 0 ϭ S 0 ϭ Q 1 1 ϭ 0 R 1 ϭ Q 0 ϭ d. t ϭ 12.5ns S 1 ϭ Q1 ϭ R 1 ϭ e. Stable (t Ͼ 12.5ns) 1 1 S 1 ϭ Q0 0 ϭ 1 R 1 ϭ Q 1 ϭ Q 0 ϭ a. Stable (t Ͻ 0) S 0 ϭ Q1 ϭ R 1 ϭ b. Initiate set (t ϭ 0) Q 1 ϭ S 0 ϭ Q 1 ϭ R 1 ϭ c. t ϭ 7.5ns FIGURE 7.12 RESET-to-SET transition www.electronictech.com 7.2 • NAND/NOR Latches 283 The waveforms in Figure 7.13 also show this transition. The simulation window has a 2.5 ns grid, so three grid spaces are equivalent to 7.5 ns and five grid spaces to 12.5 ns. The waveforms show Q going HIGH 7.5 ns after nS goes LOW, followed by nQ going LOW at 12.5 ns after nS. Figures 7.14 and 7.15 show the same thing for the RESET function. The latch is in a stable SET condition at time t Ͻ 0 (Figure 7.14a). Input R ෆ goes LOW at t ϭ 0 (Figure 7.14b). At time t ϭ 7.5 ns, Q ෆ goes HIGH, which is transferred to the upper gate in the latch circuit Figure 7.14c). Since both inputs of the upper gate are now HIGH, Q goes LOW at time t ϭ 12.5 ns (Figure 7.14d). At this point the latch is stable in the RESET condition and the input R ෆ can return to the HIGH (inactive) state, as shown in Figure 7.14e. Figure 7.15 shows the simulation waveforms for this transition. FIGURE 7.13 NAND Latch SET function simulation S 1 ϭ Q 0 0 ϭ 1 R 0 ϭ Q 1 ϭ Q 1 ϭ d. t ϭ 12.5ns S 1 ϭ Q0 0 ϭ 1 R 1 ϭ e. Stable (t Ͼ 12.5ns) S 1 ϭ Q1 1 1 1 ϭ 0 1 0 R 1 ϭ Q 0 ϭ Q 0 ϭ a. Stable (t Ͻ 0) S 1 ϭ Q1 ϭ R 0 ϭ b. Initiate reset (t ϭ 0) Q 1 ϭ S 1 ϭ Q1 ϭ R 0 ϭ c. t ϭ 7.5ns FIGURE 7.14 SET-to-RESET Transition FIGURE 7.15 NAND latch RESET function simulation 284 CHAPTER 7 • Introduction to Sequential Logic Note that the latch is not stable in its new condition until the new logic levels have propagated through both gates. Figure 7.16 shows the result of a RESET pulse that only lasts for 7.5 ns. This pulse is too short to allow both gates to change states. The outputs both oscillate, since the changing logic levels never “catch up” as they move around the latch. This is due to the fact that both paths (nS-Q-nQ and nR-nQ-Q) are the same length. If one path were slightly longer, the logic level controlled by the longer path would domi- nate and the latch would stabilize in one state or the other. FIGURE 7.16 NAND latch oscillation due to a RESET pulse that is too short Figure 7.17 shows a NAND latch with S ෆ ϭ R ෆ ϭ 0. This implies that both SET and RESET functions are active. Since a NAND gate requires at least one input LOW to make the output HIGH, both outputs respond by going HIGH. This condition is not unstable in and of itself, but instability can result when the inputs change. There are three possible results when the outputs go back to the HIGH state. 1. The SET input goes HIGH before the RESET input. In this case the latch resets, as RESET is the last input active. This is shown in the simulation in Figure 7.18. S 0 ϭ Q 1 1 ϭ 1 R 0 ϭ Q 1 ϭ FIGURE 7.17 NAND Latch Forbidden State FIGURE 7.18 SET goes HIGH before RESET FIGURE 7.19 RESET goes HIGH before SET 2. The RESET input goes HIGH before SET. In this case, the latch sets, as shown in Fig- ure 7.19. [...]... output bus, q_out, does not change until the enable line goes HIGH FIGURE 7. 36 Simulation of a 4-bit D Latch ❘❙❚ SECTION 7. 3 REVIEW PROBLEM 7. 3 Write the VHDL code for a 16-bit latch with common active-HIGH enable, using MAXϩPLUS II latch primitives 7. 4 Edge-Triggered D Flip-Flops KEY TERMS Edge The HIGH-to-LOW (negative edge) or LOW-to-HIGH (positive edge) transition of a pulse waveform CLOCK An enabling... circuits ❘❙❚ ❘❙❚ SECTION 7. 4 REVIEW PROBLEM 7. 4 Which part of a D flip-flop accounts for the difference in operation between a D flipflop and a D latch? How does it work? 7. 5 • Edge-Triggered JK Flip-Flops 303 7. 5 Edge-Triggered JK Flip-Flops KEY TERM Toggle Alternate between opposite binary states with each applied clock pulse FIGURE 7. 45 Edge-Triggered JK Flip-Flops A versatile and widely used sequential... Inhibited Positive Edge-Triggered FIGURE 7. 46 JK Flip-Flop Circuit (Simplified) Negative Edge-Triggered 304 C H A P T E R 7 • Introduction to Sequential Logic FIGURE 7. 47 Toggle Action of a JK Flip-Flop ❘❙❚ EXAMPLE 7. 8 The J, K, and CLK inputs of a negative edge-triggered JK flip-flop are as shown in the timing diagram in Figure 7. 48 Complete the timing diagram by drawing the waveforms for Q and Q Indicate which... sync3.scf K CLK AND2 JKFF PRN PRN Q CLRN J K PRN Q CLRN J K Q CLRN INPUT OUTPUT OUTPUT OUTPUT FIGURE 7. 53 3-bit Synchronous Counter Q2 Q1 Q0 7. 5 • Edge-Triggered JK Flip-Flops 3 07 Figure 7. 53 shows the circuit of a 3-bit synchronous counter Unlike the circuit in Figure 7. 49, the flip-flops in this circuit are clocked from a common source Therefore, flip-flop delays do not add up through the circuit, and all the... a CPLD are LOW immediately after power is applied to the device The MAXϩPLUS II simulator accounts for this condition ❘❙❚ EXAMPLE 7. 7 Two positive edge-triggered D flip-flops are connected as shown in Figure 7. 44a Inputs D0 and CLK are shown in the timing diagram Complete the timing diagram by drawing the waveforms for Q0 and Q1, assuming that both flip-flops are initially reset FIGURE 7. 44 Example 7. 7... enabled The edge detector sends a high-going pulse to the upper steering gate, which transmits a low-going SET pulse to the output latch This action stores a 1 at Q FIGURE 7. 41 Operation of a D Flip-Flop 7. 4 ❘❙❚ EXAMPLE 7. 6 • Edge-Triggered D Flip-Flops 301 Figure 7. 42 shows a MAXϩPLUS II Graphic Design File with a D latch and a D flipflop connected to the same data input and clock Create a MAXϩPLUS II simulation... set function, and clear, an asynchronous reset function These functions are generally active LOW, and are abbreviෆෆෆ ෆෆෆ ated PRE and CLR Figure 7. 55 shows a modification to the JK flip-flop of Figure 7. 46 The ෆRE and ෆLR Pෆෆ Cෆෆ inputs have direct access to the latch gates of the flip-flop and thus are not affected by the 308 C H A P T E R 7 • Introduction to Sequential Logic FIGURE 7. 55 PRE and ෆLR Inputs... latch as a circuit with a level-sensitive enable (e.g., gated D latch) or no enable (e.g., NAND latch) and a flip-flop as a circuit with an edge-triggered clock (e.g., D flip-flop) A NAND or NOR latch is sometimes called an SR flip-flop By our definition this is not correct, since neither of these circuits has a clock input (An SR flip-flop would be like the gated SR latch of Figure 7. 27 with a clock instead of... between the latch (level-sensitive enable) and the flip-flop (edgetriggered clock) LATCH D CLK INPUT INPUT D Q ENA OUTPUT Q_latch DFF D PRN Q OUTPUT Q_flip_flop CLRN FIGURE 7. 42 D Latch and D Flip-Flop SOLUTION The simulation, shown in Figure 7. 43, has a 200 ns grid Several points on the waveform indicate the similarities and differences between the latch and flip-flop operation FIGURE 7. 43 Simulation showing... is the JK flip-flop Figure 7. 45 shows the logic symbols of a positive- and a negative-edge triggered JK flip-flop J acts as a SET input and K acts as a RESET input, with the output changing on the active clock edge in response to J and K When J and K are both HIGH, the flip-flop will toggle between opposite logic states with each applied clock pulse The function tables of the devices in Figure 7. 45 are shown . 275 ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ ❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ CHAPTER 7 Introduction to Sequential Logic OUTLINE 7. 1 Latches 7. 2 NAND/NOR Latches 7. 3 Gated Latches 7. 4 Edge-Triggered D Flip-Flops 7. 5 Edge-Triggered JK Flip-Flops 7. 6 Edge-Triggered. Use MAXϩPLUS II to create simple circuits and simulations with D latches and D, JK, and T flip-flops. • Create simple flip-flop designs using VHDL. T he digital circuits studied to this point have. 7. 3 Example 7. 1 SR Latch 278 CHAPTER 7 • Introduction to Sequential Logic SOLUTION The Q and Q ෆ waveforms are shown in Figure 7. 3. Note that the outputs re- spond only to the first set or reset command