Digital Circuit Design - Lecture 2 pptx

Sequential Design Basics 9/25/089/25/08 9/250/8 – ECE 561 – ECE Lect 561 Lect Copyright ECE 561 -2008 Lecture - Joanne 2Copyright DeGroat, 2008ECE, - Joanne OSU DeGroat, ECE, OSU Lecture topics  Covers 7.1 and 7.2 of text 9/25/08 – ECE 561 9/25/089/25/08 – ECE Lect 561 Lect Copyright ECE 561 -2008 Lecture - Joanne 2Copyright DeGroat, 2008ECE, - Joanne OSU DeGroat, ECE, OSU Digital Circuit Types  Combinational Logic Circuit – one whose outputs depend only on its current inputs   A more descriptive term might be feedforward combinational logic circuits These are circuits in which there is no feedback Sequential Logic Circuit – one whose output depends not only on its current inputs, but also on the past sequence of inputs 9/25/08 – ECE 561 9/25/089/25/08 – ECE Lect 561 Lect Copyright ECE 561 -2008 Lecture - Joanne 2Copyright DeGroat, 2008ECE, - Joanne OSU DeGroat, ECE, OSU State changes   In sequential changes their state changes at times specified by a clock Clock frequency Cf = / T  Where T is the Clock period 9/25/08 – ECE 561 9/25/089/25/08 – ECE Lect 561 Lect Copyright ECE 561 -2008 Lecture - Joanne 2Copyright DeGroat, 2008ECE, - Joanne OSU DeGroat, ECE, OSU Sequential elements are bistable  Bistable – can be in one of two states 9/25/08 – ECE 561 9/25/089/25/08 – ECE Lect 561 Lect Copyright ECE 561 -2008 Lecture - Joanne 2Copyright DeGroat, 2008ECE, - Joanne OSU DeGroat, ECE, OSU S-R Latch  The S-R Latch is the most basic sequential elements Formed from a pair cross connected pair of NOR gates  Basic Timing 9/25/08 – ECE 561 9/25/089/25/08 – ECE Lect 561 Lect Copyright ECE 561 -2008 Lecture - Joanne 2Copyright DeGroat, 2008ECE, - Joanne OSU DeGroat, ECE, OSU The D Latch  The D Latch is the most common element in CMOS design 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU Timing diagram for a D Latch 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU The D F/F   The D Flip-Flop has edge triggered operation Can be positive edge triggered (as here) or negative edge triggered 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU Timing for a D Flip-Flop  Important to note relationships 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 10 D F/F Behavior  Some important timing parameters 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 11 D F/F with Preset and Clear  Can add preset and clear for easier circuit initialization 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 12 Scan Chains  D F/F are the F/F used in scan chains  What are scan chains? 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 13 Scan Chains  Can use scan chains to inputs data or extract data D F/F 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 14 The T Flip Flop  Toggle Flip Flop 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 15 More on Basic Sequential Elements  The S-R F/F  S The Toggle F/F  CLR T D Q SET Q Q*=Q’ CLR  S 0 1 Q Q*=S+R’Q R  SET R CLK 1 T Q Q Not allowed CLK Q Q Q Q Q is next value or next state 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 16 D F/F and J/K F/F  D F/F  D SET Q* = D CLR  J J/K F/F  Q*=JQ’+K’Q 9/25/089/25/08 – ECE 561 Lect K SET CLR Q D CLK Q Q Q Q ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU J 0 1 K CLK 1 Q Q Q 17 A simple up down counter  Start with state diagram 00 01 1 1 11 10 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 18 Then add state table  Will use T F/Fs 00 01 1 1 11 Next Start Pr St x=0 x=1 y1 y2 y1 y2 y1 y2 0 1 1 0 1 1 1 0 x=0 T1 T2 1 1 1 x=1 T1 T2 1 1 1 10 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 19 K Maps for the toggle F/Fs T1 y1 y2 00 x 0 1 T2 y1 01 11 1 y1 y2 10 00 x 0 1 x 1 y2 y1 01 11 10 1 1 1 x y2 T1 = x’y2 + x y2’ = x xor y2 9/25/089/25/08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 2008 - Joanne DeGroat, ECE, OSU 20 ... CMOS design 9 /25 /089 /25 /08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 20 08 - Joanne DeGroat, ECE, OSU Timing diagram for a D Latch 9 /25 /089 /25 /08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 20 08... ECE 561 - Lecture 2Copyright 20 08 - Joanne DeGroat, ECE, OSU Timing for a D Flip-Flop  Important to note relationships 9 /25 /089 /25 /08 – ECE 561 Lect ECE 561 - Lecture 2Copyright 20 08 - Joanne.. .Lecture topics  Covers 7.1 and 7 .2 of text 9 /25 /08 – ECE 561 9 /25 /089 /25 /08 – ECE Lect 561 Lect Copyright ECE 561 -2 008 Lecture - Joanne 2Copyright DeGroat, 20 08ECE, - Joanne OSU