Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 932 24-9-2008 #21 932 Handbook of Algorithms for Physical Design Automation The earliest power/groundnetwork sizing work [5,6] takes special advantage of the tree topology of the power/ground network typically used in early designs. Instead of restricting the voltage drop on every node in the P/G network, only the voltage drop from root to every leaf of the tree structure is constrained, where the root corresponds chip power pad and the leaf corresponds to the power pin of each macro. In this work, constant branch current constraints I i max and I i min are used to further reduce the total number of voltage and current constraints. Chowdhury proposes to solve the general nonlinear optimization problem (Equation 44.34) on a general graph topology in Ref. [50]. In this work, both currents and voltages are treated as variables. Specifically, the entire optimization procedure consists of two optimization stages. Assuming fixed branch currents and given w i = ρl i /R i and R i = V i1 −V i2 I i , the first stage minimizes area, a nonlinear function of each branch voltage Area = f ( v ) = i l i w i = i α i V i1 − V i2 (44.34) where α i = ρI i l 2 i , subject to change of current direction constraints V i1 − V i2 I i ≥ 0 (44.35) the minimum width constraints, V i1 − V i2 I i ≤ ρl i w i,min (44.36) voltage IR drop constraints, and current density constraints. This problem was converted into an unconstrained convex programming problem and was solved using the conjugate gradient method. The second stage assumes that all nodal voltages are fixed, the objective function b ecomes area = i β i I i (44.37) where β i = ρl 2 i V i1 −V i2 . Constraints include changes of current directions, minimum width constraints, and Kirchoff’s current law. This is a linear programming problem. Tan et al. [51] improves the above method by expanding the nonlinear objection function of the first-stage optimization problem using Taylor’s expansion as follows: g ( v ) = f v 0 + ∂f v 0 ∂v v −v 0 = i 2|α i | v 0 i − i |α i | v 0 2 i v i (44.38) Instead of minimizing the nonlinear objective function (Equation 44.34), they minimize Equa- tion 44.38, which is a linear function of v. The solution is thus transformed into a sequence of linear programming problem. Ref. [52] directly treats wire width as the optimization variable and solves the nonlinear optimiza- tion problem (Equation 44.34) using augmented Lagrangianrelaxation.The following unconstrained minimization problem is formulated F(v) = area + ω × i V drop 2 + j I density 2 (44.39) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 933 24-9-2008 #22 Power Grid Design 933 where i is every node connected to the power grid j is every branch in the power grid circuit ω is the penalty parameter Adjoint sensitivity [53] technique is used to evaluate the sensitivity of the objective function with respect to each wire width. The multigrid power grid analysis idea is applied to optimization in Ref. [54]. The method first reduces the original power grid to a coarse grid according to grid density in each region and maintains the total grid area. The sequence of linear program [51] algorithm is then applied to optimize the coarse grid. The optimal solution is then mapped back to a solution to the original grid. 44.4.2 DECOUPLING CAPACITANCE ALLOCATION AND SIZING Optimal decoupling capacitance allocation and placement is critical for suppressing transient power grid noise. A simple and greedy decap estimation for each module k is based on the total charge that each module will draw from the power grid: Q k = τ 0 I k ( t ) dt C k = Q k /V (lim) noise (44.40) where C k is the upper limit of required decap for module k τ is the duration that the switching process lasts I k (t) is the switching current of module k V (lim) noise is the upper limit of voltage drop As pointed out in Ref. [55], the above decap estimation is very conservative by not considering its impact on neighboring modules that draw currents from the same V dd pins. An iterative process is proposed to reduce the pessimism of the above solution. The initial solution is chosen as θ = max 1, V k noise V (lim) noise C k = ( 1 −1/θ ) Q k /V (lim) noise (44.41) Power supply noise is then verified after decap insertion. If some V k noise still go beyond V noise , θ is changed to increase C k without exceeding the upper limit (Equation 44.41). If C k is increased to the limit and V k noise is still above the voltage limit, decap of its neighboring modules will be increased until V k noise goes below V (lim) noise . In the above work, only the worst-case voltage drop across the entire transient voltage waveform is taken into consideration. Refs. [30,56] use the integral of voltage waveform beyond the noise margin as the transient noise metric and formulates the decap sizing problem as a linearly constrained nonlinear optimization problem for row-based standard-cell designs as follows: minimize Z(w j ) j = 1 ···N decap subject to k∈row i w k ≤ (1 − r i )W chip i = 1 ···N row and 0 ≤ w j ≤ w max j = 1 ···N decap The scalar objective Z, defined in Equation 44.10, is a function of all of the decap widths and N decap is the total number of decaps in the chip. The first constraint states that the total decap width in a row cannot exceed the total amount of empty space in that row, and W chip and N row denote, respectively, the Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 934 24-9-2008 #23 934 Handbook of Algorithms for Physical Design Automation width o f the chip and the number of rows in the chip. The second constraint restricts the decap widths within a realistic range. An upper bound w max for a cell in row i is easily seen to be (1−r i )W chip ,which is the largest empty space in row i; while the lower bound of each decap width is zero. Standard quadratic programming solver is applied to solve this optimization problem. Li et al. proposes a partitioning scheme to reduce the problem size. The partition-based strategy is based o n the fact that decap has a local impact on suppressing the transient noise. The partitioning task is achievedby a noise-aware graph-based multilevel minimum cut algorithm. Conjugate gradient solver is then applied for an optimal solution to each partition. 44.4.3 TOPOLOGY OPTIMIZATION Ref. [57] presents an early work on mesh-based P/G network topology optimization for standard cell layouts. The problem was formulated into a nonlinear combinatorial optimization problem as follows: minimize z = f (g x ) subject to g x i ∈ N x voltage drop and electromigration constraints (44.42) and circuit constraints (kirchholff’s voltage law [KVL], kirchholff’s current law [KCL], and Ohm’s law) (44.43) The objective function z is the total wiring resources required by the power buses. The decision variable vector g x is the conductance of every branch. g x can take any discrete value between zero and g x n x , n x =|N x |. The problem was relaxed into a continuous optimization problem by allowing g 0 i ≤ g x i ≤ g X i , iN x . Starting from an initial feasible solution, the solution is improved by moving toward the direction that decreases the objective function, total wiring resources, without causing the violation of any constraint. The improvement step is iterated until no improvement is obtained. The gradient calculation was based on adjoint sensitivity technique [53]. After obtaining an approximate solution, an exact or integer solution is locally searched in a neighborhood of the approximate solution. Note that the nature of the problem formulation provides possibility of topology changes during each iteration as g x may change between zero and nonzero. If g x is not allowed to be zero, this work reduces to be a wire sizing technique. Refs. [12,13,38] propose to design power grid using hybrid mesh/tree topologies. Although tree structures provide the benefits of easier to route and analyze, they can easily result in poor quality in P/G signal delivery especially in recent technologies. On the other hand, dense meshes are excellent in satisfying the quality requirements but are computationally difficult to an alyze. The key idea in this work is that an approach that meets both requirements of quality and fast turnaround time of analysis would be some topology between a pure tree and a full mesh. Both Ref. [12] and Refs. [13,38] illustrate the benefit of such a hybrid power grid topology of a global mesh feeding multiple local trees by proposing a fast and accurate analysis approach and showing its efficiency of both analysis and optimization. As pointed out by Refs. [13,38], the hybrid topology can be extended to other topologies that are intermediate to the two extremes of full trees and full meshes, for example, a global mesh that feeds smaller unconnected local meshes. Ref. [58] proposes another idea of hybrid power grid topology, which is intermediate to fully regular grids and highly irregular grids. Power grids with regularity help signal routing because power wires can be easily accounted for during routing. At global level, a regular power grid also provides well-balanced ground returns for signal lines. On the other hand, a highly irregular grid may adaptively provide excellent power delivery according to current demands at different regions of a chip. Therefore, Ref. [58] proposes a power grid topology with global irregularity and local regularity, which has the advantages for routing that is afforded by fully regular nets, while offering the flexibility in optimization and better resource utilization permitted by irregular grids. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 935 24-9-2008 #24 Power Grid Design 935 The optim ization procedure begins by abstractin g the P/G network with an equivalent circuit model as described in Section 44.2. The current in each tile is assumed to be evenly distributed. The chip is then divided into k rectangular tile and an imaginary skeleton grid is superimposed on the chip area on which the actual supply grid is built, to maintain wire alignments across tile boundaries. Starting with an equal number of wires in all tiles in both horizontal an d vertical directions, an initial sparse actual grid is formed on the skeleton grid. The grid is analyzed using the macromodeling technique in Ref. [39] after the required port approximations, and the most critical node x in tile i with the maximum voltage drop from V dd is determined. The voltage sensitivity of the most critical node x, with respect to increase in wire area in tile i, by addition of l wires, is computed using a finite-difference based gradient calculation method. Next, the number of horizontal or vertical wires in the tile, which produces the maximum voltage sensitivity, is increased by l. The current source to internal nodes of the tile are reassigned, so that the sum of the current sources at all internal nodes is the total current drawn by the P/G buses in that tile. Th e analysis-sensitivity-optimization steps are repeated until the voltage of the most critical node is greater than a specified value. 44.4.4 OPTIMAL PLACEMENT OF POWER SUPPLY PADS AND PINS For a given power supply network, Ref. [59] provides an optimal solution for placement of power pads and pins, subject to DC voltage drop constraints and maximum current constraints on each pad and pin. The problem is modeled as a mixed integer linear program using the macromodeling technique discussed in Section 44.3: minimize number of pads N subject to (1) I i ≤ I th , i ∈ PC (2) V j ≥ V th , j ∈ PC and OBS (3) I i and V j satisfy Equation 44.13 (44.44) where PC represents candidate pad locations OBS means observation nodes on ports of the macromodel I th is the maximum current allowed through pads V th is the worst-case voltage for each node in the power grid Introducing 0–1 integer variables z, with z i = 1 denoting that a pad is placed at pad candidate i. This will help set different voltage and port current constraints for PC nodes depending on whether a pad is connected at the candidate location or not. The constraints for PC ports can be written as V i − V dd ×z i ≥ 0 (44.45) V i ≤ V dd (44.46) V i ≥ V th (44.47) I th ×z i − I i ≥ 0 (44.48) I i ≥ 0 (44.49) The above formulation assumes ideal supply voltage of V dd at pad locations. By further partitioning the macromodel in Equation 44.13 based on PC and OBS ports, Equation 44.13 can be rewritten as I PC I OBS = A 11 A 12 A 21 A 22 V PC V OBS + S PC S OBS (44.50) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 936 24-9-2008 #25 936 Handbook of Algorithms for Physical Design Automation where I PC and I OBS are currents through the PC and OBS ports, respectively S PC and S OBS are constant current sources from these ports to the reference node It should be noted that all elements in I OBS are zero because there is no current flow into the macromodel through the observation nodes. Given T =−A −1 22 × A 21 and B =−A −1 22 × S OBS ,further derivation gives T × V PC ≥ C (44.51) where C = ⎡ ⎢ ⎢ ⎣ V th − B 1 V th − B 2 ··· V th − B n ⎤ ⎥ ⎥ ⎦ (44.52) REFERENCES 1. SIA, ESIA, JEITA, KSIA, and TSIA. The International Technology Roadmap f or Semiconductors. Available at http://www.itrs.net/Common/2005ITRS/Home2005.html, 2005. 2. G. Bai, S. Bobba, and T. N. H ajj. Static timing analysis including power supply noise effect on propagation delay in VLSI circuits. In Proceedings of the Design Automation Conference, pp. 295–300, Las Vegas, NV, June 2001. 3. L. H. Chen, M. Marek-Sadowska, and F. Brewer. Coping with buffer delay change due to power and ground noise. In Proceedings of the Design Automation Conference, pp. 860–865, New Orleans, LA, June 2002. 4. R. Saleh, S. Z. Hussain, S. Rochel, and D. Overhauser. Clock ske w verification in the presence of IR-drop in the power distribution network. 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Alpert/Handbook of Algorithms for Physical Design Automation AU7242_S010 Finals Page 939 24-9-2008 #2 Part X Physical Design for Specialized Technologies Alpert/Handbook of Algorithms for Physical Design Automation AU7242_S010 Finals Page 940 24-9-2008 #3 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C045 Finals Page 941 24-9-2008 #2 45 Field-Programmable Gate Array Architectures Steven J.E. Wilton, Nathalie Chan King Choy, Scott Y.L. Chin, and Kara K.W. Poon CONTENTS 45.1 Introduction. 941 45.2 Programming Technologies 942 45.2.1 SRAM-Based FPGAs 942 45.2.2 Flash-BasedFPGAs 943 45.2.3 Antifuse-Based FPGAs 944 45.3 Logic Block Architectures 944 45.3.1 Lookup-Tables 944 45.3.1.1 Clusters 945 45.3.1.2 Carry Chains 946 45.3.2 Non-LUT-BasedLogic Blocks 947 45.4 Routing Architectures 947 45.4.1 Segmentation 947 45.4.2 Programmable Switches 948 45.4.3 Switch Blocks and Connection Blocks 948 45.4.4 Bus-Based Routing Architectures 949 45.4.5 Pipelined Interconnect Architectures 950 45.5 Memories 950 45.5.1 Embedded Memory 950 45.5.2 Distributed Memory 952 45.6 Embedded Computation Blocks 952 45.6.1 Multipliers and DSP Blocks 952 45.6.2 Embedded Processors 953 45.7 Summary 953 References 954 45.1 INTRODUCTION Field-programmable g ate arrays (FPGAs) have become the implementation medium o f choice for many digital systems. FPGAs are integrated circuits that can be programmed after fabrication to implement virtually any d igital circuit. Th is instant manufacturability reduces time-to-market as well as nonrecurring engineeringcosts. Most FPGAs are also reprogrammable,meaning the digital circuit implemented in the device can change as requirements or standards change or as bugs are found. The flexibility in a FPGA is afforded through flexible logic elements connected to each other and to the I/O pads using flexible routing resources. Because the elements are prefabricated, the physical design tasks associated with mapping a circuit to an FPGA are somewhat different than those used 941 . X Physical Design for Specialized Technologies Alpert /Handbook of Algorithms for Physical Design Automation AU7242_S010 Finals Page 940 24-9-2008 #3 Alpert /Handbook of Algorithms for Physical Design Automation. the Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 934 24-9-2008 #23 934 Handbook of Algorithms for Physical Design Automation width o f the chip and the number of. as I PC I OBS = A 11 A 12 A 21 A 22 V PC V OBS + S PC S OBS (44.50) Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 936 24-9-2008 #25 936 Handbook of Algorithms for Physical Design Automation where I PC and