Handbook of algorithms for physical design automation part 82 potx

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 792 23-9-2008 #3 792 Handbook of Algorithms for Physical Design Automation (e.g., timing, noise, power). These factors have led to strong recent academic and industrial efforts in manufacturability-aware routing . In general, routing consists of two steps: global routing and detailed routing. Global routing plans an approximate path for each net, while detailed routing finalizes the exact design rule checker (DRC)-compatible pin-to-pin connections [8]. Track routing, as an intermediate step between global and detailed routing, can expedite detailed routing by embeddingmajortrunks from each net within a panel (a row/column of global routing cells) in DRC-friendly manner [9]. Manufacturability-aware routing canbeaccomplishedatanystageof routing systemifpropermanufacturingmodel isavailable, and the approaches can be roughly classified into two groups: rule-based and model-based. The rule-based appr oach imposes additional manufacturability-driven design rules on a router to avoid manufacturability-unf riendly patterns. The model-based approach utilizes some models to estimate the manufacturability effects to guide router. There are pros and cons for both the rule-based and the model-based approaches, in terms of runtime, scalability, implementation, and controllability. This chapter surveys recent practices an d researches on manufacturability -aware routing. Before discussing key techniques, the major manufacturability challenges for advanced technologies is discussed in Section 38.2. Then, we compare the pros and cons of the rule-based and model-based approaches in Section 38.3. In practice, both approaches are used where the model-based approach can be used for optimization and the required rules must be satisfied, in particular, at the detailed routing stage. Section 38.4 then go es into details of various key aspects of manufacturability-aware routing optimizations, including CMP-aware routing, random defect-aware routing, lithography- aware routing, etc. Section 38.5 discusses techniques for dealing with manufacturing rules at the detailed routing stage. We will use a few examples to show how these rules are becoming more complicated (largely owing to lithography-related matters) and the key issues in addressing them. Finally, we conclude in Section 38.6. 38.2 MAJOR MANUFACTURABILITY ISSUES In this section, we give an overview of the major manufacturing issues for 90-nm technology node and below, and analyze their causes and effects: (1) printability issues owing to subwavelength lithography systems [10,11], (2) random defects owing to missing/extra material, (3) topography variations owing to CMP, and (4) other causes such as via failure and antenna effect [12,13]. A fundamental limitation for the subwavelength optical lithography is WYSINWYG, i.e., “what you see (at design) is not what you get (at fab).” The printability issue arises between neighboring wires/vias because of subwavelength effects and process variations. As of now, the 193-nm (wave- length) optical lithography is still the dominant integrated circuit manufacturing p rocess for 90-nm and 65-nm nodes. It is likely to r emain so for 45- and 32-nm technology nodes [14] because of tremendous efforts in the domain of resolution enhancement techniques (RET). However, if the ini- tial design is very litho-unfriendly, even aggressive RET may not be able to solve the printability problem. Thus, the routing stage should strive hard to construct only litho-friendly and printable layouts. It should noted that litho-aware routing is more general than the restrictive design rules (RDR), which, at this time, have mostly been adopted so far for the poly-layer [15–18]. The reduced feature sizes in nanometer VLSI designs make them more vulnerable to random defects, which can be further divided into open or short defect [19,20]. Both defects are at the back- end-of-line (BEOL) [21], and cause electrical opens or shorts between interconnects. Although it is generally believed that the yield loss because ofsystematic sources is greater thanthatbecauseofran- dom defects during the technology andprocess ramp-up stage, the systematicyieldloss canbelargely eliminated when the process becomes mature and systematic variations are extracted/compensated. On the other hand, the random defects that are inherent owing to manufacturing limitations will still be there even for mature fabrication processes. Thus, their relative importance will indeed be larger for mature process with systematic variations designed in Ref. [5]. A more detailed introduction on random defect is provided in Chapter 37. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 793 23-9-2008 #4 Manufacturability-Aware Routing 793 Topography (thickness) variations owing to dishing and erosion after CMP are shown to be sys- tematically determined by wire density distribution [22–26]. Even after CMP, intrachip topography variation can still be on the order of 20–40 percent [22,27]. Such topography variations lead to not only significant performance degradation owing to increased wire resistance and capacitances, but also acute manufacturing issues such as etching and printability owing to defocus [22,25–27]. The detailed description of their impact on design and manufacturability can be found in Chapter 36. The main reason for CMP problems is related to the wire density distribution. Higher wire densities usually lead to copper thickness reduction owing to erosion after CMP [23,24], m aking wire resistances worse. Moreover,the reduced copper thickness after CMP can worsen the scattering effect, further increasing resistance [28]. A via may fail due to various reasonssuch asrandom defects,electromigration, cut misalignment, or thermal stress-induced voiding effects. Redundant vias (or double vias) can be inserted to build fault-tolerance into the interconnect. Redundant vias are known to be highly effective, leading to 10–100x lower failure rate [29]. Another reliability problem that during the fabrication process arises from charges from plasma etching can be accumulated in long floating wires. Such charges may create high current to the thin-oxide gate (Fowler–Nordheim tunneling current), and cause permanent damage to the gate. This is known as the antenna effect [13]. There are three kinds of solutions to prevent the antenna effect: protection diode embedding, diode insertion after placement and routing, and jumper insertion. Although the first two solutions need extra area for the inserted diode, jumper insertion incurs overhead in the routing system as it inserts additional vias [30]. These challenges will be the primary optimization target in manufacturability-aware routing, which our discussion in Sections 38.4 and 38.5 is mainly centered on. 38.3 RULE-BASED APPROACH VERSUS MODEL-BASED APPROACH Techniques for manufacturability-aware routing can be categorized into the rule-b a sed approach and the model-based approach. In this section, we discuss the pros and cons of each class of approaches, in terms of co mplexity and efficiency. The rule-based approach extends the conventional design rules, i.e., a set of rules that must be observed by designers/tools, by introducing a new set of manufacturability-aware rules. These new manufacturability-aware rules can be required/hard rules, or recommended/so ft rules. Because existing routing systems have been based on design rules for decades [31], the rule-based approach is friendly to the conventional design flow, wh ich makes them seemingly easy to implement and apply. However, there can be several problems with this approach: 1. The number o f such manufacturability-aware rules is increasing exponentially with each new technology node. For example, although the number of rules is only a few dozen at the 180-nm node, it reaches to several hundred at the 65-nm node. Moreover, design rules between similar objects may work differently depending on the design context. 2. The complexity of checking such rules becomes more computationally expensive, as the rules are becoming increasingly context-sensitive [10,32,33]. For example, the minimum spacing between wires may depend on the wirelengths and the wires in the neighborhood, as shown in an example in Figure 38.1. Therefore, simply checking rules by itself needs considerable amount of computing resource. 3. The rules are binary in n ature, i.e., a design may either follow the rule or violate the rule, and thus the rule-based approach does not provide smooth trade-off with yield. 4. The rules themselves may be too restrictive and pessimistic, leading to a sacrifice in per- formance. In some cases, it may be infeasible to achieve the performance goals because of overguard banding from the rules. Furthermore, the rules may not be accurate enough to model very complicated manufacturing processes, in particular for the future deeper subwavelength lithography systems. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 794 23-9-2008 #5 794 Handbook of Algorithms for Physical Design Automation Description Rule (mm) 0.12 mm 0.11 mm 0.14 mm Otherwise, minimum spacing Minimum spacing (Sa) between a metal and the end of line of the metal whose edge with (W ) <<=0.2 mm Minimum spacing (Sb) between a metal and the end of line of the metal whose edge with (W ) <=0.2 mm, if there exist objects in the influence region on both sides with parallel overlap (L1 and L2) (a) (b) Sa W W Sb L2L1 FIGURE 38.1 Context-dependent minimum spacing rule for 65-nm technology. Each case, (a) and (b), is described in the table. (From Cong, J., Tutorial presentation at the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2006.) Because of these limitations of the rule-based approach, there have been significant ongoing effortsin developingthe model-based approach in both academiaandindustry, expecting that models will capture manufacturing effects more accurately at affordable computational overhead, when coupled with a small number of simple design rules. For example, the model-based approach may involve lithography system modeling where the light will pass through the mask and react with the chemicals on the surface of the wafer, resulting in printed structures. The challenge with the model-based approach is in abstracting a set of reasonably accurate yet high-fidelity models at various abstraction levels to guide physical layout optimizations. A typical manufacturing system involves nonlinear optical, chemical, electrical, and mechanical processes, which could be extremely complicated to model accurately and mathematically. On the other hand, the models have to be compact and efficient to be embedded in the already time-consuming VLSI routing system. Therefore, the key technical bottleneck for model-based manufacturability- aware routing is to develop simple/compact yet effective/high-fidelity models, and apply them to existing routing flow in a seamless manner. 38.4 MANUFACTURABILITY-AWARE ROUTING OPTIMIZATION In this section, we survey key manufacturability-aware routing optimization issues related to various aspects of manufacturability, including topography variations owing to CMP in Section 38.4.1, yield loss owing to random defects in Section 38.4.2, lithography-related printability in Section 38.4.3, and other issues such as via failure and antenna effect in Section 38.4.4. The o ptimization may be driven through models or some rules of thumb, depending on the nature of the optimization target. 38.4.1 CMP-AWARE ROUTING FOR TOPOGRAPHY VARIATION MINIMIZATION As explained in Section 38.2, topography variation has significant impact on performance as well as printability. Widely adopted solutions to reduce the topography variation include dummy fill synthesis, where dummy features are inserted to increase copper density, and cheesing, which creates patterns of holes for fat/wide wires. The reader is referred to Chapter 36 for more details on CMP Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 795 23-9-2008 #6 Manufacturability-Aware Routing 795 fill synthesis. However, these solutions have inherent limitations, as they are often performed after all the essential polygons are embedded, i.e., on GSDII files to mitigate the problems introduced by the u pstream design stages. A more effective solution will build in intelligent CMP-awareness into the router, in particular at the global routing as CMP-induced variation is a coarse-grained variation. CMP-aware rules include a certain maximum density rule, requiring that a density within any window of a given size should not exceed the maximum density threshold set by foundry. However, the maximum density rule doesnotexplicitly address the topography variation problem, even though it may help to achieve more uniformness by reducing the range of density distribution. In Ref.[6], a predictive copper (Cu) CMP model is proposedto evaluate the topography variation, and usedto guideaCMP-aware globalrouting. Topographyvariation (thicknessvariation) after CMP is determined bytheunderlying metaldensity, contributed byboth wiresanddummies.Asdummyfill in turn depends on wire density, the required dummy density and the Cu thickness can be predicted from a given wire density. In Figure 38.2a, the normalized Cu thickness change as a function of metal density, based on three industrial designs, is shown. For a given global routing cell v i with a metal density m i , the expected Cu thickness of v i , t i can be expressed as follows: t i = α  1 − m 2 i β  (0.2 ≤ m i ≤ 0.8) (38.1) where α and β are technology-dependent constants. Equation 38.1 requires the metal density m i as an input, which is essentially the summation of the wire density w i and the dummy density d i in a global routing cell v i . Figure 38.2b shows the required dummydensity and the predicted Cu thickness with respect to wire density. For a given v i , d i can be looked up with w i using Figure 38.2b, and then m i can be obtained by adding w i and d i . Note that the metal density in real designs would neither fall below 20 percent with the aid of dummy fill nor rise above 80 percent owing to cheesing. Finally, the calculated m i can be fed into Equation 38.1 to predict the Cu thickness t i . This predictive model is verified with a commercial CMP simulator [34] and industry test cases. Intuitively, as copper is softer than dielectric material, aregionwithlesscopperwill experienceless erosion during CMP [25]. Therefore, a region with lower m etal density will have higher copper thickness, and such region in turn needs more dummies to balance wire density distribution for less topography variation. The illustration of the CMP-aware global routing is shown in Figure 38.3 where the predicted Cu thickness guides the global router for less topography variations. A unified metal density driven global router is proposed, which not only helps to reduce CMP-induced thickness variation, but also 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.85 0.9 0.95 1 Normalized copper thickness (t i ) Metal density (m i ) Design1 Design2 Design3 Normalized Cu thickness by metal density 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 0.2 0.4 0.6 0.8 1 Dummy/Metal density (d i /m i ) Wire density (w i ) 0.75 0.8 0.85 0.9 0.95 1 Normalized copper thickness (t i ) Normalized copper thickness (t i ) Metal (Wire+Dummy) density (m i ) Dummy density (d i ) Predicted dummy fill density by wire density(b)(a) FIGURE 38.2 Predictive CMP model. (From Cho, M., Xiang, H., Puri, R., and Pan, D. Z., Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2006, pp. 487–492. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 796 23-9-2008 #7 796 Handbook of Algorithms for Physical Design Automation Global routing Dummy fill density from lookup table Metal density = Wire density + Dummy fill density Cu thickness Cu thickness Wire density FIGURE 38.3 Illustration of CMP-aware global routing based on the predictive CMP model. (From Cho, M., Xiang, H., Puri, R., and Pan, D. Z., Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2006, San Jose, CA, pp. 487–492. With permission.) helps to improve timing. Promising experimental results are shown in Ref. [6], with 7.510 percent improvement for topography variation and timing and small runtime overhead. 38.4.2 CRITICAL-AREA-AWARE ROUTING FOR RANDOM DEFECT MINIMIZATION Yield loss owing to random defects in general can be minimized by optimizing the critical area. As described in Section 37.3.2, the critical area is the region where, if a defect of the given size falls, a circuit will be opened or shorted [20,35]. Because of the importance of yield in semi- conductor industry, there have been considerable amount of efforts to enhance yield by reducing critical area in routing or postrouting. The probability of failure (POF) based on critical area analysis with defect size distribution is a widely used metric for y ield prediction and optimization [19,20]. The defect size distribution F(x) can be modeled as follows [20,36]: F(x) = kx −r for x min ≤ x < ∞ (38.2) where x is the defect size x min is the minimum resolvable lithographic feature size k is a coefficient to ensure  ∞ x min F(x)dx = 1 r ≈ 3 [37] When the end effect is ignored [38], the critical area A o i (x) for open defects on a wire W i and the critical area A s ij (x) for short defects between two parallel wires W i and W j can be approximated as follows [20,36,39]: A o i (x) = ⎧ ⎪ ⎨ ⎪ ⎩ 0for0≤ x < w i L i (x − w i ) for w i ≤ x < 2w i + S min L i (w i + S min ) for 2w i + S min ≤ x < ∞ A s ij (x) = ⎧ ⎪ ⎨ ⎪ ⎩ 0for0≤ x < s ij l ij (x − s ij ) for s ij ≤ x < 2s ij + W min l ij (s ij + W min ) for 2s ij + W min ≤ x < ∞ (38.3) where L i , w i , l ij ,andS ij are the length of wire i, the width of wire i, the overlapped wirelength between wire i and j, and the spacing between wire i and j, r espectively. The values of A o i (x) and A s ij (x) will Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 797 23-9-2008 #8 Manufacturability-Aware Routing 797 saturate at defect sizes of 2 s ij + W min and 2w iw + S min , respectively [36]. Note that more detailed definition of critical area and various approach es to compute it are presented in Section 3 7.3.2. Then, the probability of failure owing to open defects on W i (POF o i ) and owing to short defects between W i and W j (POF s ij ) on a given layer can be obtained as follows [20,36]: POF o i = ∞  x min F(x) A o i (x) A chip dx = kL i 2A chip  w i + S min 2w 2 i + S min w i  POF s ij = ∞  x min F(x) A s ij (x) A chip dx = kl ij 2A chip  s ij + S min 2s 2 ij + W min s ij  (38.4) where A chip is the total chip area. As POF o i and POF s ij indicate the chance of having a random defect, yield can be improved b y minimizing POF o i and POF s ij together, which can be accomplished by maximizing wire width (w i ) and wire spacing (s ij ), respectively. However, minimizing POF o i and POF s ij are two conflicting objectives, as larger w i to decrease POF o i leads to smaller s ij that increases POF s ij with a fixed routing area. Yield optimization in channel routing is proposed in Refs. [40,41]. Weight interval graph is proposed [40] to facilitate the channel routing algorithm in Ref. [42] in a way that net merging in vertical constraint graph will minimize the number of channels as well as critical area. In Ref. [41], a wire segmentis shifted either from top layer to bottom layer (net burying) or vice versa (net floating), like wrong way routing to reduce critical area in a greedy manner. Critical area minimization based on Equation 38.4 during global routing is proposed in Ref. [43], where a linearized critical area is one of the cost factors in multicommodity flow optimization. Redundant link insertion technique to minimize open defect is proposed in Ref. [21]. Additional wires will increase the critical area for short defect. Assumption that the POF owing to open defects of a given size is much higher than the POF owing to short defects of identical size is not always valid, as it depends on design style as well as process technology [20]. Although some level of critical area reduction isachieved,thereare afew drawbacks in these early works that are mostly performed at postrouting or late-stage optimizations: (1) one single defect size is considered, rather than a defect size distribution [40,41]; (2) the trade-off between open and short defects owing to fixed routing area is ignored [21,40,41,44,45]; (3) localized/greedy optimization is performed, which may be suboptimal [21,44,46–48]; and (4) wire adjacency information is not available for accurate critical-area estimation [38,43]. In Ref. [5], the random defect issue is addressed at the track routing stage, which provides reasonable details to model random defect-induced yield loss, while also providing much more flexibility than the detailed-routing or postrouting optimization. The proposed TROY algorithm, based on mathematical programming and graph theory, attempts to find the best trade-off between open and short defects with respect to a defect size distribution through effective wire planning (wire ordering, sizing, and spacing). The mathematical formulation for the yield-driven track routing is as follows: min : α  i POF o i + (1 −α)  i,j>i POF s ij s.t. : |p i − M i |≤d i ∀ i S min ≤ s ij ≤ p i − p j − (w i + w j ) 2 + (1 −o ij )N ∀ i, j S min ≤ s ij ≤ p j − p i − (w i + w j ) 2 + o ij N ∀ i, j o ij ∈{0,1}∀i, j B k + w i 2 ≤ p i ≤ T k − w i 2 ∀ i ∈ P k W min ≤ w i ≤ W max ∀ i Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 798 23-9-2008 #9 798 Handbook of Algorithms for Physical Design Automation However, this formulation is an integer nonlinear programming problem that is prohibitively expen- sive to solve. The key strategy in Ref. [5] is that POF o i and POF s ij in Equatio n 38.4 can be simplified into simpler convex forms as in Equation 38.5and if the wire-ordering o ij (thus, n i as well) is known, the wire sizing and spacing problem for yield optimization can be formulated as the second-order cone programming (SOCP) shown below, which can be solved optimally and efficiently. min : α  i [δ i +  1 − b a  d i ]+(1 −α)  i,j γ ij s.t. : |p i − M i |≤d i ∀ i S min ≤ s ij = p i − p j − w i + w j 2 ∀ o ij = 1, ∀ j ∈ n i l ij W min ≤ s ij γ ij ∀ i, ∀ j ∈ n i L i S min ≤ w i δ i ∀ i B k + w i 2 ≤ p i ≤ T k − w i 2 ∀ i ∈ P k W min ≤ w i ≤ W max ∀ i The wire ordering optimization is performed by finding the minimum Hamiltonian path. The exper- imental results are promising, with 18 percent improvement in terms of random-defects induced yield loss. POF o i ≈ kL i 2A chip  a S min w i − b  1 ≤ w i S min ≤ 40  POF s ij ≈ kl ij 2A chip  a W min s ij − b  1 ≤ s ij W min ≤ 40  (38.5) 38.4.3 LITHOGRAPHY-AWARE ROUTING FOR PRINTABILITY Optical projection systems in modern optical-lithography technology usually use partially coherent illumination . An illustration ofatypical optical-lithographysy stem isshowninFigure 38.4.Because a partially coherent system can be approximately decomposed into a small number of P fully coherent systems [4,49], the aerial image intensity I(x, y) at the point (x, y) can be shown as follows by approximating Hopkins equation [50] through kernel decomposition [51]: I(x, y) = P−1  i=0      j∈W (x,y) (F j  K i )(x, y)     2 (38.6) Illumination L (x, y ) Transmission F (x, y ) Transfer K (x, y ) Intensity I (x, y ) WaferLensPhoto maskCondenser Laser source FIGURE 38.4 Illustration of optical lithography system for VLSI manufacturing. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 799 23-9-2008 #10 Manufacturability-Aware Routing 799 where K i is the transfer function for the ith fully coherent optical subsystem F j is the transmission function (1 over clear regions and 0 over opaque regions) of the jth rectangle in effective window W (x, y), the intensity support region of the control point at location (x, y) ThesizeoftheW(x, y) depends on the wavelength and numerical aperture of the optical system, but in general is about 1–4µm. Based on Equation 38.6, lithography simulations can be performed to obtain aerial images and then p rinted silicon images. The first attempt to address the lithography problem in routing is the optical proximity correc- tion ( OPC)-aware maze routing work in Ref. [4]. Based on aerial image simulation, it stores the expected OPC cost in a lookup table, which has the information on the interference from patterns at different length by distance. Wh ile routing a new p attern, the interferences from all existing pat- terns in its influence window are looked up from the table, and then summed up to evaluate the total optical interf erence from existing patterns. Mean while, the optical in terference (OPC cost) on existing patterns owing to the new pattern is estimated using the maximum interference on these patterns. Figure 38.5 shows an example of optical interference lookup table. Then, a vector-weighted graph method is applied to map the grid routing model to a graph, where the edge cost is a vector consisting of the interferences from existing patterns as well as the interference of a new pattern to existing patterns. With such vector-weighted graph, OPC-aware maze routing can be casted as multiconstrained shortest path problem, which is then solved by Lagrangian relaxation. It should be noted that optical interference is not a direct lithography metric, such as the edge placement error (EPE)widelyusedinOPCalgorithms. Another lithography-aware maze routing algorithm is proposed in Ref. [52], where a table of EAD (electric amplitude of diffraction) is prebuilt, and the OPC error is estimated asthe squar e of the accumulated EAD values from the patterns within process window. Then, it greedily performs maze routing such that a routed path for each net does exceed neither OPC error threshold nor path length Layout A (Ϫ4, 3, 9) A (−4,3,9) B (Ϫ4, Ϫ2, 7) B (-4,-2,7) C (1,−4,3) −5 −5 −4 −3 −2 −1 012345 −4 −3 −2 −1 01234 B C A −5 −4−3 −2−10 1 2 3 4 −5 −4 −3 −2 −1 01234 −5 −4−3 −2−1 0 1 2 3 4 -5 -4 -3 -2 -1 0 1 2 3 4 −5−4 −3−2 −1012345 −5 −4 −3 −2 −1 0 1 2 3 4 5 −5-4−3−2−1012345 −5 −4−3 −2−10 1 2 3 4 5 All lengths Table lookup I A I B I C Total optical interference (I A + I B + I C ) 2 Decomposition C (1, Ϫ4, 3) FIGURE 38.5 There patterns (A, B, and C) are within the effective window of the point (0,0) in the layout, and each effective p attern i s denoted by the left most edge coordinate and i ts length. The layout is decomposed for each effective pattern that is further located in the center of the decomposed windo w. The optical interference is simulated for all lengths of patterns centered at the origin, and the interference information on ev ery point abov e each pattern is kept in the lookup table. Therefore, the interferences from A, B, and C can be looked up from the table according to the length, then added up to compute the total optical interference energy. (From Huang, L. and Wong, D. F., Optimal proximity correction (OPC) friendly maze routing, in Proceedings of the ACM/IEEE Design Automation Conference, pp. 186–191, June 2004. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 800 23-9-2008 #11 800 Handbook of Algorithms for Physical Design Automation R 3 =+ −− R 1 R 2 R 4 R Reference point FIGURE 38.6 Convolution lookup for fast lithography simulation. (From Mitra, J., Yu, P., and Pan, D.Z., RADAR: RET-aware detailed routing using fast lithography simulations, in Proceedings of the ACM/IEEE Design Automation, pp. 369–372, June 2005. With permission.) constraint. Again, it should be noted that the EAD square metric is not a direct/verified lithography measurement. The RADAR work [7] is the first attempt to directly link a lithography simulator (using the direct EPE metric) to detailed routing. Based on fast lithography simulation techniques that are more suitable for full-chip simulations, it generates the so-called lithography hotspot maps to guide the postrouting optimization, namely wire spreading and rip-up/rerouting. As an example to measure the lithography and RET effort, the EPE metric is used. To compute EPE efficiently, Ref. [7] utilized effectivekerneldecompositionmethodandfast table-lookuptechniques.In the kernel decomposition based simulation, a core computational step is the convolution term. Because of the linearity of convolution in Equation 38.6, the convolution for any arbitrary rectangle inside the effective window can be decomposed into four upper-right rectangles that can reduce the table size significantly [7], as shown in Figure 38.6. Therefore,the linear combination of the convolutions of R1, R2, R3, andR4 can be used to compute the aerial image of R. After the EPE map is obtained from fast lithography simulations, wire spreading and rip-up/rerouting can be applied to reduce the EPE hotspots and to improve printability. The fast lithography simulator is called during the routing modification if needed to make sure no new lithography hotspots occur. Figure 38.7 shows an example of RADAR for EPE hotspot reduction. The result implies that both wire spreading and rip-up/rerouting are effective in reducing EPE hotspots, but rip-up/rerouting can be more effective than wire spreading with less wirelen gth overhead. Similar rip-up/rerouting approach is proposed later on in Ref. [53]. But different from Ref. [7], effective pattern searching is adopted, i.e., a set of known undesirable patterns are stored/matched to identify lithography hotspots. Then, the identified undesirable routing patterns are either removed or modified by performing rip-up/rerouting. Recently, a multilevel routing approach to minimize the number of OPC features is studied in Ref. [54]. A simple OPC cost that becomes higher for EPE hotspots of the initial routing after design closure is shown. Wire spreading results in12 percent EPE reduction with 10 percent WL increase. Rip-up/rerouting results in 40 percent EPE reduction 5 percent WL increase. (a) (b) (c) FIGURE 38.7 RADAR example. (From Mitra, J., Yu, P., and Pan, D. Z., Proceedings of the ACM/IEEE Design Automation Conference, Anaheim, CA, 2005, pp. 369–372. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 801 23-9-2008 #12 Manufacturability-Aware Routing 801 longer and wider wires is proposed, and applied as a factor in maze routing. It should be noted that the lithography-aware r outing is still in its infancy, and there are many research issues to achieve a holistic understanding for it. 38.4.4 REDUNDANT-VIA- AND ANTENNA-EFFECT-AWARE ROUTINGS The first redundant-via-aware routing is presented in Ref. [12]. The problem is formulated as multi- objective maze routing by assigning redundant-via cost to the routing graph, and solved by applying Lagrangian relaxation technique. In Ref. [29], the redundant via is reflected as a factor in the maze routing cost. Each original via has different number of possible redundant-via locations, namely degree of freedom (DOF). Wherever a wire occupies a possible redundant-via location during maze routing, it is inversely penalized by DOF of its corresponding original via. In postlayout optimization,redundant-via insertion is one of the key steps for yield improvement. In Ref. [55], the redundant-via insertion problem is formulated as a maximum independent set (MIS) problem by constructing a conflict graph. Figure 38.8 shows an illustration of the approach in Ref. [55], where each original via from 1 to 5 needs one redundant via. For such original vias, there can be up to four redundant-via candidates as for via 2 in Figure 38.8a (U2, R2, D2, L2). Each redundant-via candidate will be a vertex in the conflict graph as in Figure 38.8b, unless it has electrical/rule violations with other redundant vias (no U6 owing to electrical violation). An edge between vertices (redundant vias) will be created, if either both belong to the same original via o r two redundant vias have conflict as in Figure 38.8b. Then, finding MIS from the conflict graph in Figure 38.8b is equivalent to maximum redundant-via insertion. Because solving MIS is an NP-hard problem, a heuristic approach is adopted in Ref. [55]. Different redundant-via insertion solutions, based on geotopography information, are proposed in Ref. [56], where a redundant via is tried f or each original via in a greedy manner. However, as an excessive number o f vias can even worsen yield, redundant-via insertion under via-density constraint is required, which is addressed in Ref. [57] based on integer linear programming. While via failure can occur during either fabricating or operating a chip, antenna effect occurs during manufacturing process. The first work in antenna avoidance is presented in Ref. [58] and fur- ther improved later [59] where rip-up/rerouting strategy is used. Another work on antenna avoidance during full chip-level routing is discussed in Ref. [60]. While these works try to address antenna effect during routing, there are another set of works to fix antenna issue during postlayout optimiza- tion as in redundant-via insertion. In Ref. [61], antenna avoidance is achieved by a layer assignment technique based on tree partitioning. Regarding diode and jumper insertion, the research in Ref. [62] L2 U2 R2 D2 2 3 46 5 1 Conflict Violation (a) Layout for redundant-via insertion L2 U2 U 3 R2 D2U1 R1 D1 L4 R4 D4 L6 D 6 L5 U5 R5 D5 L3 R3 (b) Corresponding conflict graph FIGURE 38.8 Redundant-via insertion problem in postlayout optimization can be formulated as MIS problem by constructing conflict graph. . W max ∀ i Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 798 23-9-2008 #9 798 Handbook of Algorithms for Physical Design Automation However, this formulation. lithography systems. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 794 23-9-2008 #5 794 Handbook of Algorithms for Physical Design Automation Description Rule. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C038 Finals Page 792 23-9-2008 #3 792 Handbook of Algorithms for Physical Design Automation (e.g., timing,