Handbook of algorithms for physical design automation part 13 potx

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 102 23-9-2008 #15 102 Handbook of Algorithms for Physical Design Automation 6.6 GEOMETRIC PROGRAMMING For circuit design applications, we often encounter optimization problems with design variables corresponding to the geometry o f the circuit. Such problems naturally take the form of a geometric progr am (GP) whose definition is described below.Anexample of a g eometric program in the con text of physical design is described in Chapter 29. 6.6.1 BASIC DEFINITIONS A monomial function is defined as f (x) = cx α 1 1 x α 2 2 ···x α n n where c ≥ 0 α j ∈ domain of f (x) is {x | x i ≥ 0} For example, f (x) = 5x 2.3 1 x −0.7 2 x 2.5 3 is a monomial. The nonnegativity of variables {x i } follow from the fact that they correspond to geometric sizing parameters. Notice that a monomial function is nonconvex in general. For instance, f (x 1 , x 2 ) = x 1 x 2 is a nonconvex monomial. A posynomial function is defined as the sum of monomial functions f (x) = r  k=1 c k x α 1k 1 x α 2k 2 ···x α nk n where c k ≥ 0 α ik ∈ and again the domain of f (x) is {x | x i ≥ 0} An example of posynomial is given by f (x 1 , x 2 , x 3 ) = x 2 1 x −1 2 x 0.5 3 + 2x 2.1 1 x 3 2 . A GP is an optimization problem in the form minimize f 0 (x) subject to f i (x) ≤ 1, i = 1, , m h i (x) = 1, i = 1, , p (6.30) where f 0 , , f m are posynomial functions h 1 , , h p are monomial functions In this original form, GP is not a convex problem in general because the constraint functions {f i }’s are not convex and the equality functions {h j }’s are not affine. However, there exists a nonlinear transformation under which the GP problem (Equation 6.30) can be reformulated as an equivalent convex optimization problem. 6.6.2 CONVEX REFORMULATION OF A GP Consider the following nonlinear transformation: y i = log x i , x i = e y i Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 103 23-9-2008 #16 Optimization Techniques for Circuit Design Applications 103 Under this transformation, a monomail function f (x) = cx α 1 1 x α 2 2 ···x α n n can be written as log f (e y 1 , ,e y n ) = α 1 y 1 +···+α n y n + β which is affine in y,whereβ = log c. Moreover, if f (x) =  r k=1 c k x α 1k 1 x α 2k 2 ···x α nk n is posynomial then log f (e y 1 , ,e y n ) = log r  k=1 exp(α 1k y 1 +···+α nk y n + β k ) which is convex in y,whereβ k = log c k . Consequently, under this transformation, the geometric program (Equation 6.30) in convex form in terms of variables {y i } is minimize logf 0 (e y 1 , , e y n ) subject to log f i (e y 1 , , e y n ) ≤ 0, i = 1, , m log h i (e y 1 , , e y n ) = 0, i = 1, , p Once this convex reformulation is solved, say, using interior point methods, we can recover the original design variables {x i } using the inverse transform x i = e y i .Inthisway,everyGP,even though nonconvex in its original form, can be efficiently solved using interior point methods in polynomial time. More details can be found in Refs. [3,4]. 6.6.3 GATE SIZING AS A GP The conventional gate sizing problem is formulated as minimize area = n  i=1 a i W i L i subject to delay ≤ T spec W min ≤ W i , L min ≤ L i , ∀ i = 1, , n (6.31) where W i and L i are, respectively, the width and the effective channel length of gate i a i is some weight factor Using the Elmore delay model, * which is used for simplicity, each gate i in the circuit can be replaced by an equivalent R on i C i element, where R on i represents the effective on resistance of the pull-up or the pull-down network, and the term C i subsumes the source, drain, and gate capacitances of the transistors in the gate. The expressions for R on i and C i for a gate i are given by R on i = αL i W i , C i = βL i W i + γ (6.32) where α, β,andγ are known constants. From Equation 6.32, we see that both the capacitances and the on resistance of the transistors in a gate are posynomial functions of the vectors W = ( , W i , ) T and L = ( , L i , ) T . Consequently, the term R on i C i , which is the equivalent delay contribution of gate i in the circuit, is also a posynomialfunction of W and L. By b reaking the circuit into a series of RC trees, and applying the Elmore delay computations at each node of the circuit graph, we see that the delay constraint of Equation 6.31 at the primary outputs of the circuit can be replaced by m posynomialdelay constraints of the form  l K l  j W a j j L b j j ≤ t i (6.33) * Other more accurate convex gate delay models may be used instead of the Elmore model. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 104 23-9-2008 #17 104 Handbook of Algorithms for Physical Design Automation where m is the number of nodes in the circuit graph K l is a constant coefficient of the lth monomial term that can be derived from Equation 6.32, t i is the arrival time at gate i a j , b j ∈{−1, 0, 1} are the exponents of the jth components of the W and L vectors By substituting Equ ation 6.33 in Equation 6.31 for all gates in the circuit, the transistor sizing problem is formulated as a GP having a posynomial objective function and posynomial inequal- ity constraints. The resulting GP can be solved using standard convex optimization techniques. In Section 6.7, we show how the robust version of the standard GP formulation (Equation 6.31) can be converted to another GP. 6.7 ROBUST OPTIMIZATION Robust optimization models in mathematical programming have received much attention recently (see, e.g., Refs. [1,2,5]). In this subsection we briefly review some of these models and some extensions. Consider a convex o ptimization for the form minimize f 0 (x) subject to f i (x) ≤ 0, i = 1, 2, , m (6.34) where each f i is convex. In many engineering design applications, the data defining the constraint and the objective functions may be inexact, corrupted by noise or may fluctuate with time around a nominal value. In such cases, the traditional optimization approach simply solves Equation 6.34 by using the nominal value of the data. However, an optimal solution for the nominal formulation (Equation 6.34) may yield poor performance or become infeasible when each f i is perturbed in the actual d esign. In other words, optimal solutions for Equation 6.34 may be misleading or even useless in practice. A m ore appropriate design approach is to seek a high-quality solution that can re main feasible and deliver high-quality performance in all possible realizations of unknown perturbation. This principle was formulated rigorously in Refs. [1,2,5]. Specifically, the data perturbation can be modeled using a parameter vector δ, with δ = 0 representing the nominal unperturbed situation. In other words, we consider a family of perturbed functions parameterized by δ: f i (x; δ), with δ taken from an uncertainty set  containing the origin. Then a robustly feasible solution x is the one that satisfies f i (x; δ) ≤ 0, ∀ δ ∈  or equivalently max δ∈ f i (x; δ) ≤ 0 Thus, a robustly feasible solution x is, in a sense, strongly f easible because it is required to satisfy all slightly perturbed version of the nominal constraint f i (x;0) = f i (x) ≤ 0. The robust optimal solution can now be defined as a robust feasible solution that minimizes the worst-case objective value max δ∈ f 0 (x; δ). This gives rise to the following formulation: minimize max δ∈ f 0 (x; δ) subject to f i (x; δ) ≤ 0, ∀ δ ∈ , i = 1, 2, , m (6.35) Let us assume that the perturbation vector δ enters the objective and the constraint functions f i in such a way that preserves convexity, that is, each f i (x; δ) remains a convex function for each δ ∈ . As a result, the robust counterpart (Equation 6.35) of the original (nominal case) convex problem (Equation 6.34) remains convexbecause its constraints are convex(foreach i and δ) and the objective function max δ∈ f 0 (x; δ) is also convex. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 105 23-9-2008 #18 Optimization Techniques for Circuit Design Applications 105 Much of the research in robust optimization is focused on finding a finite representation of the feasible region of Equation 6.35, which is defined in terms of infinitely many constraints (one for each δ ∈ ). Assume that the uncertainty parameter δ can be partitioned as δ = (δ 0 , δ 1 , δ 2 , δ m ) T and that the uncertainty set has a Cartesian product structure  =  0 × 1 ×···× m , with δ i ∈  i . Moreover, assume that δ enters f i (x; δ) in an affine manner. Under these assumptions, it is possible to characterize the robust feasible set of many well-known classes of optimization problems in a finite way. In particular, consider the robust linear programming model proposed by Ben-Tal and Nemirovskii [2]: minimize max c≤ 0 (c +c) T x subject to (a i + a i ) T x ≥ (b i + b i ), for all (a i , b i )≤ i , i = 1, 2, , m (6.36) where each  i > 0 is a prespecified scalar. In the above formulation, we have δ i = (a i , b i ) and ∆ i ={(a i , b i ) |(a i , b i )≤ i }. It is known that the above robust LP can be reformulated as a SOCP [2]. Refs. [1,2,5] have shown that the robust counterpart of some other well-known convex optim ization problems can also be reformulated in a finite way as a conic optimization problem, often as an SOCP or SDP. Next we consider a robust formulation of a geometric program. 6.7.1 ROBUST CIRCUIT OPTIMIZATION UNDER PROCESS VARIATIONS We use a simple example to explain the procedure to incorporate the process variation effects in the delay constraints set. We use the toy circuit of Figure 6.1, comprising just one driver gate and one load gate, for this illustration. The main idea can be generalized to arbitrarily large circuits. For simplicity we neglect the interconnect delay and the effect of drain and source capacitances of the driver gate. Applying the Elmore delay model to the gates of circuit of Figure 6.1, we can write the delay constraint for the circuit as k 1 l 1 l 2 w 2 w 1 + k 2 l 2 w 2 ≤ t spec (6.37) where k 1 and k 2 are constants. To ensure that the delay constraint of Equation 6.37 is met under the effect of random process variations, we impose the following condition max (l−l 0 ,w−w 0 )∈∆  k 1 l 1 l 2 w 2 w 1 + k 2 l 2 w 2  ≤ t spec (6.38) where w 0 and l 0 represent, respectively, the nominal values of the transistor w and l ∆ signifies the uncertainty region A 12 C B FIGURE 6.1 Simple example circuit. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 106 23-9-2008 #19 106 Handbook of Algorithms for Physical Design Automation To simplify the above robust constraint, we approximate the constraint function by the first-order Taylor series expansion aroundthe nominalvalue(w 0 , l 0 ) and arriveatthe following simplified robust constraint: k 1 l 1 0 l 2 0 w 2 0 w 1 0 + k 2 l 2 0 w 2 0 + max (δl,δw)∈∆  k 1 l 1 0 l 2 0 δw 2 w 1 0 + k 1 l 2 0 w 2 0 δl 1 w 1 0 + k 1 l 1 0 w 2 0 δl 2 w 1 0 + k 2 δl 2 w 2 0 − k 1 l 1 0 l 2 0 w 2 0 δw 1 w 2 1 0 − k 2 l 2 0 δw 2 w 2 2 0  ≤ t spec (6.39) where δw = w −w 0 and δl = l −l 0 denote, respectively, the random variations in w and l. Employing the ellipsoid uncertainty model ∆ ={(δl, δw) : (δl t , δw t )P −1 (δl t , δw t ) t ≤ 1} (6.40) for the random parameter variations, we are led to ⎡ ⎢ ⎢ ⎣ δw 1 δw 2 δl 1 δl 2 ⎤ ⎥ ⎥ ⎦ = ⎡ ⎢ ⎢ ⎣ (P 1/2 u) 1 (P 1/2 u) 2 (P 1/2 u) 3 (P 1/2 u) 4 ⎤ ⎥ ⎥ ⎦ (6.41) where P is the covariance matrix of the random vector (l, w) of the driver and the load gate of Figure 6.1 u is the vector characterizing the variation within the four-dimensional ellipsoid centered at the nominal values of w and l, with u≤1 We introduce two vectors φ 1 and φ 2 to collect the positive and negative coefficients of the variational parameters of Equation 6.39 respectively: φ 1 = ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ 0 k 1 l 1 0 l 2 0 w 1 0 k 1 l 2 0 w 2 0 w 1 0 k 1 l 1 0 w 2 0 w 1 0 + k 2 w 2 0 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ , φ 2 = ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ −k 1 l 1 0 l 2 0 w 2 0 w 2 1 0 −k 2 l 2 0 w 2 2 0 0 0 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ (6.42) From the definitions in Equations 6.41 and 6.42, the linearized robust constraint Equation 6.39 can be rewritten as k 1 l 1 0 l 2 0 w 2 0 w 1 0 + k 2 l 1 0 w 2 0 + max u≤1  P 1/2 φ 1 , u+P 1/2 φ 2 , u  ≤ t spec (6.43) where ·, · represents the standard inner product. By the Cauchy–Schwartz inequality, a sufficient condition for Equation 6.43 is k 1 l 1 0 l 2 0 w 2 0 w 1 0 + k 2 l 1 0 w 2 0 +P 1/2 φ 1 +P 1/2 φ 2 ≤t spec (6.44) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 107 23-9-2008 #20 Optimization Techniques for Circuit Design Applications 107 We then introduce two auxiliary variables r 1 and r 2 as r 1 =P 1/2 φ 1 ,i.e.,r 2 1 = φ T 1 Pφ 1 r 2 =P 1/2 φ 2 ,i.e.,r 2 2 = φ T 2 Pφ 2 (6.45) The inequality of Equation 6.44 can then be replaced by the following equivalent constraints: w 1 l 1 0 l 2 0 w 2 0 w 1 0 + k 2 l 1 0 w 2 0 + r 1 + r 2 ≤ t spec (6.46) φ T 1 Pφ 1 r −2 1 ≤ 1 (6.47) φ T 2 Pφ 2 r −2 2 ≤ 1 (6.48) The inequality of Equation 6.46 is clearly a posynomial in terms of l, w, and the auxiliary variables r 1 and r 2 . By construction, all the elements of φ 1 are posynomials, and all the nonzero elements of φ 2 are negative of posynomials. The covariance matrix P has all nonnegative elements, because a negative correlation between random variables representing the W and L variations would not have any physical meaning. Thus, the quadratic terms φ T 1 Pφ 1 =  i,j P ij φ 1 i φ 1 j and φ T 2 Pφ 2 =  i,j P ij φ 2 i φ 2 j are a summation of monomials with positive coefficients. Consequently, the constraints of Equations 6.47 and 6.48 are also posynomials. Note that the inequality in Equations 6.47 and 6.48 will be forced to equality at optimality, because the aux iliary variables r 1 and r 2 (which represent (a) (b) Violations in NR design Percent slack Percent violations 10 20 30 40 50 0 10 20 30 40 50 60 70 80 90 Area overhead in R design Percent slack Percent area overhead 10 20 30 40 50 0 5 10 15 20 25 30 35 FIGURE 6.2 Nonrobust and robust designs fo r C499 circuit for different values of T spec . (a) T iming violations for nonrobust designs. (b) Area overhead for robust designs. (From S ingh, J., et al., Robust gate sizing by geometric programming, Proceedings of 2005 IEEE Design and Automation Conference, Anaheim, California, 2005.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 108 23-9-2008 #21 108 Handbook of Algorithms for Physical Design Automation the maximum variation in th e uncertainty ellipsoid) are to be minimized. Hence, by following the procedure outlined above, we have converted the robust posynomial constraint of Equation 6.38 to a set of posynomial constraints of Equations 6.46 through 6.48. For a general circuit, the procedure described for the example circuit of Figure 6.1 can be repeated for each constraint. Thus, by adding at most two auxiliary variables for each constraint j, we can explicitly account for the robustness against the process uncertainties while still maintaining the desirable posynomial structure of the original constraints (Equation 6.37). By this procedure, we can convert a conventionalGP formulation of the gate sizing problem to a robust gate sizing problem, which is also a GP itself. The latter can be efficiently solved using the standard convex optimization techniques (e.g., Ref. [7]). We have applied the robust gate sizing technique to a ISCAS 85 benchmark circuit (C499). The cell library selected consists of inverters and two and three input NAND and NOR gates. We use a TSMC 180 nm technology parameter [10] to estimate the constants for the on resistance and the source, drain, and gate capacitances. We assume capacitive loading for the gates. The objective function chosen for the optimization is to minimize Area =  i m i w i l i ,wherem is the number of transistors in gate i. We have implemented the proposed robust gate sizing procedure in a C program, and used an optimization software [7] to solve the final GP. The final result is illustrated in Figure 6.2. ACKNOWLEDGMENT The text in Section 6.7 is based on a joint work [ 6] with Dr. Jaskirat Singh and Professor Sachin Sapatnekar. The author hereby gratefully acknowledges their contribution to this work. REFERENCES 1. Ben-Tal, A ., El Ghaoui, L., and Nemirovskii, A ., Rob ust semidefinite programming, in Handbook of Semidefinite Programming, edited by Wolkowicz, H ., Saigal, R., and Vandenberghe, L., Kluwer Academic Publishers, March 2000. 2. Ben-Tal, A. and Nemirovskii, A., Robust conv ex optimization, Mathematics of Operations Research, 23, 769–805, 1998. 3. Boyd, S. and Vandenberghe, L., Convex Optimization, Cambridge University Press, Cambridge, United Kingdom, 2003. 4. Chiang, M., Geometric programming for communication systems, Foundations and Trends in Communi- cations and Information Theory, 2005. 5. El G haoui, L., Oustry, F., and Lebret, H., Robust solutions to uncertain semidefinite programs, SIAM Journal on Optimization, 9(1), 1998. 6. Singh, J., Nookala, V., Luo, Z Q., and Sapatnekar, S., Robust gate sizing by geometric programming, Proceedings of 2005 IEEE Designa and Automation Conference, June 13–17, 2005, Anaheim, C alifornia. 7. Mosek Software, Available at http://www.mosek.com. 8. Nesterov, Y. and Nemirovskii, A., I nterior Point Polynomial Methods in Convex Programming, SIAM Studies in Applied Mathematics 13, Philadelphia, PA, 1994. 9. Sturm, J.F., Using SeDuMi 1.02, A Matlab toolbox for optimization over symmetric cones, Opti- mization Methods and Software, 11–12, 625–653, 1999. See http://fewcal.kub.nl/sturm/software/ sedumi.html for updates. 10. TSMC: 180 nm Test Data, Available at h ttp://www.mosis.org/Technical/Testdata/tsmc-018-prm.html. 11. Wolkowicz, H., Saigal, R., and Vandenberghe, L., Handbook of Semidefinite Programming: Theory , Algorithms and Applications, Kluwer Academic Press, pp. 163–188, 1999. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C007 Finals Page 109 24-9-2008 #2 7 Partitioning and Clustering Dorothy Kucar CONTENTS 7.1 Preliminaries 110 7.1.1 Net Models 111 7.1.2 Partition ing and Clustering Metrics 112 7.2 Move-Based Partitioning Methods 114 7.2.1 Kernighan–Lin Heuristic 114 7.2.2 Fiduccia–Mattheyses Heuristic 115 7.2.3 Improvements on the Fiduccia–Mattheyses Heuristic 116 7.2.4 Simulated Annealing 117 7.3 Mathematical Partitioning Formulatio ns 118 7.3.1 Quadratic Programming Formulation 119 7.3.1.1 Lower Bounds on the Cutset Size 120 7.3.1.2 Partitioning Solutions from Multiple Eigenvectors 122 7.3.2 Linear Programming Formulations 122 7.3.3 Integer Programming Formulations 123 7.3.4 Network Flow 124 7.3.5 DynamicProgramming 126 7.4 Clustering 126 7.4.1 Hierarchical Clustering 127 7.4.2 AgglomerativeClustering 127 7.4.2.1 Clustering Based on Vertex Ordering 127 7.4.2.2 Clustering Based on Connectivity 128 7.4.2.3 Clustering Based on Cell Area 130 7.5 Multilevel Partitioning 130 7.5.1 Multilevel Eigenvector Partitioning 130 7.5.2 Multilevel Move-Based Partitioning 131 7.5.3 New Innovations in Multilevel Partitioning 132 7.6 Conclusion 132 Acknowledgments 132 References 132 Modern standard cell placement techniques must handle huge and ever-increasing design sizes. It is computationally infeasible to place flattened representations of designs of this scale. A key step in cell placement is obtaining a smaller representation of the design that capturesthe global connectivity of the original design. This is what is known as partitioning and clustering. Partitioning is typically used to divide a netlist into two or four blo cks, then recursively applied to the subregions such that the wiring cost between blocks is minimized. Clustering, on the o ther hand, is inherently a bottom-up approach, where cells are initially assigned to th eir own block, then they are gradually merged into 109 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C007 Finals Page 110 24-9-2008 #3 110 Handbook of Algorithms for Physical Design Automation larger and larger b locks. The purpose of clustering is to reduce the problem size to more manageable proportionsand to recover structural information implicit in the original netlist. Modern placers use a combination of clustering and partitioning to reduce runtimes and preserve str ucture that was present in the orig inal netlist. The very large scale integrated (VLSI) design automation community has adde d several twists to the original graph-theoretic formulation, including fixing vertices to specific blocks, assigning weights to vertices, and introducing timing constraints into the formulation. This survey consists of five sections. Section7.1 introduces the basic concepts and notations relevant to partitioning and clustering. Section 7.2 describes move-based partitioning techniques. Section 7.3 describes mathematical partitioning formulations. Section 7.4 describes clustering techniques, which are employed in multilevel partitioners, described in Section 7.5. 7.1 PRELIMINARIES In this chapter, a circuit is a collection of elementary switching elements called standard cells an d possibly larger macroblocks, connected to one another by wires at the same electrical potential called signal nets enclosed by some sort of boundary. The points at which signal nets come into contact with cells are called pins. If a pin connects cells to areas outside the circuit boundary, it is referred to as a terminal (Figu re 7.1). Standar d cell connectivity information is provided in the form of a netlist, which contains net names followed by the names of cells they are connected to. The combinatorial nature of VLSI physical design problems lends itself nicely to formulations involving graphs or matrices. Most o ften, a circuit is represented as a hypergraph where cells are represented as weighted vertices. The weight is typically proportional to the number of pins or the area of the cell. A hypergraph is the m ost natural representation of a circuit because, in a circuit, more than two vertices may be connected by the same signal net. Circuit hypergraphs have certain desirable properties as far as algorithm d evelopment is concerned. They are nearly planar because chips are typically printed on seven to ten metal layers. The nets of the circuit hypergraph are also of reasonably bounded degree—algorithms that deal with nets of high degree like power, ground, or clock nets are not discussed here. In this chapter, a hypergraph comprises |V| vertices, |E| nets, |P| pins, and k blocks, the set o f vertices in the ith block is denoted by C i , and a net consists of |e| vertices. Although a hypergraph is the natural representation of a circuit, it is very difficult to work with. Often, nets are modeled as cliques or stars as in Figure 7.2b. Definition 1 A clique is a subgraph of graph G(V, E) in which every vertex is connected to every other vertex. a b h d i g f e c 1 2 3 4 5 6 7 j Terminal Net Cell Pin FIGURE 7.1 Schematic diagram of a circuit illustrating terminals, cells, and nets. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C007 Finals Page 111 24-9-2008 #4 Partitioning and Clustering 111 (a) Hypergraph (b) Nets modeled as cliques (c) Nets modeled as stars b a c d e g f i j h 2 1 3 4 6 7 2 5 2 5 1 3 4 6 7 1/3 3/2 1/2 1 1/2 1/2 1 1/2 1/3 4/3 1/3 1/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1 1 6 3 4 1 7 5 2 a b c d e f g h i j FIGURE 7.2 Net representations. It follows that a net connected to |e| vertices will be represented b y  |e| 2  edges. Another way of representing nets is a star graph model. Definition 2 A star g raph is a subgraph of graph G(V, E) in which every vertex except for one is a leaf vertex. The nonleaf-vertex connects all leaf vertices as in Figure 7.2c. In the star graph model, each vertex induces one edge, thus a net consisting of |e| vertices will be represented by |e|−1 edges. Using this representation, the problem of edge weights is alleviated, but the root vertex must be chosen sensibly. Some placers use an alternate star model wh e re an auxiliary root vertex connecting all of the net’s original vertices is inserted (described in Chapter 17). 7.1.1 NET MODELS Many of the techniques d escribed in this work require that nets be represented in terms of edges. If a net on |e| vertices is represented as a complete graph on |e| vertices and if |e| is large, the |e| vertices will likely be placed in the same block after bipartitioning. The result is that nets with small numbers of vertices may be cut because of the predominance of large nets [SK72]. The solution to this problem is to weight the graph edges of the net so that regardless of how vertices in the g raph are partitioned, the sum of the weights of the edges cut should be as close to 1 as possible. Generally, it will not be possible for this sum to be exactly 1 as the theorem below states. Theorem 1 There is no consistent edge weighting scheme such that when some edges are removed (to split the hypergraph into several parts), their weight is exactly 1 for |e| vertices where |e|≥4 [IWW93]. . Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 102 23-9-2008 #15 102 Handbook of Algorithms for Physical Design Automation 6.6 GEOMETRIC PROGRAMMING For circuit. model. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C006 Finals Page 104 23-9-2008 #17 104 Handbook of Algorithms for Physical Design Automation where m is the number of nodes. gradually merged into 109 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C007 Finals Page 110 24-9-2008 #3 110 Handbook of Algorithms for Physical Design Automation larger and larger