Handbook of algorithms for physical design automation part 95 pot

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 922 24-9-2008 #11 922 Handbook of Algorithms for Physical Design Automation 44.3 POWER GRID NOISE ANALYSIS 44.3.1 N OISE METRICS For static (DC) analysis, the maximum voltage drop among all power grid nodes is a general metric for the entire chip. In dynamic (transient) analysis, maximum voltage drop of a node is defined as the largest voltage drop value along the period of time for simulation. The maximumvoltage drop among all nodes in the power grid circuit can indicate performance of the power grid and help identify hot spots on a chip. This measurement is widely used in most power grid noise estimation tools. However, such a measurement is very sensitive to the accuracy of circuit analysis and does not take the timings of the voltage violations into account [29]. An efficient metric for the performance of each node in a circuit was first introduced in Ref. [29], which is the integral of voltage waveform beyond the noise margin: z j ( p ) = T  0 max  NM H − v j ( t, p ) ,0  dt = t e  t s  NM H − v j ( t, p )  dt (44.10) where p represents the tunable circuit parameter s. Su et al. in Ref. [30] initially applied this metric in transient power grid noise analysis and optimization. The transient noise in a node in the supply network is represented by the shaded area (voltage integral) in Figure 44.5. 44.3.2 FAST ANALYSIS TECHNIQUES Because of the large scale (millions of nodes) of the power distribution network, even after separating the nonlinear devices from the linear grids and modeling them using independentcurrentsources, the analysis of such a huge linear network in reasonable amount of time and memory is still a challenge. The behavior of the power distribution circuit can be described by a first-order differential equation formula using modified nodal analysis (MNA) [31]: Gx ( t ) + C˙x ( t ) = u(t) (44.11) where x is a vector of node voltages and source and inductor currents G is the conductance matrix C includes both the decoupling capacitance and package inductance terms u(t) includes the loads and voltage sources 0 t t e T t s NM H V dd 90 percent V dd V j (t, p) FIGURE 44.5 Illustration of the voltage drop at a given node in the V dd po wer grid. The area of the shaded region corresponds to the integral z at that node. (From H. Su, S. S. Sapatnekar and S. R. Nassif, Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layout Designs, IEEE TCAD, 22, 428, 2003. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 923 24-9-2008 #12 Power Grid Design 923 By applying the backward Euler integration formula [31] to Equation 44.11, we have ( G + C/h ) x ( t + h ) = u ( t + h ) + C/hx ( t ) (44.12) where h is the time step for the transient analysis. Equation 44.12 can be shown to be formulated to consist only of node voltages and the matrix is symmetric positive definite. Typically this left- hand-side (LHS) matrix is very large and sparse. Efficient linear system solution techniques such as Cholesky factorization (direct method) and conjugate gradient (iterative method) are both good candidates. Various fast analysis techniques [12,13, 32–39], etc., have been published in the literature. Ref. [39] proposed a hierarchical macromodelingapproach.Even thoughthis approach is suitable for both direct or iterative methods, direct solver is used in their work. Nassif et al. proposed a multigrid- based technique [33,34], which intended to make u se of the beauties of both direct and iterative methods, i.e., it can avoid the memory limitation of direct solvers during coarse grid correction and can significantly bring down the number of iterations for the iterative solver during the fine grid relaxation or the smoothing step. While the method in Refs. [33,34] is based on geometric multigrid, the method proposed in Ref. [37] is based on the algebraic multigrid technique. Another category of analysis methods [12,13,32,38] is based on model-order reduction techniques. A random walk based [35,36] power grid analysis algorithm is presented recently and has demonstrated its success in solving large-scale power grid circuits. In the following four subsections, we discuss the above four approaches in detail. 44.3.2.1 Hierarchical Partitioning Method In Equation 44.12,if h is kept constant, only a single initial factorization (direct method) of the matrix G +C/h is required and for each successive time steps only a forward/backward solution is required. This method is very efficient fo r transient analysis; however, the initial Cholesky factorization is very expensive and can lead to a peak memory hit if the entire network is flatly solved. This motivates the hierarchical macromodeling technique in Ref. [39] . This approach first partitions the power grid into local and global grids: th is may be achieved either by exploiting the designer-specified hierarchy or by automated partitioning. Next, macromodels for the local grids are g e nerated, abstracting the large number of internal nodes into a port-based representation. These macromodels may be dense matrices that can be sparsified with minimal loss of accuracy: the intuition here is that if two ports are far from each other, their port-to-port resistance will be large, and may be ignored. The hierarchical approach then proceeds by passing the macromodels to the global grid and solving this reduced system. This solution yields the port voltages, which can then be used to find internal voltages within the local grids. They first partition th e whole network into macromodels, with each macromodel i described by its port currents and port voltages as follows: I i = A i · V i + S i , I i ∈ R m , A i ∈ R m×m , V i ∈ R m , S i ∈ R m (44.13) where m is the number of ports in the local grid A i is the port admittance matrix V i is the vector of voltages at the ports I i is the current through the interface between the local and the global grids S i is a vector of current sources connected between each port and the reference node vector The partitioning strategy they propose is to identify a subnetwork and an interface boundary such that the number of internal nodes is much larger than the square of the number of nodes at the interface. This is to ensure that each macromodel is not too densely stamped. The authors then Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 924 24-9-2008 #13 924 Handbook of Algorithms for Physical Design Automation proposed a 0–1 integer linear programming based sparsification technique to further reduce the matrix density. The p ort admittance matrix A i and current vector S i can be derived by looking at the MNA equations of the macro and by splitting the matrices into submatrices corresponding to the internal nodes and ports:  G 11 G 12 G T 12 G 22  U 1 V  =  J 1 J 2 + I  (44.14) and the formula for A i and S i can be derived as A i =  G 22 − G T 12 G −1 11 G 12  S i =  G T 12 G 1 11 J 1 − J 2  (44.15) where V i is the vector of voltages at the ports J 1 and J 2 are vectors of current sources connected at the internal nodes and ports, respectively I i is the vector of currents through the interface G 12 is the admittance of links between the internal nodes and the ports G 11 is the admittance matrix of internal nodes G 22 is the admittance matrix of ports. Because the LHS matrix in Equation 44.14 is positive definite, its Cholesky factorization is  G 11 G 12 G T 12 G 22  =  L 11 0 L 21 L 22   L T 11 L T 21 0 L T 22  =  L 11 L T 11 L 11 L T 21 L 21 L T 11 L 21 L T 21 + L 22 L T 22  (44.16) The explicit inverse of G 11 in Equation 44.15 can be avoided and efficiently computed by A i = L 22 L T 22 S i = L 21 L −1 11 J 1 − J 2 (44.17) The nodal equation for the global power grid can be formed by feeding each macromodel in ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ G 00 G 01 G 02 G 0k G T 01 A 1 G 12 G 1k G T 02 G T 12 A 2 G 2k . . . . . . G T 0k G T 1k G T 2k ··· A k ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ V 0 V 1 V 2 . . . V k ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ = ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ I 0 −S 1 −S 2 . . . −S k ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ (44.18) Here, partition 0 corresponds to the global nodes, and partition i, i > 0, to the local grids that are represented by Equation 44.13, and G ij represents the conductance links between partition and j. 44.3.2.2 Multigrid Methods Nassif et al. first p roposed to use idea of the multigrid solver for fast power grid analysis in Ref. [34] and they further expanded the idea and experiments in Ref. [33]. This method was moti- vated by the fact that the power grid equation system is structurally identical to that of a finite Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 925 24-9-2008 #14 Power Grid Design 925 element discretization of a two-dimensional p ar abolic partial differential equation (PDE) because the multigrid method is very efficient in solving smooth PDEs [40]. In iterative methods, the error between the approximate solution and the exact solution can be divided into two components: high-frequency and low-frequency Fourier modes [40]. Classi- cal iterative methods suffer from slow convergence because they are inefficient in reducing the low-frequency error components. In general, multigrid methods also consist o f two complementary components [40,41]: 1. Relaxation (smoothing), which reduces the high-frequency error components using a classical iterative solver. 2. Coarse grid correction, which reduces the low-frequency error components. It involves mapping the problem to some coarser grid ( 2h ), solving the mapped smaller problem using a direct solver or an iterative solver, and mapping the solution back to the o riginal fine grid ( h ). A restriction operator  2h h and a corresponding prolongation (interpolation) operator P h 2h are defined for the mappings between the coarse grid and the fine grid. Figure 44.6 illustrates a recursive V-cycle [40] of the multigrid method with three nested iterations. At the bottom level, the exact solution can be obtained from either a direct or an iterative solver. The multigrid-like power grid analysis method is explained as follows. First, the original power grid is reduced and the interpolation operator is defined. Then, the problem is mapped to the coarser grid, solved at the coarser grid using a direct solver, a nd then, the solution is mapped back to the original fine grid. I t is called multigrid-like because it ignores the relaxation step and therefore makes it a direct method, which has the advantage of maintaining fast speed without losing too much accuracy. Such a simiplifcation is justified by the fact that well-designed power grids are characterized by smooth voltage variation over the grid. The grid coarsening can be recursively repeated until the coarse grid is small enough to be exactly solved using a direct solver. The overall scheme consists of four passes. Initially, all voltage source nodes and corner nodes are flagged as K while other nodes are marked N. In the first pass, each K node is updated: starting from that node, we go along horizontal (vertical) direction and flag all visited nodes as H (or V ). A node flagged P 10 P 21 ℜ 12 ℜ 01 FIGURE 44.6 V-cycle of the multigrid method. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 926 24-9-2008 #15 926 Handbook of Algorithms for Physical Design Automation with both H and V is updated with the flag, K. In the second pass, each H (V) node is flagged as R and its neighbors along same row (column) as K. Next, in the third pass, the reduced grid is built by adding edges between the K nodes. Finally, in the fourth pass, the linear interpolation (INT()) is defined from neighboring nodes. If node m neighbors with nodes A and B,then V ( m ) = INT ( V(A), V ( B )) = α 0 V ( A ) + α 1 V ( B ) (44.19) where α 0 = g mA g mA +g mB and α 1 = g mB g mA +g mB . The voltages on the fine grid can be mapped from the coarse grid using this interpolation formula. The proposed technique is especially efficient in transient analysis. It applies a direct solver only on the reduced grid. Further more, while analyzing the reduced system matrix using fixed time step, only one initial factorization is needed and a forward/backward substitution will be performed in each following time steps. This further speedups the method because the solution for the fine grid can be obtained by linear interpolation, even though it compromises certain amount of accuracy. The geometrical grid reduction of the above algorithm for general irregular grids can become complicated to maintain smooth reduction. A typical power grid in lower level metal layers can be as irregular (a picture of this is provided in Figure 2 of Ref. [37]). Another weakness of the above grid reduction scheme is that it geometrically builds each level of grids (from the finest to the coarsest), which requires extra memory to store the graph data structure. To take ad vantage of the algebraic multigrid (AMG) technique that performs grid reduction through matrix multiplications, Ref. [37] proposes an AMG-based algorithm that constructs the restriction and interpolation matrices directly from the circuit (MNA) matrix. In general, variables representing important boundary conditions should be preserved. In the power grid model, these variables include all ideal voltage source nodes, all nodes in the top-level metal layer that are directly connected to package/pins, all package inductance or RL-in-series branches, and all nodes in the bottom-level metal layer that are connected to critical loads. The equationfor these boundary nodes/branchesareputat the beginning of the original G and C matrices, which makes them easy to be preserved. For the rest of the variables, the AMG-based grid reduction algorithm can be applied to determine the coarse-level grid points. The coarse grid has to be chosen to represent smooth errors and has to be able to interpolate these errors onto the fine grid. It is shown in Ref. [42] that smooth error varies slowly in the direction of strong connections. In power grid circuits, a strong connection between node p and node q in G means a relatively large conductance value at the off-diagonal entries (p, q)and(q, p), compared to the diagonal entries at (p, p)and(q, q). Therefore, a measure of connection between node p and q can be chosen as mes pq =  g pq /G p + g pq /G q  /2 (44.20) where G p and G q are self conductance at node p and q.Ifmes pq >ψ, node q is chosen in the coarse grid and p in the fine grid and will be interpolated as x(p) = x(q),whereψ is a threshold chosen to control the reduction rate and accuracy. This is equivalent to shorting node p to q when the resistor connected between them is small. The corresponding restriction matrix for shorting node p to q1in Figure 44.7 becomes R 5×4 = q1 q2 q3 q4 ⎡ ⎢ ⎢ ⎢ ⎢ ⎣ 1 1 1 1 1 ⎤ ⎥ ⎥ ⎥ ⎥ ⎦ q1 q2 p q3 q4 (44.21) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 927 24-9-2008 #16 Power Grid Design 927 To be shorted p q1 q2 q3 q4 FIGURE 44.7 Shorting node p to its strongly connected neighbor q1. This reduction scheme iterativelyremovesrelativelysmaller resistors in thegrid, thereforethenumber of nonzeros in the coarse-level matrix R T GR decreases. 44.3.2.3 Model Order Reduction Methods In model order reduction methods, the MNA equation of a linear circuit is typically described in the Laplace domain. ( G +sC ) V(s) = Bu ( s ) (44.22) where G and C represent the conductance and susceptance matrices. The vector V of the MNA variables is of dimension N ×1, and includes the nodal voltages and the branch currents for voltage sources and inductors. B is the input selector matrix mapping sources to the internal states, and u is the vector of independent sources. One of the most popular model order reduction methods is based on Krylov subspace methods, in which the following subspace is generated: spanG −1 B, G −1 CG −1 B, ,  G −1  n CG −1 B (44.23) The subspace matrix is then used to project the original system (Equation 44.22) onto a smaller system that usually keeps major ports u of the original system:  ˜ G + s ˜ C  ˜ V ( s ) = ˜ Bu ( s ) (44.24) where ˜ G, ˜ C, ˜ V,and ˜ B are the reduced matrices/vectors. From Equation 44.24, we can see that the number of independent source is a bottleneck of such methods. Different techniques to deal with this situation in power grid analysis have been proposed recently in Refs. [13,38]. In Refs. [13,38], instead of using piecewise linear-independentcurrent source as the load model, a switching RC cell model is used to avoid the problem of a large numberof ports. Therefore, the only independent sources in the power grid circuit are the independent voltage sources from the power pins or pads, which is significantly smaller compared to the total number of nodes in the circuit. When a p iecewise linear-independent current source model is used f or each cell, because the Laplace transform of each piecewise linear (PWL) source is not a constant term, an extended Krylov subspace (EKS) [43] method or an improved EKS (IEKS) method [32] need to be used. In EKS, the contribution of source moments are considered at each step of iteration during the Krylov subspace Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 928 24-9-2008 #17 928 Handbook of Algorithms for Physical Design Automation Overlying mesh Pad Pad + Underlying tree Contact point Pin FIGURE 44.8 Hybrid mesh/tree structure with the mesh in the upper level and trees in the lower level. (From H. Su, K. H. Gala and S. S. Sapatnekar , Analysis and Optimization of Structured Power/Ground Networks, IEEE TCAD, 22, 1533, 2003. With permission.) calculation and orthogonalization process. In addition, moment shifting has to be performed to recover the proper moments in EKS, therefore the IEKS method that no longer needs to perform moment shifting for source waveform modeling was proposed in Ref. [32]. Both works in Ref. [32] and Ref. [38] analyze the power grid circuit hierarchically. A hybrid mesh/tree topology (Figure 44.8) is proposed in Ref. [38] for fast turnaround time o f design and veri- fication of power grid. The model order reduction technique in this work is an enhanced PRIMA [44] method considering nonzero initial conditions in capacitors and inductors. The procedure contains three stages: first, each tree is reduced to an equivalent passive model. In this stage, an efficient path tracing technique [44] for trees is applied to speed up the reduced model computation. Next, the mesh along with these passive reduced tree models is further reduced using PRIMA and all nodal voltages in the mesh, i.e., mesh voltages can be obtained. Finally, these mesh voltages equivalent to voltage sources at the root of each tree are used to solve each tree individually and independently. The HiPRIME [32] algorithm hierarchically analyzes a general power g rid with the mesh struc- ture. It first partitions the circu it into multiple blocks and then generates multiport Norton equivalent order reduced circuits using PRIMA and IEKS and then combines all the reduced order macromodels into the higher level and perform either IEKS or PRIMA for further reduction, and poles and residues in the higher grids can be obtained. Finally, internal nodes inside each partition can be computed from the reduced order model of each partitio n and the voltages on the ports. 44.3.2.4 Random Walk Method In Refs. [35,36], a statistical approach based on random walks is proposed to perform power grid analysis. In this section, we only discuss in detail the DC analysis of the V dd grid, given that the ground grid can be similarly analyzed and that the method can be easily extended to h andle transient analysis. For the DC analysis of a power grid, a single node x in the circuit can be illustrated in Figure 44.9. According to Kirchoff’s current law, Kirchoff’s voltage law, and the device equations for the conductances, we have degree(x)  i=1 g i ( V i − V x ) = I x (44.25) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 929 24-9-2008 #18 Power Grid Design 929 1 3 4 2 I x g 1 g 2 g 3 g 4 x FIGURE 44.9 Representative node in the power grid. (From H. Qian, S. R. Nassif and S. S. Sapatnekar, Power Grid Analysis Using R andom Walks, IEEE TCAD, 24, 1204, 2005. With permission.) where the nodes adjacent to x are labeled 1, 2, ,degree(x) V x is the voltage at node x V i is the voltage at node i g i is the conductance between node i and node x I x is the current load connected to node x Equation 44.25 can be rewritten a s V x = degree(x)  i=1 g i  degree(x) j=1 g j V i − I x  degree(x) j=1 g j (44.26) We can see that this implies that the voltage at any node is a linear function o f the voltages at its neighbors. We also observe that the sum of the linear coefficients associated with the V i ’s is 1. For a power grid problem with N non-V dd nodes, we have N linear equations similar to the one above, one for each node. Solving this set of equations gives the exact solution. Now let us look at a random walk game, given a finite undirected connected graph (e.g., Figure 44.10) representing a street map. A walker starts from one of the nodes, and goes to an adjacent node i every day with probability p x,i for i = 1, 2, ,degree(x),wherex is the current node, degree(x) is the number of edges connected to node x. These probabilities satisfy the following relationship: degree(x)  i=1 p x,i = 1 (44.27) The walker pays an amount m x to a motel for lodging everyday, until he or she reaches one of the homes, which are a subset of the nodes. If the walker r eaches home, he or she will stay there and be awarded a certain amount of money, m 0 . We will consider the p roblem of calculating the expected amount of money that the walker has accumulated at the end of the walk, as a function of the starting node, assuming he or she starts with nothing. This gain function is therefore defined as f ( x ) = E  total money earned|walk starts at node x  (44.28) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 930 24-9-2008 #19 930 Handbook of Algorithms for Physical Design Automation Home Home Home m x p x, 2 p x, 3 p x, 1 FIGURE 44.10 Instance of a random walk game. (From Qian, H., Nassif, S. R., and Sapatnekar, S. S., IEEE TCAD, 24, 1204, 2005. With per mission.) It is obvious that f ( one of the homes ) = m 0 (44.29) For a nonhome node x , assuming that the nodes adjacent to x are labeled 1, 2, ,degree(x),thef variables satisfy f ( x ) = degree(x)  i=1 p x,i f ( i ) − m x (44.30) For a random-walk problem with N nonhome nodes, there are N linear equations similar to the one above, and solving this set of equations gives the exact values of f at all nodes. It iseasyto drawaparallel between thisproblem andpowergridanalysis. Equation44.30becomes identical to Equation 44.26, and Equation 44.29 reduces to the condition of perfect V dd nodes if p x,i = g i  degree(x) j=1 g j i = 1, 2, ,degree(x) m x = I x  degree(x) j=1 g j m 0 = V dd f ( x ) = V x (44.31) 44.3.3 POWER GRID ANALYSIS WITH UNCERTAIN WORK LOADS In Section 44.2.5, we outlined the various sources of variation that can impact power grid perfor- mance, and roughly divided them into (1) physical variations such as changes in the dimensions of power grid wires, and (2) loading variations that arise because of changes in the manner with which the integrated circuit operates. Consider the steady-state (DC) version of the power grid system of equations first introduced in Equation 44.11, which would be Gx = I (44.32) where G and x are the same as before I is a vector of node currents representing the loading at each node of the power grid Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 931 24-9-2008 #20 Power Grid Design 931 In Refs. [45,46], it was shown that the vector I can be represented as I = A.diag ( w ) .I b (44.33) where A is an n × k incidence matrix with n being the number of nodes, and k being the number of circuit blocks diag(w) is a k ×k matrix with diagonal entries being 0 for blocks that do not switch, and 1 for blocks that do I b is a k long vector of block currents Equations 44.11 and 44.33 describe the behavior of the power grid as the various parts of the circuit become active. With this formulation in place, one can motivate several analyses to study the dependence of the behavior of the power grid on circuit operation. The works in Refs. [45,46] showed how an integer linear program can be set up to determine the worst-case p ower grid drop under various constraints, e.g., the maximum power that a design can consume. A different approach it taken in Ref. [47] where a statistical bounding framework is developed to translate the statistical variations in leakage current, which would exhibit themselves as statistical variations in the components of the block current vector I b , to statistical bounds on the various node voltages. With power dissipation increasing, and manufacturing variability increasing, this area promises to remain relevant as researchers struggle to find efficient static (i.e., not specific to a particular workload) methods to insure the performance of a power grid. 44.4 POWER GRID OPTIMIZATION Given load current of each functional block, the goal of power distribution network optimization is to maintain voltage drop within certain threshold (typically 5 ∼ 10 percent V dd ) with various con- straints such as wiring resource, empty space for decaps, pin and pad locations, etc. The performance of power distribution network can therefore be improved through wire sizing, decap optimization, topology optimization, and optimal placement of power pins and pads. Combination of the above techniques has also been proposed in a number of literatures, for example, Refs. [48,49] perform simultaneous wire sizing and topology optimization and Refs. [13,38] perform simultaneous wire and decap sizing. 44.4.1 WIRE SIZING A general formulation o f power wire sizing is as follows: minimize area =  i l i W i subject to V g ≤ V th V p ≥ V dd − V th I i max ≤ I th and w min ≤ w i ≤ w max where l i represents the length of each P/G wire segment with width w i , which subjects to the minimum and maximum wire width constraints. Each nodal voltage V g in the ground network and V p in the power network should be constrained within a voltage drop limit V th typically chosen to be 5 ∼ 10 percent o f V dd . I th sets a threshold corresponding to the electromigration constraint for each wire segment. Voltages and currents here can either be the DC voltages/currents or the worst-case transient voltages/currents. This is a constrained nonlinear optimization problem. . V-cycle of the multigrid method. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 926 24-9-2008 #15 926 Handbook of Algorithms for Physical Design Automation with. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 922 24-9-2008 #11 922 Handbook of Algorithms for Physical Design Automation 44.3 POWER GRID. authors then Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C044 Finals Page 924 24-9-2008 #13 924 Handbook of Algorithms for Physical Design Automation proposed a 0–1 integer