Handbook of algorithms for physical design automation part 47 pps

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C021 Finals Page 442 24-9-2008 #21 442 Handbook of Algorithms for Physical Design Automation cons. A hybrid approach is proposed recently [15] to combine the netweighting and net constraints together with LP-based formulations. Furthermore, because of the complexity of modern placement problems and the iterative refinement nature from global placement to detailed/legal placement, it is very important to have stability between placement iterations. In this section, we present several representative and recent techniques for TDP and timing-aware p lacement. 21.6.1 HYBRID NET AND PATH-BASED APPROACH In Ref. [15], a hybrid approach is proposed to combine the netweighting and net constraints together with LP-based formulations. The net-based approaches, especially the netweighting, have low com- putational complexity and high flexibility/scalability. Therefore, net- based approaches have more advantages as the circuit complexity continues to increase. However, netweighting often completely ignores slew propagation. Because timing is inherently path based, an effective netweighting algo- rithm should be based on path analysis and consider timing propagation. Furthermore, net-based approaches are often done in an ad hoc manner and may have problems with convergence. For instance, while the delay on critical paths decrease, other paths become critical, and this leads to a convergence problem. A systematic way of explicit perturbation control is important for netweighting-based algorithms. The hybrid approach in Ref. [15] uses a hybrid net and path-based delay sensitivity with limited-stag e slew propagation as basis for netweighting. The objective func- tion is the weighted wirelength for a set of critical paths. The LP formulation considers not only cells on the timing-critical paths, but also cells that are logically adjacent to the critical paths in a unified manner, through weighted LP objective function and net-bound constraints. This approach is suitable for incremental timing improvement. 21.6.2 HIPPOCRATES: ADETAILED PLACER WITHOUT DEGRADING TIMING Another timing-driven incremental placement algorithm [60] helps to reduce TWL and improve timing at the same time. It specifically maintains the timing constraints while r educing wirelength during detailed placement. The detailed placement algorithms it uses can be any commonly used move-based transforms, i.e., cell swapping, cell moving, etc. Instead of modeling path constraints, it modelsthetimingconstraintsateachinputpin. Theadvantage ofthis is thatitreduces thecomputation complexity, which allows it to model timing constraints on every tim ing path. Therefore, the output of this algorithm guarantees no timing degradation. The timing constraint on each pin is called delta arrival time constraint, which is defined as the difference of arrival time at this p in to the arrival time of the most critical input pin on this gate. By constraining the delta delay changed by moving cells to be less than the delta arrival time on each pin, it guarantees that the final arrival time at timing endpoints would not degrade. It also models slew and load capacitance constraints. Experimental results [60] show that Hippocrates helps improve wirelength and timing significantly, in particular on TNS, while conventional detailed placement algorithms fail to maintain the original timing. 21.6.3 ACCURATE NET-MODELING ISSUE While most timing driven placers assume simple net models, some use specialized net models for timing critical nets, e.g., during global placement [61] or detailed placement [21]. The first, [61], based on force-directed global p lacement [35], proposes a more accurate tree net model to replace the ubiquitous clique/star net models normally used in quadratic placers. A Steiner tree net model is constructed and the length of each tree segment is controlled by weighting the individual segments to improve timing. This new model does not increase numerical complexity. This net model is not specific to the force-directed formulation and could be used in other QP-based placers. To determine the weight of each Steiner segment, the segment sensitivity is computed by determining the net delay derivative with respect to the segment length. In this way, the segments that produce the most slack improvement are shortened the most. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C021 Finals Page 443 24-9-2008 #22 Timing-Driven Placement 443 Another work [21] proposes simultaneous detailed placement and routing to optimize timing. The algorithm is stable and incremental, and it reduces WNS by 9–14 percent, although the runtime is quite high. It begins with a placed and global-routed netlist and optimizes the k most critical paths using a nonconvex mathematical programming model that optimizes slack while capturing the timing impact of cell movements and Steiner point changes of the global route. In this approach, cell movements may change the Steiner tree topology. Within the solving steps, each net is analyzed to ensure that its Steiner tree is correct, otherwise a new topology is generated. Because routing changes are modeled, this is a more accurate net model than those commonly used net models discussed in previous sections. 21.7 CONCLUSIONS Although TDP has been studied extensively in the past two decades, the problem is still far away from being solved [62]. Many challenges still remain due to the ever-growing problem size and complexity. On the one hand, modern system-on-chip designs have millions of placeable cells and hundreds/thousands of macros [63]; on the other hand, stringent timing requirements and physical effects pose increasing challenges to the timing closure where TDP plays a key role. It shall be noted that to achieve the overall timing closure, TDP needs to work closely with synthesis/optimization tools (such as buffer insertion and gate sizing) and routing (in particular global routing). The entire physical design/synthesis closure is an extremely complex task. Furthermore, modern complex SOC designs usually have multiple clock domains, or even multiple cycle paths, which make the TDP problem even more complicated. Because of the infrastructure limitation, the academia has not been able to fully push the state of the art and limits of TDP. With the availability of OpenAccess [64] and the OpenAccess gear timer [65,66], it is possible to push the frontier of the very successful International Symposium on Physical Design (ISPD) placement contest [63] for university researchers to work on more realistic timing objectives. As technology scales into sub100 nm regimes, new physical and manufacturing effects, in particular leakage/power and variations, have to be considered together with timing closure during TDP [67,68], which requires continuous innovations for better quality and productivity. REFERENCES 1. A.E. Dunlop, V.D. Agrawal, D.N. Deutsch, M.F. Jukl, P. Kozak, and M. Wiesel. Chip layout optimiza- tion using critical path weighting. In Proceedings of the Design Automation Conference,LasVegas,NV, pp. 133–136, 1985. 2. M. Burstein and M.N. Youssef. Timing influenced layout design. In Proceedings of the Design Automation Conference, Albuquerque, NM, pp. 124–130, 1984. 3. T. Kong. A novel net weighting algorithm for t iming-driven placement. In Proceedings of the International Conference on Computer Aided Design, S an Jose, CA, pp. 172–176, 2002. 4. H. Ren, D.Z. Pan, and D. Kung. S ensitivity guided net weighting for placement driven synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Phoenix, AZ, pp. 711–721, May 2005. (ISPD 2004) . 5. T. Gao, P.M. Vaidya, and C.L. Liu. A performance driven macro-cell placement algorithm. In Proceedings of the Design Automation Conference, Anaheim, CA, pp. 147–152, 1992. 6. R.S. Tsay and J. Koehl. An analytic net weighting approach for performance optimization in circuit placement. In Proceedings of the Design Automation C onference, San Francisco, CA, pp. 636–639, 1991. 7. M. Sarrafzadeh, D. Knol, and G. Tellez. Unification of budgeting and placement. In P roceedings of the Design Automation C onference, Anaheim, CA, pp. 758–761, 1997. 8. K. Rajagopal, T. Shaked, Y. Parasuram, T. Cao, A. Chowdhary, and B. Halpin. Timing driven force directed placement with physical net constraints. In Proceedings of the International Symposium on Physical Design, San Diego, CA, pp. 60–66, 2003. 9. B.Halpin, C.R. Chen,andN. Sehgal. Timingdriven placementusing physical netconstraints. In Proceedings of the Design Automation Conference, Las Vegas, NV, pp. 780–783, 2001. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C021 Finals Page 444 24-9-2008 #23 444 Handbook of Algorithms for Physical Design Automation 10. S. Hur, T. Cao, K. Rajagopal, Y. Parasuram, A. Chowdhary, V. Tiourin, and B. Halpin. Force directed mongrel with physical net constraints. In Proceedings of the Design Automation Conference, Anaheim, CA, pp. 214–219, 2003. 11. M.A.B. Jackson and E.S. Kuh. Performance-dri ven placement of cell based ic’s. In Proceedings of the Design Automation Conference, Las Vegas, NV, pp. 370–375, 1989. 12. A. Srinivasan, K. Chaudhary, and E.S. Kuh. Ritual: A performance driven placement algorithm for small cell ics. In Proceedings of the International Conference on Computer Aided Design, Santa Clara, CA, pp. 48–51, 1991. 13. W. Swartz and C. Sechen. Timing driven placement for large standard cell circuits. In Proceedings of the Design Automation Conference, San Francisco, CA, pp. 211–215, 1995. 14. A. Ch owdhary, K. Rajagopal, S.Venkatesan, T. Cao, V. Tiourin, Y. Parasuram, andB. Halpin. How accurately can we modeltiming in a placement engine. In Proceedings of the D esign Automation Conference, Anaheim, CA, pp. 801–806, 2005. 15. T. Luo, D. Newmark, and D.Z. Pan. A new LP based incremental timing driven placement for high perfor- mance d esigns. In Proceedings of the Design Automation Conference, S an Francisco, CA, pp. 1115–1120, 2006. 16. A.B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. Proceedings of the International Symposium on Physical Design, Phoenix, AZ, pp. 18–25, April 2004. 17. T. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Pr oceedings of the International Symposium on Physical Design, pp. 185–192. ACM Press, N ewYork, 2005. 18. M.A. Breuer, M. Sarrafzadeh, and F. Somenzi. Fundamental CAD algorithms. IEEE Transactions on Computer-Aided Design, 19(12): 1449–1475, 2000. 19. K.D. Boese, A.B. Kahng, and S. Mantik. On the r elevance of wire load models. In Proceedings of the 2001 International Workshop on System-Level Interconnect Prediction, Rohnert Park, CA, pp. 91–98. ACM Press, 2001. 20. P. Saxena and S. Gupta. Shield count minimization in congested regions. In Proceedings of 2002 International Symposium on Physical Design, Del Mar, CA, pp. 78–83. ACM Press, 2002. 21. A.H. Ajami and M. Pedram. Post-layout timing-driven cell placement using an accurate net length model with movable steiner points. In Pr oceedings of the Asia and South Pacific Design Automation Confer ence, Yokohama, J apan, pp. 595–600, 2001. 22. J.A. Roy, J.F. Lu, and I.L. Markov. Seeing the forest and the trees: Steiner wirelength optimization in placemen. In ISPD ’06: Proceedings of the 2006 International Symposium on Physical Design, pp. 78–85. ACM Press, New York, 2006. 23. L.T. Pillage and R.A. Rohrer. Asymptotic waveform evaluation for timing analysis. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 9: 352–366, April 1990. 24. N. Maheshwari and S. Sapatnekar. Timing Analysis and Optimization of Sequential Circuits.Kluwer Academic Publishers, 1999. 25. Sr. R.B. Hitchcock. Timing verification and the timing analysis program. In Proceedings of th e Design Automation Conference, pp. 594–604, 1982. 26. C.C. Chang, J. Lee, M. Stabenfeldt, and R.S. Tsay. A practical all-path timing-driven place and route design system. In Asia-Pacific Confer ence on Circuits and Systems, pp. 560–563. IEEE/ACM, 1994. 27. A. Marquardt, V. Betz, and J. Rose. Timing driven placement for FPGA. In ACM Symposium on FPGA, Monterey, CA, pp. 203–213, 2000. 28. M. Marek-Sadowska and S.P. Lin. Timing driven placement. In Proceedings of the International Conference on Computer Aided Design, San Jose, CA, pp. 94–97, 1989. 29. H. Chang, E. Shragowitz, J. Liu, H. Youssef, B. Lu, and S. Sutanthavibul. Net criticality revisited: An effective method to improve timing in physical design. In Proceedings of the I nternational Symposium on Physical Design, Del Mar, CA, pp. 155–160, April 2002. 30. W.K. Luk. A fast physical constraint generator for timing driven p lacement. In Proceedings of the Design Automation Conference, pp. 626–631, 1991. 31. B. Halpin, C.Y.R. Chen, and N. Sehgal. A sensitivity based placer for standard cells. In Proceedings of the 10th Great Lakes Symposium on VLSI, Chicago, IL, pp. 193–196, 2000. 32. J. Cong, L. He, C K. Koh, and P.H. Madden. Performance optimization of VLSI interconnect layout. I nt egration, the VLSI Journal, 21: 1–94, 1996. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C021 Finals Page 445 24-9-2008 #24 Timing-Driven Placement 445 33. J. Cong, J.R. Shinnerl, M. Xie, T. Kong, and X. Yuan. Large-scale circuit placement. In ACM Transactions on Design Automation of Electronic Systems, pp. 389–430, 2005. 34. B.M. Riess and G.G. Ettelt. SPEED: Fast and efficient timing driven placement. In Proceedings of the IEEE International Symposium on Circuits and Systems, Seattle, WA, pp. 377–380, 1995. 35. H. Eisenmann and F.M. Johannes. Generic global placement and fl oorplanning. In Proceedings of the Design Automation C onference, San Francisco, CA, pp. 269–274, 1998. 36. D.J.H. Huang and A.B. Kahng. Partition-based standard-cell global placement with an exact objective. In Proceedings of the International Symposium on Physical Design, Napa Valley, CA, pp. 18–25, 1997. 37. S. Ou and M. Pedram. Timing-driven placement based on partitioning with dynamic cut-net control. In Proceedings of the Design Automation Confer ence, Los Angeles, CA, pp. 472–476, 2000. 38. S. Ou and M. Pedram. Timing-driven bipartitioning with replication using iterative quadratic program- ming. In Proceedings of the Asia and South Pacific Design A utomation Conference, Wanchai, Hong Kong, pp. 105–108, 1999. 39. A.B. Kahng, S. Mantik, and I.L. Markov. Min–max placement for large-scale timing optimization. In Proceedings of the International Symposium on Physical Design, Del Mar, CA, pp. 143–148, 2002. 40. A.B. Kahng, I.L. Markov, and S. Reda. Boosting: Min-cut placement with improved signal delay. In Proceedings of the Design, Automation and Test i n Europe, Paris, France, pp. 1098–1103, 2004. 41. R. Nair, L. Berman, P.S. Hauge, and E.J. Yoffa. Generation of performance constraints for layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(8): 860–874, 1989. (ICCAD 1987) . 42. H. Youssef and E. Shragowitz. Timing constraints for correct peformance. In Proceedings of the International Conference on Computer Aided Design, Santa C lara, CA, pp. 24–27, 1990. 43. J. Frankle. Iterative and adaptive slack allocation for performance-driven layout and FPGA routing. In Proceedings of the Design Automation Confer ence, Anaheim, C A, pp. 539–532, 1992. 44. M. Sarrafzadeh, D. Knol, and G. Tellez. A delay budgeting algorithm ensuring maximum flexibility inplacement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 16(11): 1332–1341, November 1997. 45. S. Ghiasi, E. Bozorgzadeh, S. Choudhuri, and M. Sarrafzadeh. A unified theory of timing budget man- agement. In Proceedings of the International Conference on Computer Aided Design, San Jose, C A, pp. 653–659, 2004. 46. X. Yang, B. Choi, and M. Sarrafzadeh. Timing-driven placement using design hierarchy gui ded constraint generation. In P roceedings of the International Conference on Computer Aided Design, San Jose, CA, pp. 177–180, 2002. 47. W. Choi and K. Bazargan. Incremental placement for timing optimization. In Proceedings of the International Conference on Computer Aided Design, San Jose, CA, pp. 463–466, 2003. 48. M. Terai, K. Takahashi, and K. Sato. A new mi n-cut placement algorithm for timing assurance layout design meeting net length constraint. In DAC ’90: Proceedings of the 27th ACM/IEEE Conference on Design Automation, pp. 96–102. ACM Press, New Yor k, 1990. 49. C.M. Fiduccia and R.M. Mattheyses. A linear-time heuristic for improving network partitions. In Pr oceedings of the Design A utomation C onference, pp. 175–181, 1982. 50. R S. Tsay, E.S. Kuh, and C P. Hsu. Proud: A fast sea-of-gates placement algorithm. In Proceedings of the Design Automation C onference, Atlantic City, NJ, pp. 318–323. IEEE C omputer Society Press, 1988. 51. J.M. Kleinhans, G. Sigl, F.M. Johannes, and K.J. Antreich. Gordian: VLSI placement by quadratic pro- gramming and slicing optimization. IEEE Transactions on Computer-Aided Design, 10( 3): 356–365, 1991. 52. B. Halpin, C.Y.R. Chen, and N. Sehgal. Detailed placement with net length constraints. In Proceedings of the 3rd International Workshop System on Chip, Alberta, Canada, p. 22, 2003. 53. S. Hur and J. Lillis. Mongrel: Hybrid techniques for standard cell placement. In Proceedings of the International Conference on Computer-Aided D esign, San Jose, CA, pp. 165–170. IEEE, 2000. 54. C. Sechen. V L SI Placement and Global Routing Using Simulated Annealing. Kluwer, B.V., 1988. 55. C. Sechen and A.S. Vincentelli. The Timberwolf placement and routing package. In IEEE Custom Inte grated Circuits Conference, pp. 522–527, 1984. 56. W.J. Sun and C. Sechen. A loosely coupled parallel algorithm for standard cell placement. In Proceedings of the International Conference on Computer-Aided Design, San Jose, CA, pp. 137–144. IEEE, 1994. 57. K. Doll, F.M. Johannes, and K.J. Antreich. Iterative placement improvement by network flow methods. IEEE Transactions on Computer-Aided Design, 13: 1190–1200, 1994. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C021 Finals Page 446 24-9-2008 #25 446 Handbook of Algorithms for Physical Design Automation 58. W.C. Elmore. The transient response of damped linear networks with particular regard to wide-band amplifiers. Journal of Applied Physics, 19( 1): 55–63, January 1948. 59. S.E. Dreyfus. An appraisal of some shortest-path algorithms. Operations Research, 17: 395–412, 1969. 60. H. Ren, D.Z. Pan, C. Alpert, G J. Nam, and P. Villarrubia. Hippocrates: First-do-no-harm detailed place- ment. In Proceedings of the Asia and Sout h Pacific Design Au tomation Conference, Yokohama, Japan, January 2007. 61. B. Obermeier and F.M. Johannes. Quadratic placement using an improv ed timing model. In Proceedings of the Design Automation Conference, San Diego, CA, pp. 705–710, 2004. 62. J. Cong, M. Romesis, and M. Xie. Optimality and stability study of timing-driven placement algorithms. In Proceedings of the International Conference on Computer Aided Design, p. 472. IEEE Computer Society, Washington DC, 2003. 63. G J. Nam. ISPD 2006 placement contest: Benchmark suite and results. In Proceedings of the International Symposium on Physical Design, pp. 167–167. ACM Press, New York, 2006. 64. http://openeda.si2.org/. 65. Z. Xiu and R.A. Rutenbar. Timing-driven placement by grid-warping. In Proceedings of the Design Automation Conference, Anaheim, CA, pp. 585–590, 2005. 66. Z. Xiu, D.A. Papa, P. Chong, C. A lbrecht, A. Kuehlmann, R.A. Rutenbar, and I.L. Markov. Early research experience with openaccess gear: An open source development environment for physical design. In Pr oceedings of the International Symposium on Physical Design, pp. 94–100. ACM Press, New York, 2005. 67. Y. Cheon, P H. Ho, A.B. Kahng, S. Reda, and Q. Wang. Power-aware placement. In Proceedings of the Design Automation Conference, pp. 795–800. ACM Press, New York, 2005. 68. A.B. Kahng, C H. Park, P. Sharma, and Q. Wang. Lens aberration aware timing-driven placement. In Proceedings of the Design, Automation and Test in Europe, pp. 890–895, 3001. European Design and Automation Association, Leuven, Belgium, 2006. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C022 Finals Page 447 24-9-2008 #2 22 Congestion-Driven Physical Design Saurabh N. Adya and Xiaojian Yang CONTENTS 22.1 Introduction 447 22.2 Netlist-Connectivity-Based Approaches 448 22.2.1 Metrics for Structural Logic Synthesis 448 22.2.2 Congestion-Aware Logic Synthesis 449 22.2.3 Perimeter-Degree: A Priori InterconnectionComplexity Metric 450 22.3 Global-Placement Congestion Improvement 452 22.3.1 Incorporating Congestion Estimation during Global Placement 452 22.3.2 Steiner Wirelength Optimization during Global Placement 454 22.3.3 Free Space Management during Global Placement 455 22.4 Detailed Placement Congestion Improvement 456 22.4.1 Router Integration 458 22.4.2 Whitespace Management 458 22.5 Simulated Annealing for Congestion Improvement 461 22.5.1 RISA 461 22.5.2 Overflow with Look-Ahead 462 22.5.3 A-Tree Router 463 22.5.4 Sparse Parameter 463 22.6 Conclusion 464 References 464 22.1 INTRODUCTION This chapter discusses the impact and optimization of placement on the routing stage. This is com- monly referred as congestion-driven placement. Although a placer that produces unroutable designs will be of little use, historically optimization to directly reduce routing congestion has received less attention than wirelength and timing optimization. Often placement papers fail to report any infor- mation on congestion and routability. Over the last decade, with design sizes increasing dramatically and limited number of metal layers available for routing of signals and power, routability has become a paramount issue. This has driven the recent research interest in placement techniques to mitigate congestion while optimizing other placement objectives. Congestion-driven placement techniques can be classified into the following groups: netlist- connectivity-based methods, pin-density-based methods, and routing-estimation-based methods. Netlist-connectivity-based methods use a priori information about the netlist characteristics to influ- ence the placement process. Pin-density-based methods seek to limit the average pin density in local regions to indirectly address the routability concerns. Routing-estimation-based methods are frequently used during and after the placement process when sufficient routing congestion informa- tion is available. Global routers or probabilistic route estimators are often used to drive the various 447 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C022 Finals Page 448 24-9-2008 #3 448 Handbook of Algorithms for Physical Design Automation congestion mitigation techniques. Other notable techniques for addressing congestion in the design process include congestion-driven logic synthesis and global-placement density control. Several of these techniques are applied separately during global placement and detail placement, the details of each approach change according to the specific context. Often a placement flow will employ one or several of these methods. 22.2 NETLIST-CONNECTIVITY-BASED APPROACHES Recent advances in placement technology have attempted to alleviate the problem of wiring con- gestion during very large scale integration (VLSI) chip design. Classically, placement algorithms find the optimal location of the logic without attempting to change the structure of the logic netlist itself. However, the inhe rent structure o f the logic netlist has a sig nificant impact on the routabil- ity, irrespective o f the placement algorithm used. With the advent of physical synthesis techniques, there have been several attempts to combine placement transformations of the netlist in conjunction with logic synthesis transforms. Such efforts [14,15,31] have concentrated mainly in improving the delay or area characteristics of the final implementation of the design. Significant decisions regard- ing the circuit structure are made early in the synthesis stages such as register transfer level (RTL) decomposition, technology-independentlogic optimization, technology mapping, etc. For deep sub- micron (DSM) technologies, the wiring capacitance dominates the gate capacitance and the delay estimation based on fanout, and design legacy statistics (wireload tables) can be highly inaccurate. In addition, logic block size is no longer dictated solely by total cell area, and is often limited by routing resources. For these reasons, wiring congestion is an extremely important design metric and should be taken into consideration at the earliest possible stage of the design flow. In physical design, the required routing resources are captured in terms of routing congestion. Placement or routing can sometimes fix, or avoid, potential congestion problems. However, the netlist structure determined during logic synthesis may mean that it is too late in the flow to target congestion problems. In the following subsections, we detail several recent approaches to target placement congestion b y netlist transformations during the logic synthesis stage or by using inherent netlist properties to influence congestion-driven placement. 22.2.1 METRICS FOR STRUCTURAL LOGIC SYNTHESIS The work in Ref. [26] motivates that a property of the network structure called adhesion can make a significant contribution to routing congestion. The work targets the technology-independent logic optimization stage. Classically, in this stage, literal count is used as a metric for optimiza- tion. However, this does n ot adequately capture the intrinsic entanglement of the netlist. Two circuits with identical literal counts may have significantly different congestion characteristics post- placement. It is shown that by optimizing the adhesion metric in addition to literal count during technology-independent optimization, postrouting congestion can be improved. The adhesion metric of a logic network is defined as follows: Definition 1 The adhesion of a logic network represented by an undirected graph G(V,E) can be measured by the minimum number of edges between all pairs s , t ∈ V that if removed from the graph would disconnect the graph. For measuring connectivity in a technology-independent netlist, the authors propose use of the all-pairs minimum-cut problem to determine the minimum cutsize of all pairs of nodes of a graph. The metric used to describe adhesion of a graph is sum o f all-pairs mincut (SAPMC). The following lemma is hence proposed. Lemma 1 The adhesion in an undirected graph representing a logic network as given by Definition 1, can be measured by the SAPMC for the graph. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C022 Finals Page 449 24-9-2008 #4 Congestion-Driven Physical Design 449 The authors propose the following conjectures to apply the property of adhesion during logic synthesis optimization. This conjecture is then evaluated empirically. Conjecture 1 Networks with lower adhesion value will on the average have better routability postplacemen t. Conjecture 2 Using adhesion during logic synthesis transformations will result on the average in better routability postplacement. As an example of adhesion, the authors give the example in Figure 22.1. Figure 22.1a is an unoptimized network. Two possible optimizations are applied to the original unoptimized network to obtain two implementations, opt 1 in Figure 22.1b and opt 2 in Figure 22.1c. The opt1 circuit has a SAPMC cost of 173, while the opt2 optimized circuit has a SAPMC cost of 152. According to Conjecture 2, opt 2 is a better optimization for the same connection cost of 18 for the two implementations. The authors perform extensive experiments to validate their conjecture that optimizing the adhe- sion metric during logic synthesis does indeed reduce congestion postplacement of the mapped netlist. First, they show a strong corelation between SAPMC metric and postplacement congestion by changing the fast extraction, f x , logic synthesis transform to randomly select an improvement rather than operate in a greedy fashion. Such choices to optimize adhesion as a metric could also be made during other logic synthesis optimizations like cloning, buffer insertion, rewiring, and factor- ization. Theresults show a correlationof adhesion as measuredbySAPMC to average,andmaximum wirelength. Adhesion can be used in conjunction with traditional properties like literal count, number of cells, and cell count as logic synthesis metrics. 22.2.2 CONGESTION-AWARE LOGIC SYNTHESIS The work by Pandini et al. [31] proposes several techniques to incorporate congestion minimiza- tion within logic synthesis. Modern logic synthesis systems are typically divided into two phases: technology-independent optimization and technology mapping. The first phase is concerned with finding a representation of the Boolean equations with the min imum number of liter als in the factored form. Technology mapping is the task of transforming a technology-independent logic network into a technology-dependent gate-level netlist. A popular approach to technology mapping implemented in DAGON [12] and MIS [24] is to reduce the problem to directed acyclic graph (DAG) covering problem. The DAG covering problem was approximated by a sequence of tree coverings, which can be solved optimally using dynamic programming. The technology mapping is usually divided into three stages: DAG partitioning, matching, and covering. During DAG partitioning, th e network DAG is partitioned into a forest of trees. Subsequently, for each tree, a matching algorith m iden tifies (a) Original circuit (b) Optimized circuit 1: opt1 (c) Optimized circuit 2: opt2 h g + * * ** c * b f e ~b ~d ~c h g + * * * * b e ~b ~c cf c f h g + * * ** b e ~b ~c FIGURE 22.1 Example of adhesion in a logic network. (From Kudva, P. and Dougherty, A., ICCAD, 2002.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C022 Finals Page 450 24-9-2008 #5 450 Handbook of Algorithms for Physical Design Automation Technology independent optimization Logic synthesis Technology mapping Global placement and congestion map Initial placement Technology independent netlist High level description RoutingPlacement YES NO Is congestion OK? FIGURE 22.2 Application specific integrated circuit (ASIC) design flow to account for congestion in logic synthesis. (From Pandini, D., Pileggi, L. T., and Strojwas, A. J., DATE, 2002.) all possible matches, corresponding to instances of a cell library, for each subnetwork. Finally, an optimal choice according to a cost factor is selected among the matches. The work in Ref. [31] targets the DAG partitioning and covers steps to improve congestion of the final implementation. The proposed approach in Ref. [31] for congestion-aware technology mapping can be integrated into traditional ASIC design flow, as shown in Figure 22.2. A technology-independent netlist and its initial placement is obtained. If congestion is deemed as a problem for the netlist, technology mapping is carried out in a congestion-aware manner as explained below. Placement-driven DAG partitioning algorithm proposed in Ref. [31] is shown in Figure 22.3 and is based on depth-first search (DFS) traversal from the circuit primary outputs to the primary inputs. The difference from classical DAG partitioning is that partitioning at multifanout vertices is carried out by taking intoaccountthe physical location of the correspondingbase gates obtained from placement of the technology-independentnetlist. The partitioning is based o n the following property: the father of every internal vertex is always the nearest vertex on the chip layout image according to some distance metric. The function distance() uses the placement information to compute the geometric distance between two adjacent vertices. The performance of the partitioning algorith m is not dependent on the order the DAG roots are processed, but it depends only on the physical locations of the technology-independent gates. Also, subject trees that cluster vertices placed in the same neighborhood are obtained by means of this DAG partitioning algorithm. For the tree-covering stage of the DAG covering problem, the authors propose only a change in the cost function to the original tree-covering algorithm proposed in Ref. [24]. The optimization objective is expanded b y including the wirelength contribution into the cost function. 22.2.3 PERIMETER-DEGREE: APRIORI INTERCONNECTION COMPLEXITY METRIC Several of the popular congestion mitigation techniques can be classified as a priori congestion tech- niques (preplacement), online methods (during placement), and posteriori methods (postplacement). Most of existing congestion minimization techniques are posteriori. The work in Ref. [34] present several techniques for a priori congestion minimization using the concept of perimeter-degree. They show that the number of external nets is not a desirable candidate for identifying potential regions of high-interconnect density. Alternatively, they propose perimeter-degree as an effective metric for Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C022 Finals Page 451 24-9-2008 #6 Congestion-Driven Physical Design 451 procedure DAG _ Partitioning ( graph DAG, array COORD) for_each v inDAG do v.father = nil; od; for_each v in DAG. roots() do PDP (DAG, v, COORD); od; procedure PDP ( graph DAG, vertex v, array COORD) v.visited = true; for_each e in DAG. outedges (v) do w = DAG. target ( e ); if (not w.visited) then dist = INFINITY ; for_each f in DAG. inedges (w) do u = DAG. source (f); this_dist = distance (COORD[u], COORD[w]); if (this_dist < dist) then dist = this_dist; w.father = u; fi; od; PDP (DAG, w, COORD); fi; od; FIGURE 22.3 Placement-driven DAG partitioning algorithm. PDP stands for placement-driven partitioning. (From Pandini, D., Pileggi, L. T., and Strojwas, A. J., DATE, 2002.) identifying congested regions on a chip. perimeter-degree (P peri ) is defined as follows. A region represents a placement bin on the die or a cluster of cells. The degree of a region is the number of nets exposed from the region. The perimeter-degree of the region is the region degree divided by the regionperimeter. The bin degree and pin density are two common metrics used for simple congestion control [44]. However, it is misleading to compare just degrees of two regions with dissimilar area. The d egree needs to be normalized. Because the degree of a region represents the routing demand at the edges of a region, it is natural to use the perimeter of the region as the normalizing factor. Figure 22.4 shows how two regions with the same degree can have different perimeter degrees. Naturally, region A would have a higher routing supply demand compared to region B. The authors of Ref. [34] detail simple ways to incorporate the perimeter-degree objective in a multilevel partitioning-based placement tool. The first is to use the perimeter-degree at every cell to compute the cell inflation before p lacement starts. The r ational is to inflate cells with higher perime- ter degree before the clustering phase of multilevel placement. This ha s the effect of d iluting the inherently high-density portions of the netlist. There are different thresholds for higher utilization designs compared to lower utilization designs. The second technique is to inflate the clusters formed during the clustering stage with respect to their perimeter-degree. This is done to prevent dense AB FIGURE 22.4 Equal d egree but different perimeter-degree. ( From Selvakkumaran, N., Parakh, P., and, Karypis, G., SLIP, 2003.) . Computer-Aided Design, 13: 1190–1200, 1994. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C021 Finals Page 446 24-9-2008 #25 446 Handbook of Algorithms for Physical Design Automation 58 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C021 Finals Page 442 24-9-2008 #21 442 Handbook of Algorithms for Physical Design Automation cons. A hybrid. placementusing physical netconstraints. In Proceedings of the Design Automation Conference, Las Vegas, NV, pp. 780–783, 2001. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C021