Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 716 2009-10-2 716 Model-Based Design for Embedded Systems 270.0 m 220.0 m 190.0 m 120.0 m 0.0 m 1.012 1.004 0.996 0.988 480.0 m 400.0 m 340.0 m 300.0 m 270.0 m 240.0 m 210.0 m (a) –80.0 m –494.0 m –498.0 m –502.0 m –506.0 m Ax input Gx input Ay input Gy input Az input Gz input MF (V) MF (V)MF (V)MF (V)MF (V)MF (V) Ax start sample Ax finish ADC Ay finish ADC Az finish ADC Gx finish ADC Ay start sample Az start sample Gx start sample Ax data out Az data out Ay data out Gx data out Gy finish ADC Gy start sample Gy data out IMU data out Gz finish ADC Gz start sample Gz data out Address Command Clk IBIS Time (s) 0.80 m (b) 0.82 m 0.84 m 0.86 m 0.88 m 0.90 m 0.92 m 0.94 m 0.96 m 0.98 m 1.00 m FIGURE 21.20 IMU simulation. The behavior of the interface can be summarized as follows: • The interface is always expecting data, so when no data are received the interface status does not change. • When the IBIS sends a command, the interface sends signals to the SH and the ADC to start the data acquisition. The SH holds the sig- nal while the ADC converts it to digital data. When the conversion is finished, the ADC informs the interface and sends the digital data. Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 717 2009-10-2 Smart Sensors Modeling Using VHDL-AMS 717 The interface transmits the data to the IBIS bus, and waits for new commands. 21.8 Simulation and Validation Once the models for the complete IMU system have been developed, it is possible to cosimulate the entire system. This simulation (see Figure 21.20) involves the three accelerometers and the three gyroscopes with their corres- ponding excitation signals, and the IBIS bus requesting and receiving data. This simulation shows the complete process of acquiring the signal after the IBIS sends the command until the data is transmitted to the bus, with the main intermediate signals. Each sensor has been assigned to one address, so when the IBIS wants data from one sensor, it sends a frame composed of an address and a command. When the addressed sensor receives the command from the IBIS, the data capture takes place. When the process is finished, a signal is activated to indicate that the conversion has finished, and the final data is sent through the bus. 21.9 Conclusions This chapter shows a VHDL-AMS approach to behavioral modeling of MEMS-based microinstrumentation using a design methodology with a dis- tributed architecture. The development of behavioral models playsanimpor- tant role in the design process, and thanks to the mixed-signal hardware description languages it is possible to cosimulate the entire system composed of elements of a different nature. These models allow reducing simulation time, and give the designer the possibility to mix different levels of abstrac- tion to correct parameters and to evaluate interaction between modules. In future work, these results will help the design process allowing the simu- lation of electrical and nonelectrical features of microsystems applications since early phases of the design process. Acknowledgments The authors gratefully acknowledge the contributions and helpful comments of Guo Yi, Xavier Fitó, and Eleni Kanellou within the IMU modeling. The work presented in this chapter was supported by CICYT under ADDRESS project: TEC 2006-04123 and I3P scholarship program. Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 718 2009-10-2 718 Model-Based Design for Embedded Systems References 1. A. Vachoux, Analog and Mixed-Signal Hardware Description Languages, Kluwer Academic Publishers, Norwell, MA, July 1997. 2. A. Dewey, H. Dussault, J. Hanna, E. Christen, G. Fedder, B. Romanowicz, and M. Maher, Energy-based characterization of microelectromechanical systems(MEMS) and component modeling using VHDL-AMS, MSM99, Technical Proceedings of the 1999 International Conference on Modelling and Simulation of Microsystems, pp. 139–142, Puerto Rico, April 19–21, 1999. 3. B.J. Hosticka, Circuit and System Design for Silicon Microsensors, Fraun- hofer Institute of Microelectronic Circuits and Systems, Duisburg, Germany, 1997. 4. B. Lorente, J. Oliver, and C. Ferrer, Towards a distributed architecture for MEMS integration, Journal of Sensors & Actuators A: Physical, 115(2–3), 2004, 470–475. 5. C. Ferrer and B. Lorente, Smart sensors development based on a dis- tributed bus for microsystems applications, Proceedings of the SPIE’s First International Symposium on Microtechnologies for the New Millennium 2003: Smarts Sensors, Actuators and MEMS, Maspalomas, Gran Canaria, Spain, May 19–21, 2003. 6. J. Hanna and R. Hillman, A common basis for mixed-technology micro- system modeling, Technical Proceedings of the 1999 International Conference on Modeling and Simulation of Microsystems, Puerto Rico, 1999. 7. A. Wada and K. Tan, Top-down design methodology of mixed signal with analog-HDL, IEICE Transactions on Fundamentals, E80-A(3), March 1997, 441–446. 8. A. Collado, J.A. Plaza, E. Cabruja, and J. Esteve, Adapting MCM-D tech- nology to a piezoresistive accelerometer packaging, Journal of Microme- chanics and Microengineering, Institute of Physics Publishing Ltd., Bristol, UK, June 41–44, 2003. 9. D. Potter, Smart plug and play sensors, IEEE Instrumentation & Measure- ment Magazine, 5(1), 28–30, 2002. 10. J. Zhang, Y. Ge, X. Wang, G. Song, and J. Jiang, P2-39: Design and application of the field-bus-based intelligent robot plug and play sens- ing system, Sensors, 2002. Proceedings of IEEE, Orlando, FL, 2002. 11. K. Lee, Sensor Networking and Interface Standardization, National Institute of Standards and Technology, Gaithersburg, MD, 2001. Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 719 2009-10-1 Index A Abstract state machines (ASM), 463–464 Accelerometer description, 704–706 IBIS drivers, 708, 710–711, 714 interface, 711 output circuitry band-pass filter, 706–707, 711, 712 Chopper stabilization (CHS), 706 excitation signal, 708, 714 low-pass filter, 707–708, 709 modulator, 707, 710 preamplifier, 707, 710 simulation results, 707, 713 Actor-oriented models, 561–563 ADC, see Analog-to-digital converter Adhoc on-demand vector (AODV) routing protocol, 164–165 Analog-clock test generation, 417–418 Analog-to-digital converter (ADC), 703 Angular spectrum technique advantage, 665–666 complex wave function, 663 coordinate systems, 664–665 discrete Fourier transform (DFT), 666 FFT techniques, 666 Fourier transform theory, 663–664 free-space propagation, 665 frequencies, 663–664 Helmhotz equation, 663 Rayleigh–Sommerfeld formulation, 663, 666 ANNABELLE system-on-chip average power consumption, 338 heterogeneous, 336–338 partial dynamic reconfiguration, 339 reference locality, 338–339 AODV, see Adhoc on-demand vector (AODV) routing protocol Application programming interfaces (APIs), 531 ASM, see Abstract state machines Aspex Linedancer ASProCore architecture, 340–341 content addressable memory (CAM), 339–340 design methodology, 342 hardware architecture, 341–342, 343 scalable architecture, 340–341 SIMD architectures, 340 B Basic block annotation, 36, 39 pipeline modeling microarchitectures, 40–41 pipeline overlapping, 42–43 reservation tables, 41–42 principles, 39 static cycle calculation, 40 Behavior-interaction-priority (BIP) framework strengths, 300 system specification, 299 Behavior-interaction-priority framework (BIP), 299–300 Behavioral semantics specification, DSMLs abstract state machines (ASM), 463–464 composition, 462 operational and denotational semantics, 463 orthogonality, 462 proportional/integral/derivative (PID) controller, 462 semantic anchoring overview interpretation, 464–465 tool suite, 465 719 Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 720 2009-10-1 720 Index unified model transformation (UMT), 465–466 structural invariants, 462–463 tagged signal model (TSM), 463 timed automata composition, 470–473 operational semantics, 469–470 overview, 466–467 semantic unit abstract data model, 467–469 TASU modeling language, 473–474 TDL modeling language, 475–481 timing definition language (TDL), 474–475 transformational interpretation, 463 BIP, see Behavior-interaction-priority framework Burlirsch-Store methods, 575 C CAAM, see Combined architecture algorithm model CAD, see Computer-aided design Causal methods, continuous execution model, 526 CBS, see Constant bandwidth server CDI, see Continuous domain interface Chatoyant multi-domain simulation device and component models, 647–649 electrical and optoelectronic models CMOS circuits, 652 devices, 651–652 modified nodal analysis (MNA), 650 MOSFET, 652, 653 piecewise modeling, 650 PWL solution, 651 representation and template integration, 650–651 spice vs. PWL models, 652, 654 mechanical models Duncan’s reduction technique, 655 frequency response, 656 global reference system, 657 matrices, 655–656 NODAS and PWL technique, 656–657 ordinary differential equations (ODEs), 652, 654 transient response, 656–657 viscous damping effects, 654 MEM systems 4f optoelectronic link, 666–667 BER vs. frequency, 668–669 Chatoyant analysis, 667–668 CMOS drivers, 668 grating light valve (GLV), 674–679 insertion and crosstalk vs. mechanical tolerancing, 668–669 optical beam steering/alignment system, 668–674 vertical cavity surface emitting laser (VCSEL), 667–668 optical propagation models angular spectrum technique, 663–666 Gaussian models, 657–659 scalar diffractive models, 659–663 simulation issues, 649 system simulation, 646–647 Chopper stabilization (CHS), 706 Client–server programming model, 182–183; see also Distributed system object component CMOS circuits, 652 energy efficiency, 328–329 gate area analysis, 632–633 interface, 623–624 MEM systems, 668 technological specifications, 631 technology, 639 transistor, 603–604 Co-simulation instance, 524 Combined architecture algorithm model (CAAM), 238 Common intermediate code (CIC) programming model architecture information file, 214–215 description, 209 program generation, 211 task code functions, 213 macroblock decoding task functions, 213–214 Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 721 2009-10-1 Index 721 translator generic API translation, 216–217 HW-interfacing code generation, 217 OpenMP translator, 217–218 scheduling code generation, 218–220 workflow, 215–216 Computation tree logic (CTL), 529 Computer generated holograms (CGH), 659 Computer-aided design (CAD) Chatoyant multi-domain simulation device and component models, 647–649 electrical and optoelectronic models, 650–652 mechanical models, 652–657 MEM systems, 666–679 optical propagation models, 657–666 simulation issues, 649 system simulation, 646–647 HDL co-simulation environment architecture, 680–685 design, 679–680 experimental systems, 685–689 multi-domain systems on chips (MDSoCs), 644–645 system simulation, 644–645 Concrete time domain arrival and service functions, 9–10 composition, 12 simple and greedy components, 10–12 Configurable logic block (CLB), 355 Constant bandwidth server (CBS) experiments ball and beam process, 158 CPU schedule, 158–159 implementation, 156–157 updating rules, 156 Continuous domain interface (CDI) flowchart, 540 model, 542 simulation interface, 546 Continuous simulation interfaces (CSI), 551 Continuous time system, 525–526 Continuous-time (CT) dynamics ContinuousStepSizeController interface, 576 Euler methods, 575 first-order differential equations, 573 MATLAB R , 575 opaque composite actor, 576, 577 ordinary differential equations (ODEs), 573 Runge-Kutta (RK) methods, 574–575 third-order nonlinear differential equation, 573–574 Continuous/discrete co-simulation tools advantages, 520–521 applications definition, operational semantics, 536–538 discrete event system specifications (DEVS), 533–534 formalization and verification, 539–546 implementation, 550 integration, 549 simulation interfaces, 546–549 synchronization functionality, 538–539 timed automata, 535–536 CODIS, 552–553 components, 520 continuous simulators, 532, 533 discrete event system specifications (DEVS), 522 execution models continuous, 525–526 discrete, 524–525 global execution model, 523–524 formal representation-based approaches, 522 formalization and verification checking properties, 545 computation tree logic (CTL), 529 continuous simulation interfaces (CSI), 551 discrete simulation interfaces (DSI), 550–551 formal model simulation, 544–545 IContinu, 542–544 IDiscrete, 540–541 linear temporal logic (LTL), 529 Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 722 2009-10-1 722 Index model checking, 528–529 simulation interfaces, 540 synchronization model, 545–546 theorem proving, 529 UPPAAL, advantages, 539–540 hierarchical representation, 530, 546–547 internal architecture, 547 methodology formalization and verification, 528–529 framework, 526–527 generic stage, 527 implementation stage, 527 internal architecture, 530 library elements, 531 operational semantics, 528 simulation tools, 530–531 synchronization functionality, 528 models of computation (MoC), 522 simulation-based approaches, 521–522 stages, 527–528 synchronization model, 531–532 CSI, see Continuous simulation interfaces D DDR, see Dynamic design robustness Deep random search (DRS) algorithm, 406–407 Design refinement converter channels software defined radio (SDR), 597–598 SW-defined radio, 598, 599–600 SystemC code, 598–599 E-AMS systems, 587–588 embedded analog/digital systems methodology, 592–594 methodology-specific library, 596–597 methodology-specific support, 595–596 SystemC AMS extensions, 591–592 Differential and algebraic equation (DAE), 588 Digital signal processor (DSP) algorithms, 344–345 applications, 336 energy efficiency, 328 HW/SW systems, 587, 594 predictable and composable, 327–328 streaming application, 324–325 Digital-clock test generation, 417, 419–420 Diopsis R2DT, Hermes NoC H.264 encoder, 251 illustration, 249 transaction accurate architecture, 253 virtual prototype, 256 Discrete domain interface (DDI) flowchart, 539 model, 541 simulation interface, 546 Discrete event (DE), 646 Discrete event system specifications (DEVS), 522, 533–534 Discrete Fourier transform (DFT), 666 Discrete simulation interfaces (DSI), 550–551 Discrete-event (DE) systems approaches, 568–569 event queue, 571 functions, 570 mixed DE and SR model, 572–573 modal model, 573 setup phase/postfire method, 570–571 Distributed embedded systems analytical approaches black-box, 29 white-box, 30 hybrid approaches, 31–32 simulative approaches binary code translation, 31 drawbacks, 31 instruction set simulator (ISS), 30–31 Distributed platforms, performance prediction concrete time domain arrival and service functions, 9–10 composition, 12 simple and greedy components, 10–12 extensions, 23–24 modular performance analysis, real-time calculus Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 723 2009-10-1 Index 723 abstract components, 15–16 characteristics, 17 compact representation, 19–22 component model, 14–15 greedy shaper component (GSC), 16 modeling scheduling policies, 18 system performance model, 16–17 transfer functions, 15–16 variability characterization curves (VCCs), 13–14 system-level performance analysis analytic techniques, 6 design space exploration cycle, 4–5 distributed embedded platforms, 4 picture-in-picture (PiP) application, 7–9 simulation-based methods, 5–6 Distributed system object component (DSOC), 240–241 Domain-specific modeling languages (DSMLs) behavioral semantics specification composition, 462 operational and denotational semantics, 463 orthogonality, 462 proportional/integral/derivative (PID) controller, 462 semantic anchoring overview, 464–466 structural invariants, 462–463 tagged signal model (TSM), 463 timed automata, 466–481 transformational interpretation, 463 design flow, 439 framework, 442–443 informal and formal specification, 440–442 software development process, 438 structural semantics specification adding domain constraints, 455–458 compositions and domains, 458–461 domains and models, 449–451 expressive constraints, 446–449 logic programming (LP), 444–445 metamodeling language, 443 model contents, 451–455 non-recursive and stratified, 445 operations, 444 signatures and terms, 445 terms with types, 445–446 DSOC, see Distributed system object component DSP, see Digital signal processor Duncan’s reduction technique, 655 Dynamic data flow (DDF), 646 Dynamic design robustness (DDR), 81–82 E Earliest deadline first (EDF) scheduling policy, 95, 111–112 EDK, see Embedded development kit (EDK) designs Electrical and optoelectronic models CMOS circuits, 652 devices, 651–652 modified nodal analysis (MNA), 650 MOSFET, 652, 653 piecewise modeling, 650 PWL solution, 651 representation and template integration, 650–651 spice vs. PWL models, 652, 654 Embedded analog/mixed-signal (E-AMS) systems architecture level, 591–592 communication system, 585–586 open SystemC initiative (OSCI), 587–588 Embedded development kit (EDK) designs Linux design constraints, 361–362 device trees, 362–363 partial reconfiguration abstraction, 365 direct memory access interfaces, 366–368 external interfaces, 368 implementation flow, 369–370 interface architecture, 365–366 Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 724 2009-10-1 724 Index Embedded mixed-signal systems design refinement converter channels, 597–600 E-AMS systems, 587–588 embedded analog/digital systems, 591–597 HW/SW architectures, 586–587 OSCI SystemC-AMS extensions differential and algebraic equation (DAE), 588 linear electrical networks (LEN), 588–589 timed data flow (TDF), 588–591 sensor network serving nodes, 585–586 Euler methods, 526, 575 EvolveTA method, 469–470, 471–472 Execution models, C/D co-simulation tools continuous time system causal methods, 526 Euler method, 526 noncausal methods, 526 state–space equations, 525 discrete system event update schema, 524–525 state–space equations, 524 global execution model backplane, 524 elements, 523 instance, 524 interfaces, 523–524 Extended state machines (ESMs) continuous dynamics, 495–496 definition, 496–497 events and interactions, 495–496 input and outputs, 499 macrostates/locations, 501 openness, 500–501 product, 498 projection, 497–498 receptiveness, 499–500 runs, 497 union/disjunction, 498–499 variables and ports, 495–496 Extreme processing platform (XPP), 343–345 F FAR, see Frame address register Far-field diffraction theory, 675–676 Fiber image guide (FIG), 685, 686, 687–688 Field programmable gate arrays (FPGA) architecture, 373 configuration and reconfiguration, 355–358 context logic, 370 EDK designs Linux, 361–363 partial reconfiguration, 364–370 I/O pins requirements, 374–375 managing partial reconfiguration, 370–372 MIMO system, 337 modular partial reconfiguration, 363–364 platform-based design, 352 PR processors, 358–360 processor-based systems, 353–355 SRP concept, 360–361 system-in-FPGA (SIF) architecture, 352 Virtex 4 FX 100 device, 372–373, 374 Finite state machine (FSM), 449–450 First-in first-out (FIFO) scheduling policy, 110 Fixed priority scheduling (FPS), 110–111 Flip-flops (FFs), 355 Formal modeling using logic analysis (FORMULA), 445, 447, 449 Formal performance analysis application model, 60 compositional system-level analysis loop, 63 event streams, 60–61 hierarchical communication, 69–73 AUTOSAR, 70 event sequence models, 72 hierarchical event streams (HESs), 70–73 modern communication stacks, 69–70 traditional model, 69–70 local component analysis, 62–63 Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 725 2009-10-1 Index 725 MPSoCs deriving aggregate busy time, 68–69 deriving output event models, 65–66 multicore component, 64 response time analysis, 66–68 robustness data quality, 80 dynamic design robustness (DDR), 81–82 evaluation and optimization, 80–81 fault tolerance, 79 maintainability and extensibility, 80 reusability and modularity, 80 static design robustness (SDR), 81 scenario-aware analysis compositional methodology, 75–76 echo effect, 74–75 sensitivity analysis performance characterization, 76–77 performance slack, 77–79 ForSyDe model, 298 Fourier transform (FFT) techniques, 663–664, 666 FPGA, see Field programmable gate arrays FPS, see Fixed priority scheduling Frame address register (FAR), 355–356 FunState model, 300 G Gaussian models, 657–659 Generalized stochastic Petri nets (GSPN), 30 GLV, see Grating light valve (GLV) system Grating light valve (GLV) system component and device, 675 direct integration technique, 676–677 end-to-end link, 677–678 far-field diffraction theory, 675–676 micro-electrical-mechanical (MEM) phase, 674–675 operation, 676 transient analysis, 677 wavelength power vs. distance propagation, 678–679 Greedy processing component (GPC), 11 Greedy shaper component (GSC), 16 Gyroscope, 711, 713, 715–717 H H.264 encoder application and architecture specification, 248–249 system architecture level, 249–250 transaction accurate architecture level, 253–254 virtual architecture level, 250–252 virtual prototype level, 254–256 Hardware description languages (HDLs), 587 HDL co-simulation environment architecture conservative vs. optimistic synchronization, 682–683 runtime environments, 681–682 system generator, 680–681 top-level structure, 680–681 UNIX IPC mechanisms, 683–685 design, 679–680 experimental systems fiber image guide, 685, 686 FIG runtimes, 687–688 smart optical pixel transceiver, 685–687 SPOT runtimes, 688–689 Helmhotz equation, 663 Hermes NoC, Diopsis R2DT H.264 encoder, 251 illustration, 249 transaction accurate architecture, 253 virtual prototype, 256 HESs, see Hierarchical event streams Heterogeneous rich component (HRC) state machines definition, 501–503 labeling functions expressions and differential expressions, 504 guards and actions, 506 invariant, 504 mathematical syntax, 505 . Nicolescu /Model-Based Design for Embedded Systems 67842_C021 Finals Page 716 2009-10-2 716 Model-Based Design for Embedded Systems 270.0 m 220.0 m 190.0 m 120.0. 2006-04123 and I3P scholarship program. Nicolescu /Model-Based Design for Embedded Systems 67842_C021 Finals Page 718 2009-10-2 718 Model-Based Design for Embedded Systems References 1. A. Vachoux, Analog. 365–366 Nicolescu /Model-Based Design for Embedded Systems 67842_C022 Finals Page 724 2009-10-1 724 Index Embedded mixed-signal systems design refinement converter channels, 597–600 E-AMS systems, 587–588 embedded