Model-Based Design for Embedded Systems- P57 pdf

10 261 0
Model-Based Design for Embedded Systems- P57 pdf

Đang tải... (xem toàn văn)

Thông tin tài liệu

Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 536 2009-10-2 536 Model-Based Design for Embedded Systems clock differences. With this transition, the variables are updated by r (reset), which is an action performed on clocks. The actions are used for synchro- nization and are expressed by a (action) [3]. A synchronization label is of the form Expression? or Expression! where ! represents the operator send and ? represents the operator receive. The semantics for a time automaton are defined as “a transition system where a state or configuration consists of the current location and the current values of clocks” [3]. Thus, the state is represented by the tuple: (l, v) where l is the location and v is the clock valuation (a function that associates a real positive value, including zero, to each clock). Given the system, we can have two types of transitions between locations: a delay transition when the automaton may delay for some time or an action transition when the transition follows an enabled transition. The transition showing the time passing is (l, v) t −→ (l  , v  ) if and only if: ⎧ ⎨ ⎩ v  = v + t ∀t  ∈[0, t], (v +t  ) verifies Inv(l) (16.4) where Inv(l) is the invariant in the location l, l = l  , v  = v +t showing that for all clocks x, v  (x) = v(x) +t. For the discrete transitions (p, v) g;a;r −→ (q, v  ) v  has to satisfy the invariant of q. v  is obtained from v by resetting the clocks indicated by the reset r. Timed automata have the following characteristics that make them desir- able for our formal model: • The ease and the flexibility of systems’ modeling • The existence of a whole range of powerful tools that are alreadyimple- mented and that allow different verification techniques • The adequate expressivity in order to model time constrained concur- rent systems Our formal model needs to support concurrency between continuous/dis- crete systems and thus it was represented as a parallel composition of several timed automata with no constraints regarding the time spent in the locations. 16.6.3 Definition of the Operational Semantics for the Synchronization in C/D Global Execution Models The operational semantics for the C/D synchronization model is given by the set of rules presented in Table 16.1. DEVS, as defined in Section 16.7.1 allows for the definition of the operational semantics of the behavior of the simulation interfaces with respect to the synchronization model presented in Section 16.5. In Table 16.1, DataToBus is the output function from the discrete domain interface λ(s d ),andDataFromBus is the output function from the continuous Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 537 2009-10-2 Generic Methodology for the Design 537 TABLE 16.1 Operational Semantics for the C/D Synchronization Model Rule Arrows in Figure 16.5 synch =1 ∧flag = 1 ∧q = δ ext (q) (s d , e d ) !(DataFromBus,t a (s d ));flag:=0 −−−−−−−−−−−−−−−−−−→ (s d , e d ); q ?(DataFromBus,t a (s d ));synch:=0 −−−−−−−−−−−−−−−−−−−→ q Arrow 1 Figure 16.5a and b flag = 0 ∧¬stateevent(t) ∧ q  = δ int (q) q δ int −→ q  !DataToBus;flag:=1 −−−−−−−−−−−→ q  Arrow 2 and 3 in Figure 16.5a synch = 0 ∧flag = 1¬stateevent ∧s  d = δ ext (s d ) (s d , e d ) t a (s d )−e d −−−−−→ (s d , t a (s d )) ?DataToBus;δ int (s  d );λ(s  d );synch:=1 −−−−−−−−−−−−−−−−−−−−−−→ (s  d ,0) Arrow 4 in Figure 16.5a flag = 1 ∧stateevent ∧q  = δ int (q) q !DataToBus −−−−−−→ q  !DataToBus;!t se ;flag:=1 −−−−−−−−−−−−−→ q  Arrow 2 and 3 in Figure 16.5b synch = 0 ∧flag = 1 ∧ stateevent ∧ s  d = δ ext (s d, t) (s d , e d ) ?t se −→ (s d , t se ) ?DataToBus;δ int (s  d );λ(s  d );synch:=1 −−−−−−−−−−−−−−−−−−−−−−→ (s  d ,0) Arrow 4 in Figure 16.5b Source: Gheorghe, L. et al., Formal definition of simulation interfaces in a continuous/discrete co-simulation tool, Proceedings of the 17th IEEE International Workshop on RSP, Chania, Crete, Greece, pp. 186–192, 2006. With permission. Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 538 2009-10-2 538 Model-Based Design for Embedded Systems domain interface λ(s d ). The semantics of the global variable “flag” is related to the context switch between the continuous and discrete simulators. When “flag” is set to “1,” the discrete simulator is executed. When it is “0,” the con- tinuous simulator is executed. The global variable “synch” is used to impose the order of the different operations expressed by the rules. For a better explanation, we present the first rule in more detail here, corresponding to arrow 1 in Figure 16.5a and b. The premises of this rule are: the “synch” variable has value “1,” the “flag” variable has value “1,” and we have an external transition function (δ ext ) for the continuous model. The discrete model is initially in the total state (s d , e d ), this means it has been in the state s d for the time e d . In this state, the discrete simulator performs the following actions: send the data and the value of its next time stamp (this action is expressed by !(DataFromBus, t a (s d )) • Switch the simulation context to the continuous model (this action is expressed by flag =0). For the same rule, the continuous model is in state q and performs the following actions: • Receive the data and the value of the time stamp from the discrete sim- ulator (expressed by?((DataFromBus, t a (s d )). • Set the global variable synch to “0” (action expressed by synch =0)in order to respect the premise of the rule corresponding to the arrow 4. The actions expressed by this rule will be executed by the discrete simulator when the context will be switched to it [12]. 16.6.4 Distribution of the Synchronization Functionality to the Simulation Interfaces The second step of the methodology consists in the distribution of the syn- chronization functionality to the simulation interfaces. The synchronization functionality was presented in Section 16.4.2. The behavior of the discrete domain interface can be described by a few processing steps detailed in Figure 16.7. The interface is in charge of: • Exchanging data between the simulators (send/receive) • Sending the time stamps of the next events • Considering the state events • The context switch to the continuous interface The behavior of the continuous domain interface can also be described by a few processing steps detailed in Figure 16.8. This interface handles: Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 539 2009-10-2 Generic Methodology for the Design 539 Start () From discrete event simulator To co-simulation bus To co-simulation bus StateventStatevent - Send time of next event to co- simulation bus Wait event from the continuous sim. - Get data from the co-simulation bus - Send data to the discrete event simulator Wait data from the continuous simulator Wait data from the continuous simulator Stop Stop - Get time of state event from the co-simulation bus - Activate state event detection module - Get data from the co-simulation bus - Send data to the discrete event simulator To discrete event simulator - Detection of the end of discrete simulation cycle - Get data from the discrete event simulator - Send data to co-simulation bus FIGURE 16.7 Flowchart for the discrete domain interface. (From Gheorghe,L. et al., Formal definition of simulation interfaces in a continuous/discrete co-simulation tool, Proceedings of the 17th IEEE International Workshop on RSP, Chania, Crete, Greece, pp. 186–192, 2006. With permission.) • Exchanging data between the simulators (send/receive) • Sending the time stamps of the following events • The indication (to the discrete interface) of the occurrence of a state event • The context switch to the discrete interface 16.6.5 Formalization and Verification of the Simulation Interfaces Behavior This section presents details of the formalization and the formal verifi- cation of the behavior of the simulation interfaces using, as explained in Section 16.4, timed automata and TCTL. In order to model, validate, and check our model we used UPPAAL [2]. The main advantage of UPPAAL is Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 540 2009-10-2 540 Model-Based Design for Embedded Systems To continuous simulator From continuous simulator - Activate state event detection module - Send time of state event to the co-simulation bus - Send data from the continuous simulator to the co-simulation bus To co-simulation bus Start () Yes No To co-simulation bus Stop Stop - Get data from the co-simulation bus - Send data to the continuous simulator - Send time of next event to the continuous simulator - Get data from the continuous simulator - Was a state event detected - Send data from the continuous simulator to the co-simulation bus - Wait data from the discrete simulator - Wait data from the discrete simulator FIGURE 16.8 Flowchart for the continuous domain interface. (From Gheorghe, L. et al., Formal definition of simulation interfaces in a continuous/discrete co- simulation tool, Proceedings of the 17th IEEE International Workshop on RSP, Chania, Crete, Greece, pp. 186–192, 2006. With permission.) that the product automaton is computed on-the-fly during verification. This reduces the computation time and the required memory space. It also allows interleaving of actions as well as hand-shake synchronization. The tool pro- vides a user-friendly graphical interface and a simulator. 1. Formalization of the simulation interfaces: In [14] the authors demonstrate the equivalence between a DEVS model and the timed automata. The timed-automata model completes the DEVS graph with the addition of the timing evolution notions. Figure 16.9 shows the formal model for the discrete domain interface using timed automata. The model has only one initial location (marked in Figure 16.9 by a double circle) Start. The discrete interface will change location from Start to NextTimeGot following the transition Start DataFromDisc? −−−−−−−→ NextTimeGot. This is an external Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 541 2009-10-2 Generic Methodology for the Design 541 WaitDataFromContStart TimeOfStEvDisc DataToDisc!td = NextTime DataToBus? StEvDetect StateEvent NextTime = StEvTime NextTimeGot DataToBus? DataFromDisc? DataFromBus! NextTime = cycle WaitEvent EventGot Event? Cycle : int(0, period) NoStEv StateEvent == 0 U U FIGURE 16.9 The discrete domain interface model (IDiscrete). transition realized in zero time and it is triggered by receiving the data (that is also synchronization between the discrete simulator and the interface) from the discrete simulator (DataFromDisc?). Here the interface receives the data from the discrete simulator and the time of the next event in the discrete domain. The location changes to WaitEvent following the transition: NextTimeGot DataFromBus!, NextTime =cycle,cycle:int[0,period] −−−−−−−−−−−−−−−−−−−−−−−−−−−−→ WaitEvent In order to change the location, the continuous interface sends the time of the next event (occurred/scheduled event) in discrete (the synchronization DataFromBus!) to the discrete interface. The variable NextTime is the time of the next event in the discrete domain. This variable takes, in this mode, the value cycle. The theory normally assumes equidistant sampling intervals. This assumption is not usually achieved in practice. For an accurate simula- tion we assume that cycle takes random values in an interval defined here as [0, period]. In WaitEvent location, the context is switched from the discrete to the continuous simulator. When the context is switched back to the discrete simulator, the location is changed to EventGot following the synchronization transition: WaitEvent Event? −−→ EventGot. During this transition the discrete interface receives from the continuous interface the synchronization Event?. In this location the occurrence of a state event in the continuous domain is consid- ered. EventGot is an urgent location (as defined in Section 16.6.2). This will not allow the discrete model to miss a state event generated by the continu- ous model. Two cases are possible: • When no state event was generated by the continuous domain, the location changes from EventGot to NoStEv. The transition Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 542 2009-10-2 542 Model-Based Design for Embedded Systems EventGot StateEvent ==0 −−−−−−−−→ NoStEvis annotated in this case only with the guard StateEvent==0. • When a state event was generated by the continuous domain the loca- tion changes from EventGot to StEvDetect following the transition: EventGot StateEvent,NextTime=StEvTime −−−−−−−−−−−−−−−−−→ StEvDetect. This transition is annotated with a guard (StateEvent) and the update of the NextTime in the discrete domain as the time when the state event occurred in the continuous domain StEvTime (for a rigorous synchroniza- tion, the discrete domain has to consume this event and stop at the time when it was generated by the continuous domain interface). This is the time of the next event that is going to be sent to the continuous simula- tor. From both locations StEvDetect and NoStEv, the system can reach the next location: TimeOfStEvDisc. In both cases the model performs synchro- nization (DataToBus?). At this point the discrete interface will synchro- nize and send data to the discrete simulator (DataToDisc) and changes the location to WaitDataFromCont. The next location is Start, the discrete time variables is initialized on this channel (td=NextTime)and the cycle restarts. Figure 16.10 shows the formal model (using timed automata) for the continuous domain interface. The model also has only one initial location (marked in Figure 16.10 by a double circle) Start. U U WaitDataFromDisc Start tc = tcn DataFromBus? DataFromCont? Event! tse : int(0, period) StateEvent = 1 StEvTime = (tse < tcn)? tse : tcn tcn = StEvTime ReceiveDataFromBus DataToCont! tcn = NextTime ReceiveDataFromCont SendDataToCont DataToBus! Event! StateEvent = 0 TimeOfStEv StEvDetect FIGURE 16.10 The continuous domain interface model (IContinu). Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 543 2009-10-2 Generic Methodology for the Design 543 The continuous interface will leave the initial location Start following the transition: Start DataFromBus? −−−−−−−→ ReceiveDataFromBus. This is also an external transition realized with zero time and it is triggered by the reception of the data from the discrete interface (DataFromBus?) that is also the first synchronization point between the discrete interface and the continuous interface. The inter- face receives the data from the discrete simulator and the time of the next event in the discrete model. From the ReceiveDataFromBus location the pro- cess moves to the next location SendDataToCont following the transition ReceiveDataFromBus DataToCont!, ten =NextTime −−−−−−−−−−−−−−−→ SendDataToCont The value NextTime, the time of the next event (occurred/scheduled event) in the discrete simulator is assigned to tcn, the next time in the con- tinuous simulator. In our model, the synchronization on this transition is between IContinu and SimCont (where SimCont is the continuous domain simulator), the interface sends data received from IDiscrete and the time of the next event in the discrete domain to the simulator. The system changes the location from SendDataToCont to Receive- DataFromCont following the synchronization transition: SendDataToCont DataFromCont? −−−−−−−−→ ReceiveDataFromCont. During this transition the continuous interface receives data from the continuous simulator and, if a state event occurred, the time of the state event. In the ReceiveDataFromCont location, the continuous interface evaluates if a state event was generated. Two cases are possible: • When no state event is generated, the location changes from Receive- DataFromCont to TimeOfStEv following the transition ReceiveDataFromCont Event!StateEvent =0 −−−−−−−−−−→ TimeOfStEv. The transition is annotated in this case by the synchronization Event! and with the update StateEvent =0. • When a state event is generated, the location changes from Receive- DataFromCont to StEvDetect following the transition: ReceiveDataFromCont Event!StateEvent=1,StEvTime=(tse<tcn)?tse:tcn,tse:int[0,period] −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−→StEvDetect This transition is annotated with a synchronization (Event!) and three variable updates: StateEvent=1 (for the detection of a state event), StEvTime=(tse<tcn)? tse:tcn, tse:int[0,period] (for the time of the state event that occurs during the time interval [0, period]; this time will be sent to the discrete simulator). StEvDetect is an urgent location. The location StEvDetect changes to TimeOfStEv following the transition StEvDetect tcn =StEvTime −−−−−−−→ TimeOfStEv. At this point there is no synchronization, only an update of the time in the continuous domain having assigned the time of the state event StEvTime: tcn=StEvTime. Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 544 2009-10-2 544 Model-Based Design for Embedded Systems TimeOfStEv location is common for both cases, StateEvent=0 or StateEvent=1. This location changes to WaitDataFromDisc. The system performs synchronization (DataToBus!) between the continuous interface and the continuous simulator. The next location is Start, the continuous time variables is initialized on this channel (tc=tcn) and the cycle restarts. 2. Formal model simulation: The UPPAAL tool allows the validation of the system’s expected behavior regarding functionality: synchronization, conflicts, and communication. We simulated all the possible dynamic executions of our model. Figure 16.11 shows a screenshot with the simulator. We observe that the left panel is the simulation control window. It highlights the enabled transi- tion as well as the symbolic traces. The middle panel shows the variables. It displays the values of the data and clock variables in the current location or transition selected in the trace of the simulation control panel (the symbolic traces). The right panel allows the visualization of the message sequence chart (also known as simulator). The vertical lines in the simulator window in Figure 16.11 represent the transitions between the locations while the horizontal lines are the synchro- nization points. In this figure, the communication between the interfaces as well as the communication between the simulators and the domain specific interfaces is represented by the same horizontal lines. As shown here, the simulation was stopped by the user after the detection of a state event in the continuous domain. The state event was indicated to the discrete simulator FIGURE 16.11 Formal model simulation screen capture. Nicolescu/Model-Based Design for Embedded Systems 67842_C016 Finals Page 545 2009-10-2 Generic Methodology for the Design 545 and the time of the state event (StEvTime) is to be sent from the contin- uous to the discrete interface. The variable panel shows that the variable StateEvent=1, the time of the state event StEvTime=2, and the NextTime=10. The discrete simulator, instead of advancing the time to 10, will advance only to StEvTime. 3. Formal verification: The formal verification consists of checking prop- erties of the system for a broad class of inputs [25]. In our work, we checked properties that fall into three classes: • Safety properties—the system does not reach an undesirable con- figuration, (e.g., deadlock) [9]. • Liveness properties—some desired configuration will be visited eventually or infinitely (e.g., expected response to an input) [9]. • Reachability properties—the system always has the possibility of reaching a given situation (some particular situation can be reached) [25]. The properties verified in order to validate the synchronization model are described below. P0 Absence of deadlock (safety property) Deadlock exists among a set of processes if every process waits for an event that can be caused only by another process in the set. In UPPAAL, deadlock is expressed by a formula using the keyword deadlock.Astate is a deadlock state if there are no outgoing action transitions either from the state itself or any of its delay successors [36]. P1 State event detected by the discrete domain (liveness property) The indication of a state event by the continuous interface and its detec- tion by the discrete interface is very important for continuous/discrete het- erogeneous systems. We defined a liveness property in order to check this behavior that is stated as follows: Definition: A state event detected in the continuous domain leads to a state event detected in the discrete. P2 No state event in discrete if no state event in continuous domain (safety property) In order to avoid false responses from the discrete simulators, we defined a safety property to verify if the system will “detect” a state event in the dis- crete simulator when it was not generated (and indicated) by the continuous domain: Definition: Invariantly a state event detected in the discrete domain imply state event in the continuous. P3 Synchronization between the interfaces (reachability property) One of the most important properties characterizing the interaction between the continuous and the discrete domains is the communication and . StEvTime: tcn=StEvTime. Nicolescu /Model-Based Design for Embedded Systems 67842_C016 Finals Page 544 2009-10-2 544 Model-Based Design for Embedded Systems TimeOfStEv location is common for both cases, StateEvent=0. pp. 186–192, 2006. With permission. Nicolescu /Model-Based Design for Embedded Systems 67842_C016 Finals Page 538 2009-10-2 538 Model-Based Design for Embedded Systems domain interface λ(s d ). The. [2]. The main advantage of UPPAAL is Nicolescu /Model-Based Design for Embedded Systems 67842_C016 Finals Page 540 2009-10-2 540 Model-Based Design for Embedded Systems To continuous simulator From

Ngày đăng: 03/07/2014, 17:21

Từ khóa liên quan

Mục lục

  • Contents

  • Preface

  • Introduction

  • Contributors

  • Part I: Real-Time and Performance Analysis in Heterogeneous Embedded Systems

    • Chapter 1. Performance Prediction of Distributed Platforms

    • Chapter 2. SystemC-Based Performance Analysis of Embedded Systems

    • Chapter 3. Formal Performance Analysis for Real-Time Heterogeneous Embedded Systems

    • Chapter 4. Model-Based Framework for Schedulability Analysis Using UPPAAL 4.1

    • Chapter 5. Modeling and Analysis Framework for Embedded Systems

    • Chapter 6. TrueTime: Simulation Tool for Performance Analysis of Real-Time Embedded Systems

    • Part II: Design Tools and Methodology for Multiprocessor System-on-Chip

      • Chapter 7. MPSoC Platform Mapping Tools for Data-Dominated Applications

      • Chapter 8. Retargetable, Embedded Software Design Methodology for Multiprocessor-Embedded Systems

      • Chapter 9. Programmig Models for MPSoC

      • Chapter 10. Platform-Based Design and Frameworks: Meteropolis and Metro II

      • Chapter 11. Reconfigurable Multicore Architectures for Streaming Applications

      • Chapter 12. FPGA Platforms for Embedded Systems

      • Part III: Design Tools and Methodology for Multidomain Embedded Systems

        • Chapter 13. Modeling, Verification, and Testing Using Timed and Hybrid Automata

        • Chapter 14. Semantics of Domain-Specific Modeling Languages

        • Chapter 15. Multi-Viewpoint State Machines for Rich Component Models

        • Chapter 16. Generic Methodology for the Design of Continuous/Discrete Co-Simulation Tools

Tài liệu cùng người dùng

  • Đang cập nhật ...

Tài liệu liên quan