Hardware and Computer Organization- P12 pptx

Chapter 11 312 value in that field may produce unpredictable results. 1 Another feature of the compare instructions is that they will always set the flags, so the state of the S bit is ignored. The next group of data processing instructions is the very powerful set of multiplication instruc- tions. There are size multiplication instructions, as shown in the following table: Mnemonic Description Syntax MUL Multiply two 32-bit numbers, produce a 32-bit result: Rd = Rm * Rs MUL{cond}{S} Rd, Rm, Rn MLA Multiply two 32-bit numbers, and add 3 rd number for a 32-bit result: Rd = Rn + (Rm * Rs) MLA{cond}{S} Rd, Rm, Rn, Rs UMULL Multiply two unsigned 32-bit numbers, produce an unsigned 64-bit resulted in two registers: [RdHi][RdLo] = Rm * Rs UMULL{cond}{S} RdLo,RdHi,Rm,Rs UMLAL Multiply two unsigned 32-bit numbers and add an unsigned 64-bit number in two registers to produce an unsigned 64-bit resulted in two registers: [RdHi][RdLo] = [RdHi][RdLo] + Rm * Rs UMLAL{cond}{S} RdLo,RdHi,Rm,Rs SMULL Multiply two signed 32-bit numbers, pro- duce a signed 64-bit result in two registers SMULL{cond}{S} RdLo,RdHi,Rm,Rs SMLAL Multiply two signed 32-bit numbers and add a signed 64-bit number in two regis- ters to produce a signed 64-bit resulted in two registers: [RdHi][RdLo] = [RdHi][RdLo] + Rm * Rs SMLAL{cond}{S} RdLo,RdHi,Rm,Rs As a class of instructions, the multiple instructions also take longer than one cycle to execute. Finally, it may surprise you that the ARM instruction set does not contain any division instruc- tions. Sloss et al 7 describe approximation methods that may be used to convert division operations to multiplications. 2. Load/Store Instructions All data transfers between registers and memory use the load and store class of instructions. All memory addresses are generated using a base register pointer, summed with an additional immediate offset value, register values or scaled register values. In addition, the calculated memory address pointer may be used without updating the base register pointer with the new address value. Finally, the address calculation may take place before or after the address is used in the instruction. The load/store operations must also deal with the size and type of the operands, since bytes and half-words are also permitted. 1 There’s a wonderful story about the intrepid hobbyists/pioneers of the PC industry. It became sort of a cottage indus- try to try to figure out what the unimplemented op-codes did. In other words, “What would happen if the SBZ field was set to 011?” Sometimes some very interesting undocumented instructions were discovered and were actually designed into commercial products. Unfortunately, when the CPU manufacturer revised the chip, they often changed the codes for unsupported instruction codes, figuring, “Who would use them?” You can imagine the uproar when products started failing when a new batch of processors was plugged in. The ARM Architecture 313 Since we’ve already discussed much of the operation of the load/store instructions as part of our discussion of the addressing modes that they use, we’ll just take a brief look at the format of the load/store instruction word. The load register instruction may take any of the following forms: Mnemonic Description Syntax LDR Load a register from a 32-bit memory word LDR{cond} Rn,<address mode> LDRB Load a register from an 8-bit memory byte LDRB{cond} Rn,<address mode> LDRH Load a register from an 16-bit memory half-word LDRH{cond} Rn,<address mode> LDRSB Load a register from an 8-bit signed memory byte LDRSB{cond} Rn,<address mode> LDRSH Load a register from a 16-bit signed memory half-word LDRSH{cond} Rn,<address mode> Special mnemonics must be used for the signed byte and half-word data types because these val- ues are sign extended to 32-bits when the register is loaded from memory. No special instruction is necessary for a 32-bit value in memory because it is the native data size of the ARM architecture. Figure 11.7 shows the format for the load/store instructions for word or unsigned bytes. Note that the load and stores are almost identical, the dif- ference being the state of the L bit in bit position 20. The instruction format is slightly different for half-words and signed bytes. The meanings of the common fields are as follows: • Bits 31:28: Conditional execution fields. • Bits 27:25: Fixed. • Bit 24: For pre-index mode, P = 1. The offset is applied to the base register and the sum of the base register and the offset is used as the memory load/store address. For post-index mode P = 0. The base register is used as the memory pointer and then the sum of the offset and base register value is written back to the base register. • Bit 23: The When U = 1 the offset is added to the base register value to form the memory address. If U = 0 the offset is subtracted from the base register value. • Bit 22: When B = 1 the memory access is an unsigned byte. If B = 0 the access is a 32-bit word. • Bit 21: If the P bit = 1, then the W bit determines if the calculated memory address value is written back to update the base register. If W = 0 the base register is not updated. When the P bit = 0 and W = 1 the current access is treated as a user mode access. When the P bit = 0 and W = 0 then it is treated as a normal memory access. Figure 11.7: Format for the ARM word or unsigned byte load/store instructions. Immediate offset/Index COND 0 1 0 P U B W L Rn Rd 12-bit offset Register offset/Index COND 0 1 1 P U B W L Rn Rd 0 0 0 0 0 0 0 0 Rm Scaled register offset/Index COND 0 1 1 P U B W L Rn Rd Immediate Shift Shift 0 Rm 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chapter 11 314 • Bit 20: If L = 1 then the operation is a memory load. If L = 0 then it is a memory store operation. • Bits 19:16: Base register pointer. • Bits 15:12: Destination register for load operation or source register for store operation. • Bits 11:0: Addressing mode dependent. Let’s look at some examples of memory load and store operations. Instruction Description Instruction code LDR r5,[r8] Load r5 with the word pointed to by r8 0xE5985000 LDRSH r6, [r0, -r2 ]! Load register r5 with the signed half-word pointed to by r0 – r2. Update r0 with com- puted address value after the memory load operation. 0xE13060F2 LDRNE r0,[r9,#-12] Conditionally execute if the Zero Flag = 0. Load register r0 with the word value pointed to by register r3 minus 12 bytes. The value in r9 is not changed. 0x1519000C LDRVCB r11,[r4],r2,LSL #4 Conditionally execute if the Overflow Flag = 0. Load register r11 with the unsigned byte pointed to by r4. Then update r4 so that r4 = r4 + r2*16 0x76D4B202 LDR R8,[PC,r5] Load register r8 with the word value pointed to by the sum of the current value of the program counter (r15) and r5. 0xE79F8005 STRB r7,[r3,#0xAA]! Store an unsigned byte from register r7 to the memory location pointed to by the sum of r3 + 0xAA. Write back the sum to register r3. 0xE5E370AA STRCCH r11,[r2,#-&A] Conditionally execute if the Carry Flag = 0. Store the half-word in register r11 in the memory location pointed to by r2 – 10. r2 is unchanged. 0x3142B0BA STREQ r0,[r4,r5,lsr #7] Conditionally execute if the Zero Flag = 1. Store the word in r0 to the memory address pointed to by r4 + the result of r5 shifted right 7 bit positions. r5 is unchanged. 0x078403A5 STRB r6,[r4],r3 Store the byte in register r6 to the memory address pointed to by r4. Then add the con- tents of r3 to r4 and update r4 with the sum. 0xE6C46003 STRPLH r11,[r9,#-2]! Conditionally execute if the Negative Flag = 0. Store the half word contents of r11 to the memory address pointed to by r9 – 2. Update r9 with the new address. 0x5169B0B2 The above table should give you a sense of the syntax for the various forms of the single item data transfer instructions work and how they are coded in a single 32-bit instruction. Let’s now look at several forms of the load and store operations for multiple data items. The ARM Architecture 315 The general form of the load multiple registers and store multiple registers is shown in Figure 11.8. Each bit in the bit field 15:0 corresponds to a register to be loaded or stored. A 1 in the bit position indicates that the corresponding register is to be loaded or stored. The lowest numbered register is stored at the low - est memory address and the highest numbered register is stored at the highest memory address. The definition of the bit fields is as follows: • Bits 31:28: Conditional execution fields. • Bits 27:25: Fixed • Bit 24: When P = 1 the address is incremented or decremented prior to the memory access (pre-indexing). When P = 0 the current memory pointer address is used first, and then the memory pointer is changed (post-indexing). • Bit 23: When U = 1 the memory addresses are incremented with each transfer. When U = 0 the memory addresses are decremented. • Bit 22: When S = 1 and the LDM instruction is loading the program counter (r15), then the current program status register (CPSR) will be loaded from the saved program status register (SPSR). If the load operation does not involve r15 and for all STM instructions, the S bit indicates that when the processor is in privileged mode, the standard user mode registers are transferred and not the registers of the current mode. The state of the S bit is set by appending the up-carat symbol, ‘^’, to the end of the instruction. • Bit 21: If W=1, the pointer register will be permanently updated after the multiple regis- ter transfer occurs. Since each data transfer is 4 bytes long, the memory pointer will be updates by 4 times the number of registers transferred. If W = 0, the register will not be updated. • Bit 20: If L = 1 then a memory to register (load) operation will take place. If L = 0 then a register to memory (store) operation will occur. • Bits 19:16: Denotes the pointer register. • Bits 15:0: Register list. The general syntax of the load multiple or store multiple instructions is shown below. The terms in braces are optional. LDM or STM{Condition}XY Rn{!}, <register list>{^} Here, XY represents: • IA: Increment After • IB: Increment Before • DA: Decrement After • DB: Decrement Before The following are two representative forms of the load and store multiple instructions. Figure 11.8: Format for the ARM multiple register load/store operation. COND 1 0 0 P U S W L Rn Register List 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chapter 11 316 Instruction Description Instruction code LDMDB SP!,{r0-r3,r5,r7-r9} Load the registers r0,r1,r2,r3,r5,r7,r8 and r9 from the block of memory pointed to by stack pointer (SP) register r13. Load register r8 first from the ad- dress SP-4 and continue to decrement SP until r0 is loaded. Update the SP with the address of the last memory word loaded into register r0. 0xE93D03AF STMNEIA r0,{r2-r9} Conditionally execute this instruction if the Zero Flag = 0. Store the contents of registers r2 through r9 in the block of memory pointed to by r0. Store register r2 and then increment r0 for the next store operation. After the multiple data transfer is completed the value of r0 is restored to its previous value. 0x188003FC The swap instruction (SWP) is a special type of load store operation. It is designed to swap the contents of memory location with the contents of a register. Now, you might argue that this is a nice instruction to have, but it doesn’t quite fit into our streamlined model of a computer’s instruction set architecture. For example, couldn’t you use a traditional algorithm to exchange the contents of memory and a register? For example, suppose we want to exchange the contents of r0 with the contents of the memory location pointed to by r10: MOV r8,r0 ;Move r0 to a temporary register LDR r0,[r10] ;Get memory, ½ of the swap done STR r8,[r10] ;Save r8, swap completed The corresponding form of the swap instruction is: SWP r0, r0, [r10] ;Exchange <r10> with r0 The general form of the swap instruction is: SWP{B}{Condition} Rd,Rm,[Rn] Where register Rd is loaded from the memory location pointed to by Rn and the contents of the memory is overwritten by the value in Rm. Thus, in the general case, the exchange can be between two registers and a single memory location. The question still remains, “Why have the swap instruction at all?” The answer is that the swap instruction is an atomic operation. An atomic operation cannot be interrupted. Most instructions are atomic. That is, once an instruction starts and the processor receives an external interrupt, the instruction must complete before the interrupt can be taken care of. In the above example of the memory to register exchange operation, we need to use 3 instructions to complete the data trans - fer. These 3 instructions are not atomic because an interrupt could cause a gap to occur in the exchange of data. If the interrupt also changed the data in these registers or memory, then the data exchange might become corrupted. The swap instruction is a way to lock the bus so that it must complete before another event can take control. The ARM Architecture 317 3. Branch Instructions There are two forms of the branch instruction; branch (B) and branch with link (BL). The instruc- tions are similar with the exception that the branch with link instruction automatically saves the address of the next instruction after the BL instruction in the link register, r14. This is just a sub - routine call. To return from the subroutine, you just copy the link register to the program counter: MOV PC, LR. The range of the branch in- struction is +/- 32 megabytes. Just like the 68K, the branch instruction in the ARM archi - tecture is a pc-relative displacement. The displacement is added or subtracted from the current value of the pc and the pc is reloaded with this new value, causing a program branch to occur. The form of the branch instruction is shown in Figure 11.9. The branch address is calculated as follows: 1. The 24 bit offset value is sign-extended to 32 bits. 2. The result is shifted left by 2 bit positions (multiplied by 4) to provide a word-aligned displacement value, or effectively, a 26-bit word address. 3. The displacement is added to the program counter and the result is stored back into the pc. 4. Software Interrupt Instructions The software interrupt instruction is designed to allow application code to change the program execution context through a vector stored in memory. This instruction is similar to the TRAP instruction of the 68K and the INT instruction of the 8086. In general, the software interrupt (SWI) is used by an application to make a call to operating system services. Since the SWI instruction is used to change context, it must also save the current processor context so that it can return after the interrupt. The action of the SWI is as follows: 1. Save the address of the instruction after the SWI instruction in register r14_svc. 2. Save the CPSR in SPSR_svc. Enter supervisor mode and disable the normal interrupts, but not the fast interrupt request. 3. Load the PC with address 0x00000008 and execute the instruction there. Rather than use the exception vector table as an indirect address to the start of the software inter - rupt service routine, the vector table location contains space for one instruction, which is then used as a branch to the start of the code. This may seem strange if you think about the 68K’s vector table organization, but with the ARM architecture it really doesn’t matter. Since all instructions are one word long, you don’t need to use an indirect pointer to get to the start of the ISR code. Motorola must use a vector because an unconditional jump instruction would take up too much space. How- ever, since an ARM instruction fits into the same space as an address, either method would work. The software interrupt instruction also contains a 24-bit immediate operand field that may be used to pass parameters to the interrupt service routine. Thus, instead of using multiple software interrupt vectors, a single vector is used, but information about the type of interrupt service being requested can be passed in the operand field of the instruction. Figure 11.9: Format for the ARM branch and branch with link instructions COND 1 0 1 L 24-bit offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chapter 11 318 5. Program Status Register Instructions The last ARM instruction category that will look at contains two instructions that implement a load or store operation between the CPSR or SPSR registers and the general purpose registers. The syntax for the instructions is as follows: MRS{condition} Rd, <cpsr or spsr> MSR{condition} <cpsr or spsr>_<fields>, Rm MSR{condition} <cpsr or spsr>_<fields>, #Immediate The MRS instruction moves the current value of the CPSR or SPSR to a general purpose register. The MSR instruction moves the contents of a general purpose register or an immediate value into the CPSR or SPSR. Some comments on the status register instructions. This instruction will be ignored if the proces - sor is in user mode and the instruction attempts to modify any other field besides the Flag Field. It must be in one of the privileged modes for this instruction to be executable because the program status registers may only be modified when the processor is in one of the privileged modes. The values for the field variables are as follows: • _C: The Control Field represents bits 0 through 7 of the program status register. This is further subdivided as: – Bits 0:4: Processor mode – Bit 5: Enable Thumb Mode – Bit 6: Enable Fast Interrupt Request Mode – Bit 7: Enable Interrupt Request Mode • _X: The Extension Field represents bits 8:15. Currently this field is not used, but is re- served by ARM for future expansion. These bits should not be modified. • _S: The Status Field represents bits 16:23. Currently this field is not used, but is reserved by ARM for future expansion. These bits should not be modified. • _F: The flag field represents bits 24:31. This field is further subdivided as: – Bit 28: V bit- Overflow Flag – Bit 29: C bit- Carry Flag – Bit 30: Z bit- Zero Flag – Bit 31: N bit- Negative Flag The immediate operand can only modify the bits in the Flag Field. Also, in order not to inadver - tently modify bits in the program status register that should not be modified, the program status register should be modified using the following three steps: 1. Copy the contents of the PSR into a general purpose register using the MRS instruction, 2. Modify the appropriate bits in the general purpose register, 3. Copy the general purpose register back into the PSR using the MSR instruction. The following instruction sequence enables the FIR mode. MRS r6, c_spsr ;Copy the spsr to r6 MOV r7, #&40 ;Set bit 6 to 1 ORR r6,r7,r6 ;Set the bit MSR c_spsr, r6 ;Reload the register The ARM Architecture 319 The field bits are logically OR’ed together, so that, for example, you may use cxsf_cpsr to modify all the fields of the cpsr. The formats of the MSR and MRS instructions are shown in Figure 11.10. If the R bit = 1 the program status register used is the SPSR, if R = 0 the program status register is the CPSR register. The immediate filed is rotated by the rotate field value to move the bits to the Flag bits position of the PSR. ARM System Vectors The system vectors for the ARM architecture are rather sparse, compared to the 68K and 8086 architectures. There are a total of 8 system vec - tors, shown in the following table: The Fast Interrupt Request vector is the last vector in the table for a reason that may not be so obvious. Recall that each vector is a 32-bit word, capable of holding just one instruction. That instruction will generally be a branch instruction to the starting point of the user’s service routine. The FIR vector sits at the top of the table so that the FIR service routine can begin at address 0x0000001C and continue on from there, without the need to add a branch instruction to get to the real code. If you want to be fast, every clock cycle counts! The Prefetch Abort vector is used when the processor attempts to fetch an instruction from an address without having the correct permissions to access that instruction. It is called a pre-fetch abort because the actual instruction decoding takes place after the instruction is fetched, but the exception actually occurs during the prefetching of the instruction. We’ll look into this more deeply when we study pipelined processors in a later chapter. The Data Abort vector is like the Prefetch Abort vector, except for data. Thus, a Data Abort Exception will occur when the processor attempts to fetch data from a memory region without the correct access permissions. The Reset vector is also unique because when it is asserted the processor will immediately stop execution and begin the reset sequence. With other exceptions, the processor will complete the current instruction before accepting the exception sequence. Of course, this makes good sense, since a reset has no need to restore the system context, so you might as well get on with it as soon as possible. Figure 11.10: Format for the ARM modify status register instructions. MSR COND 0 0 0 1 0 R 0 0 1 1 1 1 Rd 0 0 0 0 0 0 0 0 0 0 0 0 MSR Immediate Form COND 0 0 1 1 0 R 1 0 field_mask 1 1 1 1 Rotate Immediate MSR Register Form COND 0 0 0 1 0 R 1 0 field_mask 1 1 1 1 0 0 0 0 0 0 0 0 0 Rm 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Exception Vector Address Reset 0x00000000 Undefined Instructions 0x00000004 Software Interrupt 0x00000008 Prefetch Abort 0x0000000C Data Abort 0x00000010 Reserved 0x00000014 Interrupt Request 0x00000018 Fast Interrupt Request 0x0000001C Chapter 11 320 Summary and Conclusions The ARM instruction set is a thoroughly modern, 32-bit RISC instruction set. Unlike the 8086 and 68K processors, all instructions are the same length and, with few, exceptions, execute in one clock cycle. The register set is almost completely general-purpose. Only three of the 16 regis - ters user mode registers have dedicated uses. All data processing instructions take place between registers and all memory operations are restricted to memory-to-register load operations and regis - ter-to-memory store operations. All memory accesses use one of the general purpose registers as a base address memory pointer. Additional effective addressing modes enhance this model by adding incrementing, decrementing, index register, immediate offset values and scaled register modes. While you might disagree with this, the ARM instruction set architecture is quite a bit simpler and more restrictive than the architectures that we’ve previously examined. This simplicity places more dependence upon the compiler to be able to generate the most optimal code flow, and hence, the most efficient code. With this chapter’s overview of the ARM architecture we will be leaving the study of common ar - chitectures and move on to other topics. We’ll return to the study of architecture once again when we consider pipelines in detail in a later chapter. At that time we’ll return to the ARM architecture once again, but hopefully, we’ll stay at a higher level the next time around. While a certain per - centage of those of you reading these chapters may have found this as exciting as watching paint dry, these is a method to the madness. In order to understand a computer’s architecture from a software perspective, we must look at examples of how the various bit patterns are used to form the instruction words. Dr. Science, a performer on National Public Radio, once said, “I like to read columns of random numbers, looking for patterns.” Summary of Chapter 11 Chapter 11 covered: • A brief history of the evolution of the ARM architecture • An overview of the ARM7TDMI processor architecture • An introduction to the ARM instruction set and addressing modes Chapter 11: Endnotes 1 Jim Turley, RISCy Business, Embedded Systems Programming, March, 2003, p. 37. 2 Ibid. 3 ARM Corporate Backgrounder, http://www.arm.com/miscPDFs/3822.pdf, p. 1. 4 Andrew N. Sloss, Dominic Symes and Chris Wright, ARM System Developer’s Guide, ISBN 1-55860-874-5, Morgan- Kaufmann, San Francisco, CA. 5 Dave Jagger, Editor, Advanced RISC Machines Architectural Reference Manual, ISBN 0-13-736299-4, Prentice-Hall, London. 6 Steve Furber, ARM System-on-chip Architecture, ISBN 0-201-67519-6, Addison-Wesley, Harlow, England. 7 Andrew N. Sloss, Dominic Symes and Chris Wright, ibid, pp. 143–149. 321 1. What are the operating modes of the ARM system? How do they compare with the 68K? 2. Why is there a Fast Interrupt Request Mode and how is it implemented? 3. Compare the 16 base registers of the ARM architecture with the 16 registers of the 68K architecture. 4. Is the instruction, MOV r4,#&103 a legal or illegal instruction? Why? Note: &103 is the ARM notation for a hexadecimal number. 5. Write a code snippet that loads register r4 with the immediate value &103. 6. Initialize register r7 with the value &06AA4C01. 7. Suppose that the contents of register r8 = &0010AA00 and the contents of register r6 = &0000CFD3. What will be the value stored in register r11 after the instruction: ADD r11,r8,r6 LSL #2 8. Rewrite the following 68K instruction as an equivalent ARM operation. Hint: Don’t forget the flags. ADD.L D3,$00001000 9. Assume that <r1> = &DEF02340. Describe as completely as you can the operation performed by the instruction: LDRNEH r4,[r1,#4]! Exercises for Chapter 11 [...]... we’ve examined the computer system in terms of the processor and memory Add a clock and this is a functional, but useless, computer On occasion, throughout the previous lessons, you might have noticed the word interrupt sprinkled here and there Now let’s take the time to understand just what the interrupt is all about Recall that we actually alluded to interrupts when we studied the computer architectures... ARM architecture and its interrupt and fast interrupt request modes We also looked at software interrupts and how they were used to change the context of the processor and access the operating system Now, let’s step back and look at the interrupt process itself In order for a computer to be worth the cost of the electricity that you feed into it, it must be able to interact with you and its environment... fail Glue Logic and Address Decode (Y2K) or human life To outside world Clock Generation may be lost and Distribution If we are going to accept the Random Access I/O Interface fact that we need to make Memory - RAM ( D/A, A/D, Digital ) some order out of the chaos of the real-world, we first need Read Only Communications Memory - ROM to understand how the real( FLASH ) world and the computer can communicate... faults that require special handling From a structural point of view they are handled like an interrupt, except they cannot be masked out If the exception-generating situation occurs, the exception handling process begins immediately Motorola 68K Interrupts The Motorola 68K handles interrupts in a fairly standard manner, so we’ll use this architecture as our prototype and take a few moments to discuss... input and “0” correspond to an output, but hardware designers are such a bunch of kidders Thus, writing $FF to the DDR makes all of the bits of the I/O port output bits and writing a $00, makes all of the bits input bits Writing $AA to the DDR port makes the odd bits inputs and the even bits outputs, and so on Assuming that we program the DDR to $FF, we now have an 8-bit output port From the computer. .. within its own environment, and couldn’t interact with the real world is a rather useless computer It is a nice environment for studying architecture, but that’s about all its good for It was somewhat refreshing (I hope) when you were able to add input and output activity (I/O) to your programs using the TRAP #15 instructions Now, let’s begin our discussion of computers and the real-world by consider... lines in the figure represents the minimum number of components necessary to have an operating computer Outside of the dotted lines is everything else that we need to make it do useful work As you can see, a processor, memory array, glue logic (memory decoding and such) and clocks form the basic computer, but this computer is relatively worthless in human terms We somehow need to be able to interact (interface)... Another factor might be criticality of the interrupt Most laptop computers have a high priority interrupt driven by the circuitry that monitors the battery’s energy level When the battery has almost lost its ability to power the computer, a high-priority ISR automatically takes over and saves the state of the computer so you can shut down and recover when the battery is recharged Speaking of criticality... being read In many situations, particularly with operating systems such as Windows and Linux, the time it takes for the computer and operating system to respond to an interrupt, is unpredictable, and may not be fast enough, to reliably service all of the interrupts in the allotted amount of time In order to deal with computer- based systems that must function reliably while dealing with real-world events,... interrupts are inherent in computer/ real-world interaction;  Explain why interrupts are prioritized;  Understand the concept of I/O ports;  Explain how analog signals are converted to the digital domain and vice versa;  Understand the tradeoffs associated with speed versus accuracy in the analog to digital conversion process Introduction In the previous lesson we saw that a computer that operated only . processor and memory. Add a clock and this is a functional, but useless, computer. On occasion, throughout the previous lessons, you might have noticed the word interrupt sprinkled here and there ARM architecture and its interrupt and fast interrupt request modes. We also looked at software inter - rupts and how they were used to change the context of the processor and access the operating. manipulate a keyboard and a mouse. The computer responds with actions on the screen, sound, disk access, etc. Sometimes unexpected events, called exceptions, occur and the computer has to be able