Research the fir filter and implement it on the fpga de1 board

Leveraging FPGA technology for FIR filter implementation on the DE1 board provides a platform for real-time signal processing with enhanced flexibility and efficiency.. Through meticulou

MINISTRY OF EDUCATION AND TRAINING

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION

GRADUATION THESIS MAJOR: COMPUTER ENGINEERING TECHNOLOGY

INSTRUCTOR: NGUYEN NGO LAM

HUYNH NGOC KHANHRESEARCH THE FIR FILTER AND IMPLEMENT IT

ON THE FPGA DE1 BOARD

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY АND EDUCАTION

FАCULTY OF INTERNATIONAL EDUCATION

GRАDUАTION PROJECT

RESEARCH THE FIR FILTER AND IMPLEMENT IT ON

THE FPGA DE1 BOARD

Students:

NGUYEN HONG DANG

ID Student: 20119127 HUYNH NGOC KHANH

ID student: 19119062 MАJOR: COMPUTER ENGINEERING TECHNOLOGY Advisor: ME NGUYEN NGO LАM

Ho Chi Minh City, June 2024

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY АND EDUCАTION

FАCULTY OF INTERNATIONAL EDUCATION

GRАDUАTION PROJECT

RESEARCH THE FIR FILTER AND IMPLEMENT IT ON

THE FPGA DE1 BOARD

Students:

NGUYEN HONG DANG

ID Student: 20119127 HUYNH NGOC KHANH

ID student: 19119062 MАJOR: COMPUTER ENGINEERING TECHNOLOGY Advisor: ME NGUYEN NGO LАM

Ho Chi Minh City, June 2024

HCMC UNIVERSITY OF

TECHNOLOGY AND EDUCATION

Faculty of International Education

THE SOCIАLIST REPUBLIC OF VIETNАM

Independence – Freedom– Happiness

-

Ho Chi Minh City, June 24, 2024

GRАDUАTION PROJECT АSSIGNMENT

1 Project title: Research the fir filter and implement it on the fpga DE1 board.

2 Initiаl mаteriаls provided by the аdvisor: FIR Filter for Audio Signals Based on FPGA: Design and Implementation

3 Content of the project: Research, design and implement an FIR lowpass filter on kit DE1

4 Finаl product: The low-pass filter system is written in vhdl, successfully

implemented on the DE1 kit, meeting the requirements

CHАIR OF THE PROGRАM

(Sign with full nаme)

ADVISOR

Nguyen Ngo Lam

HCMC UNIVERSITY OF

TECHNOLOGY AND EDUCATION

Faculty of International Education

THE SOCIАLIST REPUBLIC OF VIETNАM

Independence – Freedom– Hаppiness

-

Ho Chi Minh City, June 20, 2024

EVАLUАTION SHEET OF DEFENSE COMMITTEE MEMBER

Student name: Nguyen Hong Dang Student ID: 20119127

Student name: Huynh Ngoc Khanh Student ID: 19119062

Major: Computer Engineering Technology

Project title: Research the FIR filter and implement it on the fpga de1 board

Name of Defense Committee Member:

EVАLUАTION

1 Content of the project:

2 Strengths:

3 Weaknesses:

4 Approval for oral defense? (Approved or denied)

5 Overall evaluation: (Excellent, Good, Fair, Poor)

6 Mark: …… (In words: .)

Ho Chi Minh City, June 24, 2024

COMMITTEE MEMBER

(Sign with full name)

Firstly, I would like to express my аppreciаtion to the University of Technology аnd Educаtion, аs well аs the Fаculty for International Education, for providing аll the support needed in the process of mаking this project

Additionally, I would want to express my gratitude to ME Nguyen Ngo Lam, my primary instructor for my capstone project, for his dedication He provided timely feedback and such targeted guidance to make this project better right from the start He played a significant part in establishing the direction and advancement of this investigation

I also want to thank all of the University of Technology and Education lecturers from the bottom of my heart for giving me the essential background information The information acquired serves as a strong foundation for studying and writing this paper With such limited time and resources for this project, there might be faults and mismatches We are looking forward to receiving feedback from all the reviewers to further develop and improve my future work

Sincerely, Capstone Project implementation team

(Sign and write full name)

Nguyen Hong Dang Huynh Ngoc Khanh

DISCLAMER

This article is the result of our research project under the guidance of our lecturer,

Ph.D Nguyen Ngo Lam We focus our research on the topic "Research the FIR filter

and implement it on the FPGA DE1 board " The examples and results in the article are

based on specific research conditions and do not apply to all situations We recommend

consulting an expert before putting the information from the article into practice

We are not responsible for losses from using the information in the article or

applying the methods in the project

All sources of information have been fully and accurately cited in the article

This article may not be reproduced or used for commercial purposes without our

written consent

Thank you for your interest and participation

Capstone Project implementation team

(Sign and write full name)

Nguyen Hong Dang Huynh Ngoc Khanh

TABLE OF CONTENTS

АBSTRАCT xii

CHАPTER 1: INTRODUCTION xiii

1.1 OVERVIEW xiii

1.2 OBJECTIVES xiv

1.3 RESEARCH SITUATION xv

1.4 SUBJECTS АND SCOPE OF RESEАRCH xv

1.5 REPORT’S LАYOUT xvii

CHАPTER 2: THEORETICАL BАSIS xviii

2.1 INTRODUCTION THE PROBLEM xviii

2.2 INTRODUCTION OF FIR FILTER xix

2.2.1 Concept and Basic Characteristics xix

2.2.2 Structure and Operational Principles xix

2.2.3 Design Methods and Advantages xx

2.2.4 Applications and Future Outlook xx

2.3 THEORETICAL BACKGROUND xx

2.3.1 Understanding FIR Filters xx

2.3.2 FIR filter for audio signals bases on FPGA xxi

CHАPTER 3: Implement FIR lowpass filter on DE1kit xxiv

3.1 DESIGN SPECIFICATIONS AND IMPLEMENTATION xxiv

3.2 CODEC INITIALIZATION xxiv

3.3 S2P ADAPTER BLOCK xxvi

3.4 FIR FILTER BLOCK xxix

3.5 MАIN АLGORITHMS xxx

3.5.1 Flowchart of Clock divider: xxx

3.5.2 Flowchart of CODEC initialization: xxxiii

CHАPTER 4 THE RESULTS xxxix

4.1 SIMULATION RESULTS xxxix 4.2 HARDWARE RESULTS xlv CHAPTER 5: CONCLUSION AND FUTURE WORK li

5.1 CONCLUSION li5.2 FUTURE WORK li

REFERENCES liv

LIST OF FIGURES

Figure 2 1 Direct realisation of FIR filter xxii

Figure 2 2 DE1 Board xxiii

Figure 3 1 The audio digital filter system xxiv

Figure 3 2 I2C Protocol xxv

Figure 3 3 Register Map Description xxvi

Figure 3 4 Block diagram of S2P Adapter xxvii

Figure 3 5 Digital audio interface xxviii

Figure 3 6 Strobe/Ready handshaking (parallel interface) xxviii

Figure 3 7 The concept of FIR low pass design xxix

Figure 3 8 The frequency response of the FIR low pass filter xxx

Figure 3 9 Clock divider Flowchart xxxii

Figure 3 10 Codec initialize flowchart xxxiv

Figure 3 11 S2P flowchart xxxvi

Figure 3 12 FIR filter flowchart xxxviii

Figure 4 1 I2C Protocol xxxix Figure 4 2 Final simulation of the CODEC xl Figure 4 3 Input and output channels of S2P Adapter xl Figure 4 4 Input channel protocol xli Figure 4 5 Output channel protocol xli Figure 4 6 Final simulation of top module xli Figure 4 7 Final simulation of FIR filter xlii Figure 4 8 RTL viewer xliii Figure 4 9 Output signal at cutoff frequency 5Khz xliii Figure 4 10 Output signal at cutoff frequency 5Khz on MATLAB app xliv Figure 4 11 Output signal at cutoff frequency 10Khz on MATLAB app xliv Figure 4 12 Output signal at cutoff frequency 15Khz on MATLAB app xlv Figure 4 13 Hardware devices xlvi Figure 4 14 Input and Output at 5Khz xlvi Figure 4 15 Input and Output at 10Khz xlvii Figure 4 16 Input and Output at 15Khz xlvii Figure 4 17 Input and Output at 18Khz xlviii Figure 4 18 Four 7 segment LEDs display on kit DE1 xlviii Figure 4 19 LEDs display on DE1 kit xlix Figure 4 20 Harmonic Distortion xlix

АBSTRАCT

This essay presents a comprehensive exploration of the research endeavor focused

on implementing Finite Impulse Response (FIR) filters on the FPGA DE1 board FIR filters,

integral to digital signal processing, offer precise control over signal characteristics and find applications in diverse domains such as audio processing, communications systems,

and image filtering Leveraging FPGA technology for FIR filter implementation on the DE1 board provides a platform for real-time signal processing with enhanced flexibility and efficiency Through meticulous research and experimentation, this study delves into the theoretical foundations of FIR filters, design methodologies, FPGA implementation techniques, and performance evaluation on the DE1 board By bridging the gap between theory and practice, this research contributes to the advancement of FPGA-based signal processing techniques and unlocks new avenues for innovation in digital signal processing applications

CHАPTER 1: INTRODUCTION

In conclusion, Finite Impulse Response filters are an essential instrument in digital signal processing that allows one to adjust the characteristics of signals, such as frequency response and noise attenuation, with high precision The integration of concepts of designing such filters into Field-Programmable Gate Arrays has inspired new applications of signal processing and considerably broadened their possibilities Thus, the purpose of this essay was to offer a wide perspective on the research in the area of FIR filters and their realization on the FPGA DE1 board while combining the theoretical background with specific examples of implementation

A finite impulse response refers to the FIR filter, where the output of the filter depends only on the finite sequence of its earlier samples FIR filters are designed in terms of filter coefficients, which determine the filter’s frequency response and the overall behavior There are different design methods involving windowing, frequency sampling and optimization algorithms like Parks-McClellan that can be used to create custom FIR filters for a specific application

Field-Programmable Gate Arrays are another flexible hardware platform used to prototype and run digital signal processing algorithms To implement FIR filters on FPGAs, the filter algorithms should be translated into a hardware description language, such as Verilog or VHDL The DE1 board, which is developed on an Altera Cyclone II FPGA, is a popular choice for FIR filter implementation It provides a good trade-off between computational power and available resources

In general, the implementation of FIR filters on the DE1 board involves a structured process from the design stage through simulation, synthesis, and programming Designers define the filter architecture and resolve the respective coefficients Next, simulation within a framework such as using Model-Sim permits an assessment of the filter’s functionality and performance A synthesis tool such as from Quartus Prime allows the production of hardware description files prior to programming the FPGA on the DE1 board

The performance evaluation of the FPGA-based FIR filters includes metrics related to filtering effectiveness, throughput, resource utilization, and power consumption Comparative analysis with theoretical models and simulation results is used to evaluate the effectiveness of the implemented filters Not only this, but there are continuous research efforts directed toward the optimization of FIR filter designs for better resource utilization and enhanced overall performance

The symbiotic relationship of FIR filter design and the advent of FPGA technology produces unparalleled opportunities for advancing new capabilities in digital signal processing Precise design and implementation, such as on the DE1 board, make FIR filters versatile tools that make engineers and researchers able to tackle different challenges of signal processing with agility and precision With continuously developing research in this direction, this fusion of theoretical insights into practice promises the redefinition of the landscape of digital signal processing toward novel applications in many domains

The essay shall detail the main objectives that guide research into the implementation

of FIR filters on the DE1 board of an FPGA FIR filters help in digital signal

of deploying FIR filters onto FPGA platforms like the DE1 board:

- Investigate FIR Filter Design Methodologies: Explore various FIR filter design

techniques, including windowing, frequency sampling, and optimization algorithms such as Parks-McClellan Evaluate the advantages and limitations of each design methodology in terms of filter performance, complexity, and resource utilization Identify the most suitable design approach based on the requirements of real-time signal processing applications

- Optimize FPGA Implementation for Resource Efficiency: Investigate

optimization strategies to enhance resource utilization and minimize area overhead in FPGA implementations of FIR filters Explore techniques for reducing hardware complexity while maintaining filter performance and throughput Evaluate the trade-offs between resource utilization, filter accuracy, and power consumption in FPGA-based FIR filter designs

- Validate Filter Performance Through Simulation and Experimentation: Develop

comprehensive simulation models to validate the functionality and performance

of FPGA implemented FIR filters Conduct real-world experiments using benchmark signals to assess the filter’s efficacy in noise reduction, frequency shaping, and signal enhancement Compare simulation results with experimental data to validate the accuracy and reliability of FPGA-based FIR filter implementations

- Explore Real-Time Signal Processing Applications: Investigate potential

applications of FPGA-based FIR filters in domains such as audio processing, image filtering, communications systems, and biomedical signal analysis Evaluate the suitability of FIR filters for real-time processing tasks requiring low latency and high throughput Explore the scalability of FPGA-based FIR filter implementations for handling large-scale signal processing tasks in resource constrained environments

- Facilitate Accessibility and Reproducibility: Develop open-source FPGA

implementations of FIR filters and provide comprehensive documentation to facilitate accessibility and reproducibility Foster collaboration and knowledge sharing within the research community by establishing repositories of FPGA-based FIR filter designs, 3simulation models, and experimental datasets Encourage the adoption of standardized design methodologies and best practices

to ensure consistency and reliability across FPGA implementations of FIR filters

Research methods used include:

- Learn theory

- Run simulation on development environment

- Build and deploy the system on production environment

This essay provides an insightful exploration of the current research landscape

surrounding the implementation of Finite Impulse Response (FIR) filters on the FPGA DE1 board FIR filters are fundamental components in digital signal processing,

offering versatile capabilities for noise reduction, frequency shaping, and signal

enhancement Leveraging FPGA technology for FIR filter implementation presents exciting opportunities for real-time signal processing applications Through this essay,

we navigate the research situation, highlighting recent advancements, ongoing

challenges, and emerging trends in the field of FIR filter implementation on FPGA platforms like the DE1 board

Important points about the research situation of "FIR Filters on the FPGA DE1 Board" include:

- Advancements in FIR Filter Design Methodologies: Recent research has

witnessed

significant advancements in FIR filter design methodologies, with a focus on optimizing filter performance, complexity, and resource utilization Novel

approaches, such as genetic algorithms and machine learning techniques, are being explored to automate the design and optimization of FIR filters for FPGA implementation Researchers are also investigating adaptive FIR filter designs capable of dynamically adjusting filter coefficients in response to changing signal conditions, enabling enhanced adaptability and performance in real-time applications

- FPGA Implementation Challenges and Solutions: While FPGA technology

offers unparalleled flexibility and scalability for implementing digital signal processing algorithms, challenges related to resource constraints, power consumption, and design complexity persist Recent research endeavors have focused on developing innovative solutions to address these challenges, including resource-efficient filter architectures, low-power optimization techniques, and high-level synthesis tools for rapid FPGA prototyping Additionally, collaborative research efforts between academia and industry have resulted in the development of FPGA-based design frameworks and libraries tailored specifically for FIR filter implementation, streamlining the design process and accelerating time-to-market for FPGA-based signal processing solutions

- Real-World Applications and Case Studies: The proliferation of FPGA-based

FIR filter implementations has fueled advancements in a myriad of real-world applications spanning diverse domains Case studies and application-specific research highlight the versatility and efficacy of FPGA-based FIR filters in domains such as wireless communications, medical imaging, radar signal processing, and audio processing Researchers are actively exploring innovative use cases for FPGA-based FIR filters, including edge computing, Internet of Things (IoT) devices, and autonomous systems, underscoring the broad applicability and transformative potential of FPGA technology in the era of digital transformation

- Emerging Trends and Future Directions: Looking ahead, emerging trends in FIR

filter implementation on FPGA platforms point towards the convergence of heterogeneous computing architectures, leveraging the synergy between FPGAs, GPUs, and specialized accelerators Research directions include exploring hybrid FPGA-GPU architectures for accelerating FIR filter computations, leveraging deep learning techniques for automated FPGA design optimization, and advancing hardware-software co-design methodologies for holistic system optimization Furthermore, interdisciplinary collaborations between researchers from diverse fields such as computer science, electrical engineering, and applied mathematics are driving innovation at the intersection of FPGA technology and digital signal processing, fostering a vibrant 5research ecosystem poised for

continued growth and discovery

- Conclusion: The research situation surrounding the implementation of FIR filters

on the FPGA DE1 board is characterized by a dynamic interplay of advancements, challenges, and opportunities As researchers continue to push the boundaries of FPGA based signal processing, the landscape evolves to embrace emerging technologies, novel methodologies, and transformative applications By navigating this research situation with diligence and creativity, researchers can unlock new frontiers in Realtime signal processing, driving innovation, and impact across diverse domains

Our capstone project report will consist of 5 chapters:

- Chapter 1: Overview of the topic General introduction to the issues mentioned

in the topic, stating the importance and urgency of the topic Clearly point out the development and application of FIR filter in practice, thereby giving reasons for choosing the topic At the same time, determine the goals, subjects, and scope

of research for the topic

- Chapter 2: Theoretical basis Presents an overview of the theory and operating

principles of the sensors and modules used Introducing the languages and technologies applied in the topic

- Chapter 3: System design Present the system block diagram and calculations,

and select the components used to design the main diagram of the hardware Design the structure and operation diagram of the FIR filter From there, program and build the system Build a system with multiple components from the submodule to the top module

- Chapter 4: The Results of system Present the results obtаined аfter completing

the system construction

- Chapter 5: Conclusion and future work The group formulates conclusions

for the topic based on the goals outlined in Chapter 1 after considering the results

of Chapter 4 Simultaneously, they suggest avenues for refinement and future developments to round out the subject and make it more extensively used in practice

CHАPTER 2: THEORETICАL BАSIS

This essay embarks on an illuminative journey into the realm of Finite Impulse Response (FIR) filters, exploring their theoretical foundations and practical implementation on the FPGA DE1 board FIR filters serve as indispensable tools in digital signal processing, offering precise control over signal characteristics and enabling a myriad of applications ranging from noise reduction to frequency shaping Leveraging the power and flexibility of FPGA technology for FIR filter implementation

on the DE1 board holds promise for real-time signal processing with enhanced efficiency and versatility Through a comprehensive examination of FIR filter theory and FPGA implementation techniques, this essay aims to bridge the gap between theoretical understanding and practical application, shedding light on the intricate interplay between theory and practice in FIR filter research and implementation

Delving into FIR Filter Theory: FIR filters, characterized by their finite impulse response, offer a straightforward yet powerful approach to signal processing The impulse response of an FIR filter, defined by a finite sequence of coefficients, determines the filter’s behavior and frequency response Key concepts such as filter order, cutoff frequency, transition bandwidth, and filter type delineate the design space and influence the performance of FIR filters

Design Methodologies Unveiled: A plethora of design methodologies exists for specifying the coefficients of FIR filters to achieve desired frequency responses Windowing techniques, including the Hamming and Kaiser windows, provide intuitive means of designing FIR filters with specified passband and stopband characteristics Frequency sampling methods offer direct control over the filter’s frequency response

by prescribing desired magnitude and phase characteristics at discrete frequency points Optimization algorithms such as the Parks-McClellan algorithm facilitate the design of FIR filters with optimal frequency response properties, minimizing ripple and meeting stringent design specifications

FPGA Implementation: Transforming Theory into Reality: FPGA technology serves as

an ideal platform for implementing FIR filters, offering reconfigurability, parallelism, and real-time processing capabilities The DE1 board, featuring an Altera Cyclone II FPGA, emerges as a compelling choice for FPGA-based signal processing applications Implementation of FIR filters on the DE1 board entails translating filter algorithms into hardware description language (HDL) code, such as Verilog or VHDL, and synthesizing

the code to generate the corresponding hardware configuration files Practical considerations such as resource utilization, clock frequency, and input/output interfaces are meticulously addressed to ensure efficient utilization of FPGA resources and real-time performance

Challenges and Triumphs in FPGA Implementation: FPGA implementation of FIR filters presents challenges including resource constraints, timing closure, and power consumption Advanced techniques such as pipelining, parallel processing, and resource sharing mitigate these challenges, enhancing overall performance and efficiency High-level synthesis tools and design automation techniques streamline the FPGA development process, enabling rapid prototyping and deployment of FIR filter implementations on the DE1 board

Bridging the Gap Between Theory and Practice: The synthesis of FIR filter theory and FPGA implementation techniques on the DE1 board epitomizes the seamless fusion of theory and practice in digital signal processing By harnessing the symbiotic relationship between theoretical understanding and practical application, researchers and engineers unlock new frontiers in real-time signal processing, driving innovation and exploration in diverse domains The journey from theory to practice underscores the transformative potential of FIR filter research and implementation on FPGA platforms like the DE1 board, paving the way for novel applications, breakthroughs, and discoveries in the dynamic landscape of digital signal processing

2.2 INTRODUCTION OF FIR FILTER

2.2.1 Concept and Basic Characteristics

The Finite Impulse Response (FIR) filter stands as a cornerstone in digital signal processing, particularly in the realm of audio, image processing, and communication systems Distinguished from its counterpart, the Infinite Impulse Response (IIR) filter, FIR filters exhibit no feedback from past outputs, rendering each output sample dependent solely on a finite number of input samples and the filter coefficients

The FIR filter is characterized by its precision and straightforward design Its finite nature ensures stability and ease of implementation, making it a popular choice for applications demanding high accuracy and swift responsiveness

2.2.2 Structure and Operational Principles

The fundamental structure of an FIR filter comprises a series of coefficients (taps) and

an array of input samples Each output sample is computed by summing the weighted input samples, where each sample is multiplied by a corresponding coefficient

The operational principle of the FIR filter relies on applying these coefficients to input samples and subsequently summing the weighted values to generate a new output sample This process is entirely linear and easily comprehensible, rendering the FIR filter a flexible and user-friendly tool across various applications

2.2.3 Design Methods and Advantages

Designing an FIR filter can be achieved through multiple methods, including utilizing window functions such as Hamming, Blackman, or via optimization methods like the Parks-McClellan or Remez algorithms Each method presents its own set of advantages and limitations, contingent upon the specific requirements of the application

The primary advantage of FIR filters lies in their high precision and stability Without feedback from past outputs, FIR filters mitigate the risk of undesired oscillations in the output, making them ideal for applications necessitating reliability and consistency

2.2.4 Applications and Future Outlook

FIR filters find widespread applications across various domains, including audio processing, image processing, digital communication, and system control With the incessant advancement of technology and the escalating demand for digital signal processing, FIR filters are poised to continue playing a pivotal role and evolving in the future

2.3.1 Understanding FIR Filters

FIR filters are characterized by their finite impulse response, meaning their output is solely determined by a finite sequence of input samples and filter coefficients The impulse response of an FIR filter, represented by a finite-length sequence of coefficients, defines the filter’s behavior and frequency response FIR filters are commonly employed for tasks such as noise reduction, signal enhancement, and frequency shaping in digital signal processing applications

Design Methodologies for FIR Filters:

- Various design methodologies exist for specifying the coefficients of FIR filters

- to achieve desired frequency responses

- Windowing techniques, including the Hamming and Kaiser windows, provide

- intuitive ways to design FIR filters with specific passband and stopband

characteristics

- Frequency sampling methods allow direct control over the filter’s frequency

response by specifying magnitude and phase characteristics at discrete frequency points

- Optimization algorithms such as the Parks-McClellan algorithm offer systematic

- approaches for designing FIR filters with optimal frequency response properties

FPGA Implementation of FIR Filters:

- Field-Programmable Gate Arrays (FPGAs) provide a flexible and reconfigurable

- platform for implementing FIR filters with high computational efficiency

- The DE1 board, featuring an Altera Cyclone II FPGA, offers a suitable

environment for FPGA-based signal processing applications

- FPGA implementation of FIR filters involves translating filter algorithms into

- hardware description language (HDL) code, such as Verilog or VHDL, and

synthesizing the code to generate hardware configuration files

- Considerations such as resource utilization, clock frequency, and input/output

interfaces are crucial for optimizing FPGA implementations of FIR filters on the DE1 board

Performance Evaluation and Validation:

- Rigorous performance evaluation and validation are essential to ensure the

functionality and efficacy of FPGA-based FIR filters

- Simulation-based testing and hardware-in-the-loop (HIL) testing validate the

performance of FPGA-implemented FIR filters under diverse operating conditions

- Comparative analysis against theoretical models and simulation results

corroborates the accuracy and reliability of FPGA-based FIR filter implementations

2.3.2 FIR filter for audio signals bases on FPGA

A filter in signal processing is a device that extracts a usable range of frequencies or rejects undesirable portions of the signal, such as random noise An optimal filter should only permit specific frequencies to flow through while blocking all others This is dependent upon the necessary filter’s cutoff frequency There are four types of filters: band pass, band stop, high pass, and low pass Electric filters, such as those found in televisions and radios, work by allowing a certain channel’s frequency range to pass through while blocking out those of other channels In signal processing, FIR filters, usually referred to as non-recursive filters, are frequently employed

The inputs from the past and present affect the FIR filter’s output It will become stable and simple to apply as a result Stated differently, FIR filters provide more hardware implementation realizability [3] Depending on the hardware requirements, a filter with

a large number of coefficients and taps is necessary to increase performance

The frequency response of the FIR filter in the z-domain and the relationship between y(n) and x(n) are displayed in the equations below

The equations show that the coefficients of the filter are presented by 𝑏𝑘 Furthermore, the FIR filter lacks feedback, and as shown in figure below, its underlying architecture can be described by a sequence of block diagrams known as tapped delay lines or direct realization

Figure 2 1 Direct realisation of FIR filter

FPGA platforms have advanced in terms of reconfigurable hardware design for speed processing with the quick development of digital signal processing It is commonly acknowledged that the Very High-Speed Integrated Circuits Hardware Description Language (VHDL) can be used to reprogrammed the FPGA in accordance with the needs of the designer FPGA is used in many different applications, including image processing, audio processing, speech recognition, and high-performance computing

high-The International Technology Roadmap for Semiconductors (ITRS) has been cited as having the goal of keeping costs low while reducing the size of the items For instance, the FPGA is inexpensive and has a large number of components This indicates that while the circuit’s component sizes have decreased, performance has grown

concurrently In this scenario, it is often possible to reduce the electronic gadgets’ power consumption

FPGAs may be repeatedly programmed with the desired application, in contrast to Application Specific Integrated Circuits (ASICs), where the device can be developed for the specific design The many-featured Cyclone II FPGA is employed in this study For example, it is the FPGA series with the lowest cost, embedded CPU support, and embedded DSP multipliers As seen in Figure 2, the Altera DE1 board also has the Cyclone II FPGA in addition to many other features This board can be used for a variety

of design projects in addition to the development of complex digital systems

Figure 2 2 DE1 Board

CHАPTER 3: IMPLEMENT FIR LOWPASS FILTER ON

DE1KIT3.1 DESIGN SPECIFICATIONS AND IMPLEMENTATION

The proposed system is designed to meet the below requirements:

Three blocks have been created and assessed to gain insights into the functioning of the entire system These blocks include:

• Codec initialization block

• S2P Adaptor (responsible for converting between serial and parallel data)

• FIR filter block

To achieve a filtered audio signal, several steps must be taken Initially, the Codec block must be initialized, relying on the I2C protocol because the Codec lacks a predefined configuration upon power-up Subsequently, within the S2P Adaptor block, the serial digital signal is transformed into a parallel digital signal and forwarded to the FIR filter Lastly, the filtered signal undergoes conversion back to a serial signal through the same S2P block and is then routed back to the Codec output port

Figure 3 1 The audio digital filter system

3.2 CODEC INITIALIZATION

The initialization phase is critical in defining the operation of the Codec, specifying parameters such as a 44100 Hz sample rate and two input channels (left and right) This architecture uses only the left channel, with settings controlled by data bits stored in registers Loading these data bytes into the registers, which contain both address and data, allows the actual audio signal data to be transmitted over the control interface, namely via the pins SCLK and SDIN, where SDIN handles serial data and SCLK regulates the serial data clock The I2C protocol is used for codec initialization, which involves establishing the start and end conditions of the SDIN signal and then regulating the delivered data, which contains configurations For example, after transmitting each eight bits, the Codec expects to receive an acknowledgment bit (ACK) from the FPGA,

confirming that the data was correctly received, as shown in Figure 3.2

In order to initialize the Codec, SDIN transmits 11 words of data, each with 24 bits in

it Eight bits are used at the beginning of each word; seven are used for the chip address (Codec) and one bit is used to indicate whether the operation is a read or write The address of the register is indicated by another 8 bits, and the actual data for customizing the Codec is contained in the last 8 bits The data transmission is governed by SCLK, which operates at a maximum frequency of 500 kHz.However, for verification reasons,

it can function at lower frequencies The commencement of data transmission is depicted in Figure 4 as starting with the detection of the start condition, which occurs when SDIN goes from high to low (falling edge) and SCLK stays high Most significant bit (MSB) to least significant bit (LSB) is the order in which data is transmitted The Codec awaits a new start condition in the event that an erroneous address is received When the SDIN receives the right address bits and an R/W bit of 0, it sends out eight bits and waits for an acknowledgment This process is repeated for every word (24 bits), and when the last ACK is received, the rising edge of SDIN is detected while the SCLK stays high and the SDIN changes from low to high, indicating the stop condition The

Figure 3 2 I2C Protocol

Codec goes back to idle mode and waits for another start condition after transmitting all configuration data Understanding the content of each register is crucial for comprehending all 11 data words, as the I2C Protocol offers various options enabling designers to achieve their objectives Familiarity with the details of all registers is essential for leveraging these options effectively, as depicted in Table below

Figure 3 3 Register Map Description

3.3 S2P ADAPTER BLOCK

Prior to being transmitted to the FIR filter block, the S2P adaptor block converts the digital data from the Codec from serial to parallel It receives the processed data from the FIR block after converting the data from parallel to serial, as shown in Figure 5

Additionally, it has two interfaces: a digital audio interface and a paralleling interface The term "BCLK" refers to a clock signal generated by the FPGA in the digital audio interface, which is used to identify data bits numbered one through sixteen This can be identified when the BCLK changes from high to low (the falling edge) and the LRC signal is strong Nonetheless, the initial bit gets read in the bit’s center because of how stable its architecture is In other words, as Figure 6 shows, reading (transmitting) occurs when BCLK rises from low to high (rising edge), and writing (receiving) occurs

on the descending edge of BCLK

Figure 3.4 illustrates the distinction between audio input serial data (ADCDAT) and audio output serial data (DACDAT) The ADCDAT and DACDAT data begins with the LRC signal, which also serves as a BCLK reference Furthermore, the MSB and the input and output data (ADCDAT and DACDAT) begin transferring simultaneously Each bit requires one BCLK cycle when data is sent or received via the left and right channels As a security measure, idle time intervals (32 bits) can be used to provide the FIR filter ample time to process the data This length starts at the end of the left and right channels and ends with the next LRC

Figure 3 4 Block diagram of S2P Adapter