HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION FACULTY OF INTERNATIONAL EDUCATION GRADUATION PROJECT LE TRONG HOANG Student ID: 20119132 TRAN NGUYEN ANH KHOA Student ID: 20119
INTRODUCTION
Introduction
In the era of Industry 4.0, the rapid advancement of electronics and information technology has led to the emergence of innovative devices like personal computers and smartphones, significantly enhancing modern lifestyles These high-tech products not only improve daily living but also play a crucial role in the global technology competition among advanced nations.
The remarkable success of electronic devices highlights the crucial role of the semiconductor chip industry In particular, the manufacturing of small yet powerful electronic chips is essential, as these chips serve as the indispensable core of electronic circuits.
The integration of transistors into compact spaces has sparked a competitive race among major technology companies like Intel, IBM, Sony, and Toshiba to launch innovative products This advancement has also catalyzed the growth of various industries, including embedded systems and the Internet of Things (IoT), addressing the increasing demand for complexity and modernity across diverse aspects of human life.
For systems to function properly, they require pre-programmed command line functions and efficient input/output data handling, leading to the necessity of memory storage This need gave rise to memory made from integrated circuits, which consists of two primary types: Read-Only Memory (ROM) and Random Access Memory (RAM).
ROM serves as the primary memory that retains the operating status of a system, with its fixed bits remaining unchanged when the power is off, unless reloaded In contrast, RAM temporarily stores data and application programs in use, allowing the device's processor to access them swiftly; however, this data is lost without a power supply.
RAM is primarily categorized into two types: dynamic random access memory (DRAM) and static random access memory (SRAM) DRAM stores data in capacitors that require constant recharging to maintain their charge, utilizing a transistor to manage read and write operations In contrast, SRAM relies on interconnected transistors to store bits without the need for continuous charging, allowing for faster access times.
In Q1 2024, the global smartphone market experienced a 6% year-over-year growth, achieving 296.9 million unit shipments This surge in demand underscores the growing concern about the operating time of mobile devices.
Low power consumption is essential for the sustainability of the semiconductor industry, especially in portable and smart devices Static Random-Access Memory (SRAM) cells play a crucial role in chip design but contribute significantly to leakage power during idle operation, which can ultimately restrict battery life.
This paper explores the use of various low-power design modules to tackle the challenges associated with conventional 6T SRAM cells While reducing supply voltage is a common approach, alternative methods often lead to an increased number of transistors, with configurations expanding from 7T to 14T Key techniques discussed include power gating, multi-threshold complementary metal-oxide-semiconductor (MTCMOS), reverse bias, and transistor width modification, which are critical for enhancing power efficiency in SRAM designs.
Objectives
-Introduction to 6T SRAM and low power design of: Components and descrip- tions of their functions
-Research and apply power methods, thereby designing low-power designs
-Learn the basics and main functions of Virtuoso Cadence simulation design soft- ware running on VMware virtual machine platform
-Evaluate data reading and writing activities for each specific testbench case based on simulation results
-Calculate power, latency in the cases of read/write/hold states
-Layout each component in an 8x8 SRAM set and combine it into a complete de- sign.
Methodology
The project implementation team initiated their research by analyzing and synthesizing theories from various sources to create principle diagrams and calculate specific parameters for modeling They then employed experimental methods to validate the results obtained This research approach focused on effectively solving problems throughout the process.
- Solve problem 1: Learn the structure of the 6T transistor model and its mode of operation
- Solve problem 2: Research low-power methods and apply them to designs
- Solve problem 3: Build a model to read and write data and test by simulation of states represented through timing diagrams
- Solve problem 4: Assemble the components of a complete SRAM memory and evaluate the latency, and power consumption when performing data reads and writes
- Solve problem 5: Learn the rules and correct methods to layout the model of each component in the project
- Solve problem 6: Completing and evaluating the overall results for the entire im- plementation process, thereby providing comments and development directions.
Report’s layout
Chapter 1 provides an overview of microchips, with a specific focus on Static Random Access Memory (SRAM) It outlines the objectives of the research, the current state of knowledge in the field, and the methodological approach taken This chapter sets the stage for the subsequent sections, guiding the reader through the development of the topic.
Chapter 2 of the literature review examines the structure and components of SRAM memory, explores low power techniques, and discusses relevant theories It details the processes involved in reading and writing data for various fixed cases, ultimately providing a comprehensive design framework for the topic at hand.
• Chapter 3 System design: Analyze deeply each block of SRAM , put the components together and explain the function of each circuit
• Chapter 4 Results: Perform a test to evaluate the read/write states achieved through simulation Then do the layout, and complete assembly according to design standards
In Chapter 5, we conclude by summarizing the achievements attained in the topic while also addressing the limitations encountered in relation to the established goals Furthermore, we will outline potential directions for future development, emphasizing opportunities for growth and improvement in subsequent research endeavors.
LITERATURE REVIEW
SRAM structure
The SRAM array consists of 64 memory cells arranged in an 8x8 configuration, utilizing a 6T SRAM design with two pull-up, two pull-down, and two pass gate transistors These cells are organized in rows and columns, controlled by wordlines (WLs) and bitlines (BLs), with each cell assigned a unique address accessible through the WL signal During access, the WL signal activates the pass gate transistors, while read and write operations are managed by the corresponding bitline (BL) and its complement, bitline bar (BLB) Further details on the operational intricacies will be discussed in Section 2.3.
Figure 2 1 Block diagram of 8x8 SRAM
Each memory cell is assigned a unique address, and to manage a large number of addresses efficiently, decoders are used to minimize the bits needed for identification The two main types of decoders are row decoders and column decoders Additionally, some designs may include a pre-decoder, especially in applications that emphasize low power consumption.
Table 2 1 Comparing number of cells can be controlled without/with decoder
Number cell can control without decoder 3 6
Number cell can control with decoder 8 64
A comprehensive SRAM design includes essential peripheral components that manage the read/write operations of memory cells, with the control block acting as the central hub for precise signal activation This block's primary objective is to generate internal clock signals from external clock pulses, highlighting the critical role of timing signals in SRAM operations Furthermore, the control block efficiently manages various input signals, such as addresses and memory enable signals, to ensure optimal functionality of the SRAM.
The pre-charge circuit plays a crucial role in managing the charging and discharging sequences of bitlines in memory operations Before each read or write operation, the bitlines must be pre-charged to the VDD voltage level Once the read or write signals are activated, the pre-charge circuit disengages, enabling one of the bitlines to discharge or be pulled down, depending on the specific operation being executed.
The read process in SRAM involves detecting voltage differences between the bitline and its complement, the bitline bar, with a focus on minimizing this variance for better power efficiency A sense amplifier is utilized to detect these small voltage differentials, and when paired with an output data latch, it effectively identifies and indicates the stored value in the cell.
Figure 2 2 Operations of Sense Amplifier
The write operation in SRAM necessitates grounding the bitline, which demands a powerful driver to quickly pull it down This write driver works in tandem with the input data latch to effectively support the write process.
Figure 2 3 Operations of Write Driver : a) Write 1 operation; b) Write 0 operation
The I/O block features circuits that regulate data flow, ensuring synchronization by latching incoming data before a write operation begins During data retrieval from memory cells, the data is also latched out before the sense amplifier is deactivated, guaranteeing a stable output These critical processes occur within the I/O control block.
Read/Write operation of SRAM
The mainstream six-transistor (6T) CMOS SRAM cell, depicted in Figure 2.4, is constructed similarly to an SR latch, utilizing six transistors This configuration includes four transistors (Q1 - Q4) that form cross-coupled CMOS inverters, while two NMOS transistors (Q5 and Q6) facilitate read and write access to the memory cell.
17 the word line, the access transistors connect the two internal nodes of the cell to the true (BL) and the complementary (BLB) bit lines
Figure 2 4 Six-transistor (6T) CMOS SRAM cell [3]
Initially, both bitlines are at a high-floating state For simplicity, let's assume that
In this operation, Q starts at 0 while Q_b is set to 1, and both Q_b and bit_b must stay at 1 When the wordline is activated, the driver and access transistors D1 and A1 pull the bit down, causing node Q to rise To maintain Q at a low level, the strength of driver D1 must surpass that of access transistor A1, ensuring that Q remains below the switching threshold of the P2/D2 inverter, a condition known as read stability.
Figure 2 5 Read operation for 6T SRAM cell [4]
The waveforms depicting the read operation are illustrated in Figure 2.5 when a 0
18 is read onto the bit It's noteworthy that while Q momentarily rises, it doesn't experi- ence significant glitching to cause the cell to flip
To write a 1 into an SRAM cell initially set to 0, the bit is pre-charged high while bit_b is driven low by a write driver Due to read stability constraints, bit cannot elevate Q through A1, necessitating that Q_b be pulled low via A2 For this to occur, P2 must be weaker than A2, ensuring Q_b can drop sufficiently low, a condition known as writability Once Q_b is low, D1 deactivates, and P1 activates, resulting in the desired increase of Q Figure 2.6 illustrates the SRAM cell writing process.
Figure 2 6 Write operation for 6T SRAM cell [4]
Delay time
Propagation delay time (tpd) is defined as the maximum duration from the input signal crossing the 50% threshold to the output signal reaching the same threshold, as shown in Figure 2.7 The propagation delay for a signal transmitted through a logic gate can be determined using a specific formula.
TPHL: Time propagation from High to Low
TPLH: Time propagation from Low to High
Figure 2 7 Propagation delay and rise/fall times [4]
Contamination delay time, tcd = minimum time from the input crossing 50% to the output crossing 50%
Rise time, t r = time for a waveform to rise from 20% to 80% of its steady-state value
Fall time, t f = time for a waveform to fall from 80% to 20% of its steady-state value
Power Consumption
The instantaneous power P(t) consumed or supplied by a circuit element is the product of the current through the element and the voltage across the element
The average power over this interval is
Power dissipation in CMOS circuits comes from two components:
• Charging and discharging load capacitances as gates switch
• “Short-circuit” current while both pMOS and nMOS stacks are partially
• Subthreshold leakage through OFF transistors
• Gate leakage through gate dielectric
• Junction leakage from source/drain diffusions
• Contention current in ratioed circuits
P Static =(I sub +I gate +I junc +I connection )V DD (2.6)
Putting this together gives the total power of a circuit
Static noise margin (SNM)
The stability and writability of a cell are assessed through the hold margin, read margin, and write margin, which reflect the static noise margin during different operational modes In hold and read operations, a cell must maintain two stable states, while during write operations, it should only have one stable state The static noise margin (SNM) quantifies the amount of noise that can be tolerated at the inputs of the cross-coupled inverters before losing stability in hold or read modes or generating a second stable state during write operations.
In the analysis of cross-coupled inverters, a noise source \( V_n \) is introduced while the access transistors remain OFF, ensuring they do not influence circuit performance The static noise margin can be graphically assessed using a butterfly diagram, as illustrated in Figure 2.8 This diagram is created by setting \( V_n = 0 \) and plotting \( V_2 \) against \( V_1 \) for curve I and \( V_1 \) against \( V_2 \) for curve II.
Figure 2 8 Butterfly diagram indicating hold margin [4]
During the cell reading process, bitlines are precharged, causing the access transistor to elevate the low node, which distorts the voltage transfer characteristics This scenario results in a static noise margin known as the read margin, which is smaller than the hold margin The read margin can be evaluated by simulating the circuit with the bitlines connected to VDD, as illustrated in Figure 2.9.
When the cell is being written, the access transistor A must overpower the pullup
To establish a single stable state in memory, the write margin is defined through a simulation analogous to the read margin, involving one access transistor driving the state to 0 and another to 1 If the voltage |Vn| exceeds a certain threshold, a second stable state may emerge, hindering write functionality Figure 2.10 illustrates the characteristics when the bit is maintained at 0.
Low power gating method
Power gating is a technique that partitions functions on an integrated circuit (IC) by connecting power supplies to power gates, allowing for complete shutdown of power to specific blocks This method effectively zeros out voltage in the power equation, leading to significant static and dynamic power savings while the block is off To maximize these savings, it is crucial to turn off as many power domains as possible without compromising functionality Implementing power switches and isolation gates is necessary to maintain known boundary values when the power is off Additionally, careful consideration of the power states and the combinations of ON/OFF states for various voltages is required A power management unit (PMU) must also be integrated to control the power switches and isolation signals, ensuring the correct sequence during power down and power up to clamp values accurately at the right times.
MTCMOS method
Multi-threshold CMOS (MTCMOS) technology utilizes transistors with varying threshold voltages (Vth) to enhance performance by optimizing delay and power consumption This innovation allows for the formation of an inversion layer at specific gate voltages, contributing to improved efficiency in CMOS chip design.
The interface between the gate oxide layer and the substrate of a transistor defines its threshold voltage (Vth), with low Vth devices offering faster switching speeds, making them ideal for critical delay paths to optimize clock periods However, these low Vth devices incur significantly higher static leakage power In contrast, high Vth devices are employed on non-critical paths to substantially reduce static leakage, achieving a tenfold decrease compared to their low Vth counterparts In active mode, the sleep transistor is activated, maintaining circuit functionality, while in standby mode, it is turned off to disconnect the gate from ground, necessitating a higher threshold voltage to minimize leakage If not properly managed, a low threshold can lead to excessive leakage current, undermining the effectiveness of power gating Furthermore, reducing the width of the sleep transistor relative to the combined width of the pull-down circuit transistors can enhance leakage control To maintain circuit performance, careful sizing of the sleep transistor is essential to minimize voltage drop during operation, as this drop can lower the effective supply voltage of the logic gate and increase the threshold voltage of pull-down transistors due to the body effect.
Figure 2 12 Parameters of (a) High-voltage threshold and (b) Low-voltage threshold
Reverse body bias method
To establish a reverse junction between the body and source terminals, the PMOS body voltage must exceed Vdd, while the NMOS body voltage should be lower than Vgnd, which enhances the depletion layer width RBB is commonly utilized in memory cells to mitigate latch-up issues and protect memory data, effectively reducing subthreshold leakage and overall leakage current by increasing the body voltage However, its effectiveness in controlling leakage is diminished in short-channel and low-threshold devices.
Figure 2 13 Effect of reverse body bias on the depletion region and inversion layer charge in a MOSFET (a) A zero body biased NMOS transistor (b) A reverse body bi- ased NMOS transistor [8]
Change width method
This innovative approach utilizes voltage mode methodology to minimize voltage swing during write operations, resulting in increased interference voltage values at the bit line, word line (WL), and output compared to traditional SRAM cells These interference voltage levels can be effectively managed by adjusting the transistor's width (W) and channel length (L) Additionally, in standard SRAM cells, process variations can lead to data loss during read operations.
Figure 2 14 Width and Channel length in CMOS [10]
SYSTEM DESIGN
Block diagram of one-bit 6T SRAM structure
The block diagram design is divided into the following main blocks:
Figure 3 1 Block diagram of 6T SRAM 1 bit memory cell system
Control block
To manage data read/write operations in memory cells, a control block is essential This block features two inputs, Clk and W_R_en, and generates two outputs, Read_en and Write_en, to facilitate control over memory access.
Figure 3 2 Control block diagram allows reading/writing data
The circuit generates the Write_en output signal for the write driver and the Read_en output signal for the sensing amplifier, enabling data read and write operations It takes inputs W_R_en and pulse Clk; when W_R_en is set to 1 and pulse Clk is also 1, the Write_en output is activated.
= 1, then data will be written to memory cell 6T If input W_R_en = 0 and pulse Clk
= 1, output Read_en = 1, then the sensing amplifier circuit will sense the data to out- put the data to be read in memory
Figure 3 3 Schematic of control circuit
Based on table, we see the operating status of the control circuit that allows read- ing/writing data
Table 3 1 Truth table of control circuit operation
CLK W_R_en Write_en Read_en
Precharge block
The precharge circuit includes input signal lines such as Pre and has VDD to stim-
The circuit includes two signal lines, BL and BLB, which are essential for transmitting data to subsequent circuits during read and write operations, while also regulating the voltage to a high level.
The pre-charge block is an essential charge circuit for the bit lines (BL) and complementary bit lines (BLB) of memory cells before data reading or writing occurs when the clock signal is low (Clk = "0") During the writing process, to record a level "0" in the memory cell, the write driver block sets BL to "0" and BLB to "1." This simultaneous operation can extend the duration of the process Precharging is crucial as it ensures that the bit line voltage is stabilized at a midpoint level, facilitating efficient data operations.
The precharge circuit is designed to minimize propagation delay time by allowing the actual cell to be read as either "0" or "1" by driving the line from a midway voltage to the desired state Figure 3.8 illustrates the principle diagram of this circuit.
Figure 3 5 Schematic of precharge circuit
Sense amplifier block
The sense amplifier circuit features input signal pins including BL, BLB, and SE, along with an output pin labeled OUT This circuit serves as a reading mechanism for SRAM, enhancing data retrieval efficiency A block diagram illustrating the amplifier and sense circuit is also provided.
This circuit employs transistors (M1 and M2) along with a current mirror load (M3 and M4) and a biasing current source (M5) to effectively amplify the signal (SE) When the SE signal is activated, the sense amplifier compares the voltages on two lines (BL and BLB), enhancing the voltage difference to produce a clear output This mechanism significantly reduces the reading time of 6T SRAM, thereby improving its overall performance.
Figure 3 7 Schematic of sense amplifier circuit [11]
Write driver block
Figure 3 8 Write driver block Write driver circuit: this circuit helps control low bit streams during recording Its
The primary function of the 30 function is to swiftly discharge one of the bitstreams from the precharge level Typically, the data writing circuit is triggered by the Write_en signal from the control circuit This circuit utilizes two NMOS transistors configured as pass transistors, along with an inverter, as illustrated in figure 3.5 When Write_en is set to 1, the input data Din is transferred accordingly.
BL and the inverse of Din is moved to BLB
Figure 3 9 Schematic of write driver circuit Based on Table 3.2, we can see the operating status of the write driver circuit
Table 3 2 Table of write driver circuit
Latch block
This circuit is used for latching the input data in write operation For such func- tion, clock inverters are used for performing latching data
Based on Table , we can see the operating status of the write latch operation
Table 3 3 Table of latch operation
RESULTS
Control block
In Figure 4.1, we use 2 AND gates combined with a NOT gate 1 input signal that allows reading or writing WEN and 2 output signals including W_E, R_E
Then we create its symbol and layout in Figure 4.2 and Figure 4.3 Finally, we check DRC, LVS of those designs in Figure 4.4 and Figure 4.5 Finally, there aren’t any errors
Figure 4 4 Check DRC of control circuit
Figure 4 5 Check LVS of control circuit
When the clock (CLK) is at 0, both write enable (W_E) and read enable (R_E) are consistently 0, irrespective of the write enable not (WEN) status Conversely, when CLK is at 1, the values of W_E and R_E are contingent upon the WEN value; specifically, if WEN is 0, then W_E is 0 and R_E is 1, while if WEN is 1, W_E becomes 1 and R_E is 0 The waveform of this control block is illustrated in Figure 4.6.
Figure 4 6 Waveform of control block
Precharge block
This circuit employs three p-type transistors, with their signal pins connected to the Precharge pin (PRE) This configuration ensures that the BL and BLB signals remain balanced for a brief period when the Precharge pin is activated in a low state.
From the schematic, the Precharge’s symbol is shown in Figure 4.8 and its layout in Figure 4.9 The cellview is named PRECHARGE and has 4 pins:
- Bitlines pins: BL and BLB
In this section, we validate the Design Rule Check (DRC) and Layout Versus Schematic (LVS) for the designs presented in Figures 4.10 and 4.11, ensuring all errors are resolved Additionally, it is important to note that the Precharge circuit does not utilize the VSS input, resulting in one error related to the p-substrate.
Figure 4 10 Check DRC of precharge
Figure 4 11 Check LVS of precharge
Figure 4.12 show the waveform of precharge block When PRE = 1, BL and BLB are now in charging state and when PRE = 0, BL and BLB are in voltage balance state
Sense amplifier block
Sense amplifier circuit shown in Figure 4.13:
- When SE pin is enable, the sense amplifier circuit will be activated
- Inputs (BL and BLB) are fed to NM0 & NM2
- PM0 and PM1 act as the active mirror load
From the schematic, the sense amplifier’s symbol amd layout is created and shown in Figure 4.14 and Figure 4.15 The cellview is named sa and has 9 pins:
- Sensing bitlines pins: BL and BLB
- Sense Amplifier enable pins: SE
Ultimately, we ensure the designs meet DRC and LVS criteria in Figure 4.16 and Figure 4.17
Figure 4 16 Check DRC of sense amplifier
Figure 4 17 Check LVS of sense amplifier
In SRAM design, incorporating a sense amplifier is crucial for speeding up data retrieval from SRAM cells, as a design without it would lead to longer read times As shown in Figure 4.18, a minor voltage change in the bit line (BL) occurs when an SRAM bit cell stores a value of 0, causing the BL voltage to drop from 1V to 677.02 mV This voltage variation enables the reading of data from the SRAM bit cell, with D_O representing the retrieved data.
Figure 4 18 Waveform of sense amplifier
Write driver block
This circuit features two NMOS transistors integrated with two AND gates and one NOT gate, creating a Write driver circuit The input signals include the write enable pin (W_E) and the input data pin (DIN), while the output data is directed to the two pins, BL and BLB, as illustrated in Figure 4.19.
From the schematic, the write driver’s symbol which contains all input and outputs is created and is shown in Figure 4.20 The cellview is named WRITE_AMPLIFIER and has 6 pins:
- Write bitlines pins: BL and BLB
- Write data input pins: DIN
- Power pins: VDD and VSS
Figure 4 20 Write driver symbol Following that, Write driver layout is constructed in Figure 4.21:
Lastly, we perform DRC and LVS checks on these designs criteria in Figure 4.22 and Figure 4.23 No errors were founded
Figure 4 22 Check DRC of write driver
Figure 4 23 Check LVS of write driver
The waveform of the write driver, illustrated in Figure 4.24, is derived from the design and truth table discussed in Chapter 3 It demonstrates that when W_E is active at 1V, the values of BL_W and BLxW are contingent upon the DIN value Specifically, if DIN is set to 1, BL_W reflects this input.
When the signal BLxW is 1, NMOS transistor NM1 turns off while NMOS transistor NM0 turns on, leading to voltage levels of 1V on BL and 0V on BLB The current waveforms I_BL and I_BLB reflect the operations of NM1 and NM0, respectively Conversely, if the input DIN is 0, the functions of the transistors are reversed.
Figure 4 24 Waveform of write driver
Latch block
A D latch is built from a two-input multiplexer and two inverters is shown in Fig- ure 4.25
The latch's schematic symbol and layout, which includes all inputs and outputs, are illustrated in Figures 4.26 and 4.27 This cellview is designated as LATCH and features five pins.
- Power pins: VDD and VSS
Finally, the DRC and LVS of these designs are checked in Figure 4.28 and Figure 4.29 In the results, there are no errors
Figure 4 28 Check DRC of latch
Figure 4 29 Check LVS of latch
The waveform of the latch block illustrates the functioning of a data latch circuit, highlighting the CLK, D, and OUT signals When the CLK signal is high, the latch becomes transparent, enabling the output (OUT) to track the data input (D) Conversely, when the CLK signal is low, the latch retains the last value of D that was present during the high state, ensuring a stable output.
Design of 6T SRAM
Figure 4.31 illustrates the design of a memory cell using six transistors This de- sign is created by 4 NMOS transistors and 2 PMOS transistors
From the schematic, the 6T SRAM’s symbol and layout are created and presented in Figure 4.32 and Figure 4.33 The cellview contains 5 pins:
- Bitlines pins: BL and BLB
- Power pins: VDD and VSS
Finally, we check the DRC and LVS of these designs in Figure 4.34 and Figure 4.35 And there are no errors
Figure 4 34 Check DRC of SRAM
Figure 4 35 Check LVS of SRAM
Design of complete one-bit 6T SRAM structrure
Each function blocks after being created are assembled in a complete standard one-bit 6T SRAM shown in Figure 4.36
Figure 4 36 One-bit 6T SRAM schematic
The complete standard one-bit 6T SRAM schematic and the layout of its assembled blocks are utilized to create the overall layout of the SRAM This comprehensive layout is illustrated in Figure 4.37.
Figure 4 37 One-bit 6T SRAM layout
The process concludes with DRC and LVS verifications of the designs in Figure 4.38 and Figure 4.39 with no errors in the results
Figure 4 38 Check DRC of one-bit 6T SRAM
Figure 4 39 Check LVS of one-bit 6T SRAM
A comprehensive simulation of a standard one-bit 6T SRAM was conducted, as illustrated in the schematic, to analyze the waveform and verify the proper functioning of the 6T SRAM The waveform depicted in Figure 4.40 represents the behavior of a conventional 6T SRAM, highlighting its operational characteristics prior to vertical transitions.
The memory cell stores data represented by the waveforms of Q and Qx, with a value of 1 From vertical 1 to vertical 2, both CLK and WEN are set to 1, indicating a write operation, during which the DIN waveform shows a value of 0, resulting in the memory cell being written with the value 1 Following a brief delay after vertical 1, the Q value transitions from 1 to 0, confirming the successful operation of the memory cell From vertical 3 to vertical 4, while CLK remains at 1 and WEN drops to 0, the memory cell performs a read operation, during which the data is retrieved as indicated by the Q and Qx waveforms.
The 58 waveform indicates a read operation with a value of 0 from the memory cell Prior to vertical 3, the D_O value is 1, but after a brief delay following vertical 3, it transitions from 1 to 0, latching the data until the next read operation Between verticals 5 and 6, as well as between verticals 7 and 8, write and read operations occur, respectively, with a value of 1.
Figure 4 40 Waveform of SRAM’s operating process
The power consumption of 6T SRAM memory is assessed after confirming each read/write operation case Figure 4.41 illustrates the dynamic waveform during various read/write processes The average power is computed using the formula provided in equation (2.4).
Figure 4 41 Waveform of SRAM’s dynamic power
From Figure 4.41, the average dynamic power consumed by the 6T SRAM memory is shown in Figure 4.42
Figure 4 42 Calculating SRAM’s dynamic power
The evaluation of static power in memory is illustrated in Figure 4.44, alongside its dynamic power Static power is measured when the memory is idle, as depicted in Figure 4.43, by maintaining stable inputs while observing power consumption The average static power is calculated using equation (2.4), with results presented in Figure 4.44.
Figure 4 43 Waveform of SRAM’s static power
Figure 4 44 Calculating SRAM’s static power
Design of low-power 6T SRAM using power gating method
The power gating method effectively disconnects power from a circuit, eliminating leakage power when there is no supply voltage However, it is important to note that the gating circuit itself still experiences leakage To mitigate this, the write driver utilizing the power gating method incorporates high voltage threshold PMOS, NMOS, and inverters, as high voltage threshold CMOS technology exhibits lower leakage power compared to low voltage threshold CMOS When W_E is set to 0, PM0 and NM2 are deactivated, which disconnects buffer I3 from the circuit.
60 inverter I0 from the supply voltage When W_E is 1, buffer I3 and inverter I0 are re- connected to the supply voltage
Figure 4 45 Low-power 6T SRAM using power gating method schematic
The power consumption of the 6T SRAM memory is assessed after verifying each read/write operation case Figures 4.46 and 4.47 illustrate the average power consumed by the write driver, both with and without the implementation of the power gating method.
Figure 4 46 Calculating write driver’s static power without using power gating method
Figure 4 47 Calculating write driver’s static power using power gating method
Design of low-power 6T SRAM using MTCMOS method
To apply MTCMOS (Multi-threshold CMOS) method, 2 HVT (High-voltage thresh hold) PMOS and NMOS are attached to VDD and VSS pin of 6T SRAM re- spectively
Figure 4 48 Low-power 6T SRAM using MTCMOS method schematic
After verifying of each read/write operation cases, the power of the 6T SRAM memory is evaluated the average power consumed by the 6T SRAM memory is shown in Figure 4.49
Figure 4 49 Calculating SRAM’s dynamic power
In addition to dynamic power, the evaluation of static power in memory is crucial Static power is quantified using equation (2.4), with the results illustrated in Figure 4.50.
Figure 4 50 Calculating SRAM’s static power
Design of low-power 6T SRAM using reverse body bias method
In the 6T SRAM schematic utilizing the reverse bias method, the substrates of NMOS transistors NM5 and NM6 are connected to a positive bias source V1 of 0.5V instead of VSS Meanwhile, the substrates of the PMOS transistors are maintained at VDD, which is set to V2 = 1V.
Figure 4 51 Low-power 6T SRAM using reverse body bias method schematic
Figure 4 52 Setting value for V1 and V2
After verifying of each read/write operation cases, the power of the 6T SRAM memory is evaluated the average power consumed by the 6T SRAM memory is shown in Figure 4.53
Figure 4 53 Calculating SRAM’s dynamic power
In addition to dynamic power, the static power of the memory is assessed and quantified The static power is calculated using equation (2.4), with the results illustrated in Figure 4.54.
Figure 4 54 Calculating SRAM’s static power
Design of low-power 6T SRAM using change width method
The 6T SRAM schematic utilizes the change width method, where the widths of all six transistors are increased from 100 nm to 200 nm Furthermore, two additional NMOS transistors are incorporated, as referenced in source [6].
Figure 4 55 Low-power 6T SRAM using change width method schematic
After verifying of each read/write operation cases, the power of the 6T SRAM memory is evaluated the average power consumed by the 6T SRAM memory is shown in Figure 4.57
Figure 4 57 Calculating SRAM’s dynamic power
In addition to dynamic power, the article evaluates static power in memory systems, which is quantified using equation (2.4) The results of this assessment are illustrated in Figure 4.58.
Figure 4 58 Calculating SRAM’s static power
CONCLUSIONS
Conclusions
After simulating and calculating, values of SRAM’s power consumption are pre- sented in the Table 5.1:
Table 5 1 Comparing power parameters between each low-power 6T SRAM design
Type Dynamic power Static power
Figure 5 1 Comparing the dynamic power of four designs
Figure 5 2 Comparing the static power of four designs
MTCMOS Reverse body bias Change width Dynamic power (μW)
MTCMOS Reverse body bias Change widthStatic power(μW)
The bar charts in Figures 5.1 and 5.2 illustrate a significant difference in dynamic and static power consumption between a one-bit cell utilizing low-power techniques and a standard cell In practical applications, such as an SRAM array with a larger number of bit cells, even minor variations in power consumption can lead to substantial impacts on overall energy usage For instance, a computer chip featuring a 25MB cache shows a static power difference of about 0.55W between conventional SRAM and SRAM employing the MTCMOS method.
Table 5 2 Comparing power parameters between write driver of 6T SRAM using/without using low power gating method
Type Dynamic power Static power
Figure 5 3 Comparing the write driver’s dynamic power of 6T SRAM using/without us- ing low power gating method
Figure 5 4 Comparing the write driver’s static power of 6T SRAM using/without using power gating method
Conventional Write driver Power gating Write driver
Conventional Write driver Power gating Write driver
The bar charts in Figures 5.3 and 5.4 indicate a minor increase in the power dynamic of the write driver, approximately 0.4 μW In contrast, the leakage power of the standard 6T SRAM significantly decreases from 50.14 nW to 29.44 nW when utilizing a low power gating method.
The analysis of power management techniques for low-power 6T SRAM highlights the distinct advantages of four methods: power gating, MTCMOS, change width, and reverse body bias Among these, the change width technique stands out as the most effective for power reduction, while MTCMOS excels in dynamic power reduction, making it suitable for dynamic power-sensitive applications Although reverse body bias significantly lowers static power, it results in higher dynamic power consumption compared to standard 6T SRAM, limiting its use in high dynamic power scenarios Ultimately, the ultra CMOS technique offers an optimal balance for low-power SRAM design by minimizing static power, while MTCMOS remains the preferred choice for dynamic power reduction This study underscores the importance of selecting appropriate low-power strategies based on specific energy requirements and application contexts in SRAM design.
Further work
In our future plans, we aim to implement low-power techniques in larger 6T SRAM configurations, such as 64-bit and 1Kb, to better visualize their impact on power consumption Additionally, we will focus on evaluating other factors, including area, delay timing, temperature, and static noise margin, to understand how these elements interact with reduced power levels.
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